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| REJ09B0191-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SuperH TM SH7206 Group Hardware Manual Renesas 32-Bit RISC Microcomputer RISC engine Family / SH7200 Series R5S72060W200FPV SH7206 Rev.3.00 Revision Date: Jun. 18, 2008 Rev. 3.00 Jun. 18, 2008 Page ii of xxiv Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 3.00 Jun. 18, 2008 Page iii of xxiv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 3.00 Jun. 18, 2008 Page iv of xxiv Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix * Product Type, Package Dimensions, etc. 10. Main Revisions and Additions in This Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 3.00 Jun. 18, 2008 Page v of xxiv Preface This LSI is an RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users. Refer to the SH-2A, SH2A-FPU Software Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-2A, SH2A-FPU Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 24, List of Registers. Rev. 3.00 Jun. 18, 2008 Page vi of xxiv * Examples The notation used for register names, bit names, numbers, and symbols in this manual is described below. (1) Registers The style (register name)_(channel number) is used in cases where the same or a similar function is implemented on more than one channel. Example: CMCSR_0 (2) Bits When bit names are given in this manual, the higher-order bits are to the left and the lower-order bits are to the right. Example: CKS1, CKS0 (3) Numbers Binary numbers are given as B'xxxx, hexadecimal are given as H'xxxx, and decimal are given as xxxx. Examples: B'11 or 11, H'EFA0, 1234 (4) Symbols An overbar is added to the names of active-low signals. Example: WDTOVF (4) (1) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock.Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (2) (3) Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. Rev. 3.00 Jun. 18, 2008 Page vii of xxiv * Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Bit Chart] Bit: 15 14 13 12 11 10 0 R 9 1 R 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 Q 0 R/W 3 2 1 0 IFE ASID2 ASID1 ASID0 0 R/W 0 R/W 0 R/W ACMP2 ACMP1 ACMP0 0 R/W 0 R/W 0 R/W Initial value: R/W: 0 R/W 0 R/W 0 R/W [Table of Bits] (1) (2) (3) (4) (5) Bit 15 14 13 to 11 10 9 Bit Name - - ASID2 to ASID0 - - - Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R Description Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. All trademarks and registered trademarks are the property of their respective owners. Rev. 3.00 Jun. 18, 2008 Page viii of xxiv Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 1.5 SH7206 Features.................................................................................................................... 1 Block Diagram ....................................................................................................................... 7 Pin Arrangement .................................................................................................................... 8 Pin Functions ......................................................................................................................... 9 List of Pins ........................................................................................................................... 16 Section 2 CPU......................................................................................................29 2.1 Register Configuration......................................................................................................... 29 2.1.1 General Registers.................................................................................................... 29 2.1.2 Control Registers .................................................................................................... 30 2.1.3 System Registers..................................................................................................... 32 2.1.4 Register Banks ........................................................................................................ 33 2.1.5 Initial Values of Registers....................................................................................... 33 Data Formats........................................................................................................................ 34 2.2.1 Data Format in Registers ........................................................................................ 34 2.2.2 Data Formats in Memory ........................................................................................ 34 2.2.3 Immediate Data Format .......................................................................................... 35 Instruction Features.............................................................................................................. 36 2.3.1 RISC-Type Instruction Set...................................................................................... 36 2.3.2 Addressing Modes .................................................................................................. 40 2.3.3 Instruction Format................................................................................................... 45 Instruction Set ...................................................................................................................... 49 2.4.1 Instruction Set by Classification ............................................................................. 49 2.4.2 Data Transfer Instructions....................................................................................... 54 2.4.3 Arithmetic Operation Instructions .......................................................................... 58 2.4.4 Logic Operation Instructions .................................................................................. 61 2.4.5 Shift Instructions..................................................................................................... 62 2.4.6 Branch Instructions ................................................................................................. 63 2.4.7 System Control Instructions.................................................................................... 64 2.4.8 Bit Manipulation Instructions ................................................................................. 66 Processing States.................................................................................................................. 67 2.2 2.3 2.4 2.5 Section 3 Clock Pulse Generator (CPG)..............................................................69 3.1 3.2 Features................................................................................................................................ 69 Input/Output Pins ................................................................................................................. 73 Rev. 3.00 Jun. 18, 2008 Page ix of xxiv 3.3 3.4 3.5 3.6 Clock Operating Modes ....................................................................................................... 74 Register Descriptions........................................................................................................... 78 3.4.1 Frequency Control Register (FRQCR) ................................................................... 79 3.4.2 MTU Clock Frequency Control Register (MCLKCR) ........................................... 82 Changing the Frequency ...................................................................................................... 83 3.5.1 Changing the Multiplication Rate........................................................................... 83 3.5.2 Changing the Division Ratio................................................................................... 84 Notes on Board Design ........................................................................................................ 85 3.6.1 Note on Inputting External Clock ........................................................................... 85 3.6.2 Note on Using an External Crystal Resonator ........................................................ 85 3.6.3 Note on Resonator .................................................................................................. 86 3.6.4 Note on Bypass Capacitor....................................................................................... 86 3.6.5 Note on Using a PLL Oscillation Circuit................................................................ 86 Section 4 Exception Handling ............................................................................. 87 4.1 Overview.............................................................................................................................. 87 4.1.1 Types of Exception Handling and Priority ............................................................. 87 4.1.2 Exception Handling Operations.............................................................................. 89 4.1.3 Exception Handling Vector Table .......................................................................... 91 Resets................................................................................................................................... 93 4.2.1 Input/Output Pins.................................................................................................... 93 4.2.2 Types of Reset ........................................................................................................ 93 4.2.3 Power-On Reset ...................................................................................................... 94 4.2.4 Manual Reset .......................................................................................................... 96 Address Errors ..................................................................................................................... 97 4.3.1 Address Error Sources ............................................................................................ 97 4.3.2 Address Error Exception Handling......................................................................... 98 Register Bank Errors............................................................................................................ 99 4.4.1 Register Bank Error Sources................................................................................... 99 4.4.2 Register Bank Error Exception Handling ............................................................... 99 Interrupts............................................................................................................................ 100 4.5.1 Interrupt Sources................................................................................................... 100 4.5.2 Interrupt Priority Level ......................................................................................... 101 4.5.3 Interrupt Exception Handling ............................................................................... 102 Exceptions Triggered by Instructions ................................................................................ 103 4.6.1 Types of Exceptions Triggered by Instructions .................................................... 103 4.6.2 Trap Instructions................................................................................................... 104 4.6.3 Slot Illegal Instructions......................................................................................... 104 4.6.4 General Illegal Instructions................................................................................... 104 4.6.5 Integer Division Exceptions.................................................................................. 105 4.2 4.3 4.4 4.5 4.6 Rev. 3.00 Jun. 18, 2008 Page x of xxiv 4.7 4.8 4.9 When Exception Sources Are Not Accepted ..................................................................... 106 Stack Status after Exception Handling Ends...................................................................... 107 Usage Notes ....................................................................................................................... 109 4.9.1 Value of Stack Pointer (SP) .................................................................................. 109 4.9.2 Value of Vector Base Register (VBR) .................................................................. 109 4.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 109 Section 5 Interrupt Controller (INTC) ...............................................................111 5.1 5.2 5.3 Features.............................................................................................................................. 111 Input/Output Pins ............................................................................................................... 113 Register Descriptions ......................................................................................................... 114 5.3.1 Interrupt Priority Registers 01, 02, 05 to 14 (IPR01, IPR02, IPR05 to IPR14) .... 115 5.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 117 5.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 118 5.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 119 5.3.5 IRQ Interrupt Request Register (IRQRR)............................................................. 120 5.3.6 PINT Interrupt Enable Register (PINTER)........................................................... 122 5.3.7 PINT Interrupt Request Register (PIRR) .............................................................. 123 5.3.8 Bank Control Register (IBCR).............................................................................. 124 5.3.9 Bank Number Register (IBNR) ............................................................................ 125 Interrupt Sources................................................................................................................ 127 5.4.1 NMI Interrupt........................................................................................................ 127 5.4.2 User Break Interrupt ............................................................................................. 127 5.4.3 H-UDI Interrupt .................................................................................................... 127 5.4.4 IRQ Interrupts ....................................................................................................... 128 5.4.5 PINT Interrupts ..................................................................................................... 128 5.4.6 On-Chip Peripheral Module Interrupts ................................................................. 129 Interrupt Exception Handling Vector Table and Priority................................................... 130 Operation ........................................................................................................................... 139 5.6.1 Interrupt Operation Sequence ............................................................................... 139 5.6.2 Stack after Interrupt Exception Handling ............................................................. 142 Interrupt Response Time.................................................................................................... 143 Register Banks ................................................................................................................... 149 5.8.1 Banked Register and Input/Output of Banks ........................................................ 150 5.8.2 Bank Save and Restore Operations....................................................................... 150 5.8.3 Save and Restore Operations after Saving to All Banks....................................... 152 5.8.4 Register Bank Exception....................................................................................... 153 5.8.5 Register Bank Error Exception Handling ............................................................. 153 Data Transfer with Interrupt Request Signals .................................................................... 154 5.4 5.5 5.6 5.7 5.8 5.9 Rev. 3.00 Jun. 18, 2008 Page xi of xxiv Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC Activating ................................................................................................ 155 5.9.2 Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU Interrupt................................................................................................. 155 5.10 Usage Note......................................................................................................................... 156 5.10.1 Timing to Clear an Interrupt Source ..................................................................... 156 5.10.2 Timing of IRQOUT Negation............................................................................... 156 5.9.1 Section 6 User Break Controller (UBC)............................................................ 157 6.1 6.2 6.3 Features.............................................................................................................................. 157 Input/Output Pin ................................................................................................................ 159 Register Descriptions......................................................................................................... 160 6.3.1 Break Address Register (BAR)............................................................................. 161 6.3.2 Break Address Mask Register (BAMR) ............................................................... 162 6.3.3 Break Data Register (BDR) .................................................................................. 163 6.3.4 Break Data Mask Register (BDMR)..................................................................... 164 6.3.5 Break Bus Cycle Register (BBR) ......................................................................... 165 6.3.6 Break Control Register (BRCR) ........................................................................... 167 Operation ........................................................................................................................... 170 6.4.1 Flow of the User Break Operation ........................................................................ 170 6.4.2 Break on Instruction Fetch Cycle ......................................................................... 172 6.4.3 Break on Data Access Cycle................................................................................. 173 6.4.4 Value of Saved Program Counter ......................................................................... 174 6.4.5 Usage Examples.................................................................................................... 175 Usage Notes ....................................................................................................................... 178 6.4 6.5 Section 7 Cache ................................................................................................. 179 7.1 7.2 Features.............................................................................................................................. 179 7.1.1 Cache Structure..................................................................................................... 179 Register Descriptions......................................................................................................... 182 7.2.1 Cache Control Register 1 (CCR1) ........................................................................ 182 7.2.2 Cache Control Register 2 (CCR2) ........................................................................ 184 Operation ........................................................................................................................... 188 7.3.1 Searching Cache ................................................................................................... 188 7.3.2 Read Access.......................................................................................................... 190 7.3.3 Prefetch Operation (Only for Operand Cache) ..................................................... 190 7.3.4 Write Operation (Only for Operand Cache) ......................................................... 191 7.3.5 Write-Back Buffer (Only for Operand Cache) ..................................................... 191 7.3.6 Coherency of Cache and External Memory.......................................................... 193 Memory-Mapped Cache .................................................................................................... 194 7.3 7.4 Rev. 3.00 Jun. 18, 2008 Page xii of xxiv 7.4.1 7.4.2 7.4.3 7.4.4 Address Array ....................................................................................................... 194 Data Array ............................................................................................................ 195 Usage Examples.................................................................................................... 197 Notes ..................................................................................................................... 198 Section 8 Bus State Controller (BSC)................................................................199 8.1 8.2 8.3 Features.............................................................................................................................. 199 Input/Output Pins ............................................................................................................... 202 Area Overview ................................................................................................................... 204 8.3.1 Address Map ......................................................................................................... 204 8.3.2 Data Bus Width and Pin Function Setting in Each Area....................................... 205 Register Descriptions ......................................................................................................... 206 8.4.1 Common Control Register (CMNCR) .................................................................. 208 8.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 8) ..................................... 211 8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 8) .................................. 216 8.4.4 SDRAM Control Register (SDCR)....................................................................... 253 8.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 257 8.4.6 Refresh Timer Counter (RTCNT)......................................................................... 259 8.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 260 8.4.8 AC Characteristics Switching Register (ACSWR) ............................................... 261 8.4.9 AC Characteristics Switching Key Register (ACKEYR) ..................................... 262 8.4.10 Sequence to Write to ACSWR.............................................................................. 263 Operation ........................................................................................................................... 264 8.5.1 Endian/Access Size and Data Alignment.............................................................. 264 8.5.2 Normal Space Interface......................................................................................... 267 8.5.3 Access Wait Control ............................................................................................. 272 8.5.4 CSn Assert Period Expansion ............................................................................... 274 8.5.5 MPX-I/O Interface................................................................................................ 275 8.5.6 SDRAM Interface ................................................................................................. 279 8.5.7 Burst ROM (Clocked Asynchronous) Interface.................................................... 323 8.5.8 SRAM Interface with Byte Selection.................................................................... 325 8.5.9 PCMCIA Interface................................................................................................ 330 8.5.10 Burst MPX-I/O Interface ...................................................................................... 337 8.5.11 Burst ROM (Clocked Synchronous) Interface ...................................................... 342 8.5.12 Wait between Access Cycles ................................................................................ 343 8.5.13 Bus Arbitration ..................................................................................................... 350 8.5.14 Others.................................................................................................................... 352 Usage Notes ....................................................................................................................... 355 8.6.1 Burst ROM Interface ............................................................................................ 355 8.6.2 PCMCIA I/O Card Interface................................................................................. 355 Rev. 3.00 Jun. 18, 2008 Page xiii of xxiv 8.4 8.5 8.6 8.6.3 Burst MPX-I/O Interface ...................................................................................... 355 Section 9 Direct Memory Access Controller (DMAC)..................................... 357 9.1 9.2 9.3 Features.............................................................................................................................. 357 Input/Output Pins............................................................................................................... 360 Register Descriptions......................................................................................................... 361 9.3.1 DMA Source Address Registers (SAR)................................................................ 365 9.3.2 DMA Destination Address Registers (DAR)........................................................ 366 9.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 367 9.3.4 DMA Channel Control Registers (CHCR) ........................................................... 368 9.3.5 DMA Reload Source Address Registers (RSAR)................................................. 376 9.3.6 DMA Reload Destination Address Registers (RDAR)......................................... 377 9.3.7 DMA Reload Transfer Count Registers (RDMATCR) ........................................ 378 9.3.8 DMA Operation Register (DMAOR) ................................................................... 379 9.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).................. 383 Operation ........................................................................................................................... 385 9.4.1 Transfer Flow........................................................................................................ 385 9.4.2 DMA Transfer Requests ....................................................................................... 387 9.4.3 Channel Priority.................................................................................................... 391 9.4.4 DMA Transfer Types............................................................................................ 394 9.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing .................................... 403 Usage Notes ....................................................................................................................... 407 9.5.1 Setting of the Half-End Flag and Generation of the Half-End Interrupt............... 407 9.5.2 Timing of DACK and TEND Outputs .................................................................. 407 9.5.3 DREQ Sampling ................................................................................................... 407 9.4 9.5 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 413 10.1 Features.............................................................................................................................. 413 10.2 Input/Output Pins............................................................................................................... 419 10.3 Register Descriptions......................................................................................................... 420 10.3.1 Timer Control Register (TCR).............................................................................. 424 10.3.2 Timer Mode Register (TMDR)............................................................................. 428 10.3.3 Timer I/O Control Register (TIOR)...................................................................... 431 10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 450 10.3.5 Timer Interrupt Enable Register (TIER)............................................................... 451 10.3.6 Timer Status Register (TSR)................................................................................. 456 10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 464 10.3.8 Timer Input Capture Control Register (TICCR)................................................... 465 10.3.9 Timer Synchronous Clear Register (TSYCR) ...................................................... 466 10.3.10 Timer A/D Converter Start Request Control Register (TADCR) ......................... 468 Rev. 3.00 Jun. 18, 2008 Page xiv of xxiv 10.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4)...................................................................... 471 10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) ................................................................ 471 10.3.13 Timer Counter (TCNT)......................................................................................... 472 10.3.14 Timer General Register (TGR) ............................................................................. 472 10.3.15 Timer Start Register (TSTR) ................................................................................ 473 10.3.16 Timer Synchronous Register (TSYR)................................................................... 475 10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ..................................... 477 10.3.18 Timer Read/Write Enable Register (TRWER) ..................................................... 480 10.3.19 Timer Output Master Enable Register (TOER) .................................................... 481 10.3.20 Timer Output Control Register 1 (TOCR1) .......................................................... 482 10.3.21 Timer Output Control Register 2 (TOCR2) .......................................................... 485 10.3.22 Timer Output Level Buffer Register (TOLBR) .................................................... 488 10.3.23 Timer Gate Control Register (TGCR) .................................................................. 489 10.3.24 Timer Subcounter (TCNTS) ................................................................................. 491 10.3.25 Timer Dead Time Data Register (TDDR)............................................................. 492 10.3.26 Timer Cycle Data Register (TCDR) ..................................................................... 492 10.3.27 Timer Cycle Buffer Register (TCBR)................................................................... 493 10.3.28 Timer Interrupt Skipping Set Register (TITCR) ................................................... 493 10.3.29 Timer Interrupt Skipping Counter (TITCNT)....................................................... 495 10.3.30 Timer Buffer Transfer Set Register (TBTER) ...................................................... 496 10.3.31 Timer Dead Time Enable Register (TDER).......................................................... 498 10.3.32 Timer Waveform Control Register (TWCR) ........................................................ 499 10.3.33 Bus Master Interface............................................................................................. 501 10.4 Operation ........................................................................................................................... 502 10.4.1 Basic Functions..................................................................................................... 502 10.4.2 Synchronous Operation......................................................................................... 508 10.4.3 Buffer Operation ................................................................................................... 510 10.4.4 Cascaded Operation .............................................................................................. 514 10.4.5 PWM Modes ......................................................................................................... 519 10.4.6 Phase Counting Mode........................................................................................... 524 10.4.7 Reset-Synchronized PWM Mode.......................................................................... 531 10.4.8 Complementary PWM Mode................................................................................ 534 10.4.9 A/D Converter Start Request Delaying Function.................................................. 579 10.4.10 MTU2-MTU2S Synchronous Operation.............................................................. 583 10.4.11 External Pulse Width Measurement...................................................................... 589 10.4.12 Dead Time Compensation..................................................................................... 590 10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 593 10.5 Interrupt Sources................................................................................................................ 594 Rev. 3.00 Jun. 18, 2008 Page xv of xxiv 10.5.1 Interrupt Sources and Priorities ............................................................................ 594 10.5.2 DMAC Activation ................................................................................................ 596 10.5.3 A/D Converter Activation..................................................................................... 597 10.6 Operation Timing............................................................................................................... 599 10.6.1 Input/Output Timing............................................................................................. 599 10.6.2 Interrupt Signal Timing ........................................................................................ 606 10.7 Usage Notes ....................................................................................................................... 611 10.7.1 Module Standby Mode Setting ............................................................................. 611 10.7.2 Input Clock Restrictions ....................................................................................... 611 10.7.3 Caution on Period Setting ..................................................................................... 612 10.7.4 Contention between TCNT Write and Clear Operations...................................... 612 10.7.5 Contention between TCNT Write and Increment Operations............................... 613 10.7.6 Contention between TGR Write and Compare Match.......................................... 614 10.7.7 Contention between Buffer Register Write and Compare Match ......................... 615 10.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 616 10.7.9 Contention between TGR Read and Input Capture............................................... 617 10.7.10 Contention between TGR Write and Input Capture.............................................. 618 10.7.11 Contention between Buffer Register Write and Input Capture ............................. 619 10.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ...... 619 10.7.13 Counter Value during Complementary PWM Mode Stop .................................... 621 10.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 621 10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 622 10.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 623 10.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 624 10.7.18 Contention between TCNT Write and Overflow/Underflow................................ 625 10.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode.................................................................................... 625 10.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode..................................................................................................................... 626 10.7.21 Interrupts in Module Standby Mode ..................................................................... 626 10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 626 10.8 MTU2 Output Pin Initialization......................................................................................... 627 10.8.1 Operating Modes .................................................................................................. 627 10.8.2 Reset Start Operation ............................................................................................ 627 10.8.3 Operation in Case of Re-Setting Due to Error during Operation, Etc................... 628 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc............................................................................................ 629 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) .............................. 659 11.1 Input/Output Pins............................................................................................................... 663 Rev. 3.00 Jun. 18, 2008 Page xvi of xxiv 11.2 Register Descriptions ......................................................................................................... 664 Section 12 Port Output Enable 2 (POE2) ..........................................................667 12.1 Features.............................................................................................................................. 668 12.2 Input/Output Pins ............................................................................................................... 670 12.3 Register Descriptions ......................................................................................................... 672 12.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 673 12.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 677 12.3.3 Input Level Control/Status Register 2 (ICSR2) .................................................... 678 12.3.4 Output Level Control/Status Register 2 (OCSR2) ................................................ 682 12.3.5 Input Level Control/Status Register 3 (ICSR3) .................................................... 683 12.3.6 Software Port Output Enable Register (SPOER) .................................................. 685 12.3.7 Port Output Enable Control Register 1 (POECR1)............................................... 687 12.3.8 Port Output Enable Control Register 2 (POECR2)............................................... 688 12.4 Operation ........................................................................................................................... 693 12.4.1 Input Level Detection Operation........................................................................... 694 12.4.2 Output-Level Compare Operation ........................................................................ 695 12.4.3 Release from High-Impedance State..................................................................... 696 12.5 Interrupts............................................................................................................................ 697 Section 13 Compare Match Timer (CMT) ........................................................699 13.1 Features.............................................................................................................................. 699 13.2 Register Descriptions ......................................................................................................... 700 13.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 701 13.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 702 13.2.3 Compare Match Counter (CMCNT) ..................................................................... 704 13.2.4 Compare Match Constant Register (CMCOR) ..................................................... 704 13.3 Operation ........................................................................................................................... 705 13.3.1 Interval Count Operation ...................................................................................... 705 13.3.2 CMCNT Count Timing......................................................................................... 705 13.4 Interrupts............................................................................................................................ 706 13.4.1 Interrupt Sources and DMA Transfer Requests .................................................... 706 13.4.2 Timing of Compare Match Flag Setting ............................................................... 706 13.4.3 Timing of Compare Match Flag Clearing............................................................. 707 13.5 Usage Notes ....................................................................................................................... 708 13.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................... 708 13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 709 13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 710 13.5.4 Compare Match between CMCNT and CMCOR ................................................. 710 Rev. 3.00 Jun. 18, 2008 Page xvii of xxiv Section 14 Watchdog Timer (WDT) ................................................................. 711 14.1 Features.............................................................................................................................. 711 14.2 Input/Output Pin ................................................................................................................ 713 14.3 Register Descriptions......................................................................................................... 714 14.3.1 Watchdog Timer Counter (WTCNT).................................................................... 714 14.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 715 14.3.3 Watchdog Reset Control/Status Register (WRCSR) ............................................ 717 14.3.4 Notes on Register Access ..................................................................................... 718 14.4 WDT Usage ....................................................................................................................... 720 14.4.1 Canceling Software Standby Mode ...................................................................... 720 14.4.2 Changing the Frequency ....................................................................................... 721 14.4.3 Using Watchdog Timer Mode .............................................................................. 722 14.4.4 Using Interval Timer Mode .................................................................................. 724 14.5 Usage Notes ....................................................................................................................... 725 14.5.1 Timer Variation .................................................................................................... 725 14.5.2 Prohibition against Setting H'FF to WTCNT........................................................ 725 14.5.3 Interval Timer Overflow Flag............................................................................... 725 14.5.4 System Reset by WDTOVF Signal....................................................................... 726 14.5.5 Manual Reset in Watchdog Timer Mode.............................................................. 726 Section 15 Serial Communication Interface with FIFO (SCIF)........................ 727 15.1 Features.............................................................................................................................. 727 15.2 Input/Output Pins............................................................................................................... 729 15.3 Register Descriptions......................................................................................................... 730 15.3.1 Receive Shift Register (SCRSR) .......................................................................... 732 15.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 732 15.3.3 Transmit Shift Register (SCTSR) ......................................................................... 733 15.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 733 15.3.5 Serial Mode Register (SCSMR)............................................................................ 734 15.3.6 Serial Control Register (SCSCR).......................................................................... 737 15.3.7 Serial Status Register (SCFSR) ............................................................................ 741 15.3.8 Bit Rate Register (SCBRR) .................................................................................. 749 15.3.9 FIFO Control Register (SCFCR) .......................................................................... 756 15.3.10 FIFO Data Count Set Register (SCFDR).............................................................. 759 15.3.11 Serial Port Register (SCSPTR) ............................................................................. 760 15.3.12 Line Status Register (SCLSR) .............................................................................. 762 15.4 Operation ........................................................................................................................... 764 15.4.1 Overview .............................................................................................................. 764 15.4.2 Operation in Asynchronous Mode ........................................................................ 766 15.4.3 Operation in Clocked Synchronous Mode ............................................................ 777 Rev. 3.00 Jun. 18, 2008 Page xviii of xxiv 15.5 SCIF Interrupts .................................................................................................................. 786 15.6 Usage Notes ....................................................................................................................... 787 15.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 787 15.6.2 SCFRDR Reading and RDF Flag ......................................................................... 787 15.6.3 Restriction on DMAC Usage ................................................................................ 788 15.6.4 Break Detection and Processing ........................................................................... 788 15.6.5 Sending a Break Signal......................................................................................... 788 15.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 789 Section 16 I2C Bus Interface 3 (IIC3) ................................................................791 16.1 Features.............................................................................................................................. 791 16.2 Input/Output Pins ............................................................................................................... 793 16.3 Register Descriptions ......................................................................................................... 794 16.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 795 16.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 798 16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 800 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 802 16.3.5 I2C Bus Status Register (ICSR)............................................................................. 804 16.3.6 Slave Address Register (SAR).............................................................................. 807 16.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 807 16.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 808 16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 808 16.3.10 NF2CYC Register (NF2CYC) .............................................................................. 809 16.4 Operation ........................................................................................................................... 810 16.4.1 I2C Bus Format...................................................................................................... 810 16.4.2 Master Transmit Operation ................................................................................... 811 16.4.3 Master Receive Operation..................................................................................... 813 16.4.4 Slave Transmit Operation ..................................................................................... 815 16.4.5 Slave Receive Operation....................................................................................... 818 16.4.6 Clocked Synchronous Serial Format..................................................................... 820 16.4.7 Noise Filter ........................................................................................................... 824 16.4.8 Example of Use..................................................................................................... 825 16.5 Interrupt Requests .............................................................................................................. 829 16.6 Bit Synchronous Circuit..................................................................................................... 830 16.7 Usage Notes ....................................................................................................................... 833 16.7.1 Note on Issue of Stop/Start Conditions................................................................. 833 16.7.2 Settings for Multi-Master Operation..................................................................... 833 16.7.3 Note on Master Receive Mode.............................................................................. 833 16.7.4 Note on Setting ACKBT in Master Receive Mode............................................... 834 16.7.5 Note on the States of Bits MST and TRN when Arbitration is Lost..................... 834 Rev. 3.00 Jun. 18, 2008 Page xix of xxiv Section 17 A/D Converter (ADC) ..................................................................... 835 17.1 Features.............................................................................................................................. 835 17.2 Input/Output Pins............................................................................................................... 837 17.3 Register Descriptions......................................................................................................... 838 17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 839 17.3.2 A/D Control/Status Register (ADCSR) ................................................................ 840 17.3.3 A/D0, A/D1 Control Register (ADCR) ................................................................ 844 17.4 Operation ........................................................................................................................... 845 17.4.1 Single Mode.......................................................................................................... 845 17.4.2 Multi Mode ........................................................................................................... 848 17.4.3 Scan Mode ............................................................................................................ 850 17.4.4 Simultaneous Sampling Operation ....................................................................... 853 17.4.5 A/D Converter Activation by External Trigger, MTU2, or MTU2S .................... 853 17.4.6 Input Sampling and A/D Conversion Time .......................................................... 853 17.4.7 External Trigger Input Timing.............................................................................. 855 17.5 Interrupt Sources and DMAC Transfer Request ................................................................ 856 17.6 Definitions of A/D Conversion Accuracy.......................................................................... 857 17.7 Usage Notes ....................................................................................................................... 858 17.7.1 Module Standby Mode Setting ............................................................................. 858 17.7.2 Setting Analog Input Voltage ............................................................................... 858 17.7.3 Notes on Board Design ......................................................................................... 858 17.7.4 Processing of Analog Input Pins........................................................................... 859 17.7.5 Permissible Signal Source Impedance .................................................................. 860 17.7.6 Influences on Absolute Precision.......................................................................... 861 17.7.7 Note on Usage in Scan Mode and Multi Mode..................................................... 861 Section 18 D/A Converter (DAC) ..................................................................... 863 18.1 Features.............................................................................................................................. 863 18.2 Input/Output Pins............................................................................................................... 864 18.3 Register Descriptions......................................................................................................... 865 18.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 865 18.3.2 D/A Control Register (DACR) ............................................................................. 866 18.4 Operation ........................................................................................................................... 868 18.5 Usage Notes ....................................................................................................................... 869 18.5.1 Module Standby Mode Setting ............................................................................. 869 18.5.2 D/A Output Hold Function in Software Standby Mode........................................ 869 18.5.3 Setting Analog Input Voltage ............................................................................... 869 Section 19 Pin Function Controller (PFC) ........................................................ 871 19.1 Features.............................................................................................................................. 875 Rev. 3.00 Jun. 18, 2008 Page xx of xxiv 19.2 Register Descriptions ......................................................................................................... 876 19.2.1 Port A I/O Registers H, L (PAIORH, PAIORL)................................................... 878 19.2.2 Port A Control Registers H1 to H3, L1 to L4 (PACRH1 to PACRH3, PACRL1 to PACRL4) ................................................... 879 19.2.3 Port B I/O Register (PBIOR) ................................................................................ 892 19.2.4 Port B Control Registers 1 to 3 (PBCR1 to PBCR3) ............................................ 892 19.2.5 Port C I/O Register L (PCIORL) .......................................................................... 897 19.2.6 Port C Control Register L1 (PCCRL1) ................................................................. 897 19.2.7 Port D I/O Registers H, L (PDIORH, PDIORL)................................................... 899 19.2.8 Port D Control Registers H1 to H4, L3, L4 (PDCRH1 to PDCRH4, PDCRL3, PDCRL4)....................................................... 900 19.2.9 Port E I/O Registers H, L (PEIORH, PEIORL) .................................................... 926 19.2.10 Port E Control Registers H1, L1 to L4 (PECRH1, PECRL1 to PECRL4) ........... 927 19.2.11 IRQOUT Function Control Register (IFCR) ........................................................ 936 19.3 Switching of Functions in Each Pin ................................................................................... 937 19.3.1 Ports A, B, C, D, and E ......................................................................................... 937 19.3.2 Port F .................................................................................................................... 943 19.4 Usage Notes ....................................................................................................................... 944 Section 20 I/O Ports ...........................................................................................945 20.1 Features.............................................................................................................................. 945 20.2 Port A................................................................................................................................. 946 20.2.1 Register Descriptions............................................................................................ 947 20.2.2 Port A Data Registers H, L (PADRH, PADRL) ................................................... 947 20.2.3 Port A Port Registers H, L (PAPRH, PAPRL) ..................................................... 951 20.3 Port B ................................................................................................................................. 953 20.3.1 Register Descriptions............................................................................................ 953 20.3.2 Port B Data Register (PBDR) ............................................................................... 954 20.3.3 Port B Port Register (PBPR)................................................................................. 956 20.4 Port C ................................................................................................................................. 957 20.4.1 Register Descriptions............................................................................................ 957 20.4.2 Port C Data Register L (PCDRL) ......................................................................... 958 20.4.3 Port C Port Register L (PCPRL) ........................................................................... 959 20.5 Port D................................................................................................................................. 960 20.5.1 Register Descriptions............................................................................................ 960 20.5.2 Port D Data Registers H, L (PDDRH, PDDRL) ................................................... 961 20.5.3 Port D Port Registers H, L (PDPRH, PDPRL) ..................................................... 964 20.6 Port E ................................................................................................................................. 966 20.6.1 Register Descriptions............................................................................................ 966 20.6.2 Port E Data Registers H, L (PEDRH, PEDRL) .................................................... 967 Rev. 3.00 Jun. 18, 2008 Page xxi of xxiv 20.6.3 Port E Port Registers H, L (PEPRH, PEPRL)....................................................... 969 20.7 Port F ................................................................................................................................. 971 20.7.1 Register Descriptions............................................................................................ 971 20.7.2 Port F Data Register (PFDR) ................................................................................ 972 20.8 Usage Notes ....................................................................................................................... 974 Section 21 On-Chip RAM ................................................................................. 975 21.1 Features.............................................................................................................................. 975 21.2 Usage Notes ....................................................................................................................... 976 21.2.1 Page Conflict ........................................................................................................ 976 21.2.2 RAME and RAMWE Bits .................................................................................... 976 Section 22 Power-Down Modes........................................................................ 977 22.1 Features.............................................................................................................................. 977 22.1.1 Power-Down Modes ............................................................................................. 977 22.2 Register Descriptions......................................................................................................... 979 22.2.1 Standby Control Register (STBCR)...................................................................... 980 22.2.2 Standby Control Register 2 (STBCR2)................................................................. 981 22.2.3 Standby Control Register 3 (STBCR3)................................................................. 982 22.2.4 Standby Control Register 4 (STBCR4)................................................................. 984 22.2.5 System Control Register 1 (SYSCR1) .................................................................. 986 22.2.6 System Control Register 2 (SYSCR2) .................................................................. 988 22.3 Operation ........................................................................................................................... 990 22.3.1 Sleep Mode ........................................................................................................... 990 22.3.2 Software Standby Mode........................................................................................ 990 22.3.3 Software Standby Mode Application Example..................................................... 993 22.3.4 Module Standby Function..................................................................................... 994 22.4 Usage Notes ....................................................................................................................... 995 22.4.1 Note on Writing to Registers ................................................................................ 995 Section 23 High-Performance User Debugging Interface (H-UDI)................. 997 23.1 Features.............................................................................................................................. 997 23.2 Input/Output Pins............................................................................................................... 998 23.3 Register Descriptions......................................................................................................... 999 23.3.1 Bypass Register (SDBPR) .................................................................................... 999 23.3.2 Instruction Register (SDIR) .................................................................................. 999 23.4 Operation ......................................................................................................................... 1001 23.4.1 TAP Controller ................................................................................................... 1001 23.4.2 Reset Configuration ............................................................................................ 1002 23.4.3 TDO Output Timing ........................................................................................... 1002 Rev. 3.00 Jun. 18, 2008 Page xxii of xxiv 23.4.4 H-UDI Reset ....................................................................................................... 1003 23.4.5 H-UDI Interrupt .................................................................................................. 1003 23.5 Usage Notes ..................................................................................................................... 1004 Section 24 List of Registers .............................................................................1005 24.1 Register Addresses (by functional module, in order of the corresponding section numbers).......................... 1006 24.2 Register Bits..................................................................................................................... 1021 24.3 Register States in Each Operating Mode ......................................................................... 1052 Section 25 Electrical Characteristics ...............................................................1067 25.1 25.2 25.3 25.4 Absolute Maximum Ratings ............................................................................................ 1067 Power-On/Power-Off Sequence....................................................................................... 1068 DC Characteristics ........................................................................................................... 1069 AC Characteristics ........................................................................................................... 1073 25.4.1 Clock Timing ...................................................................................................... 1074 25.4.2 Control Signal Timing ........................................................................................ 1077 25.4.3 Bus Timing ......................................................................................................... 1080 25.4.4 UBC Trigger Timing .......................................................................................... 1115 25.4.5 DMAC Module Timing ...................................................................................... 1115 25.4.6 MTU2, MTU2S Module Timing ........................................................................ 1117 25.4.7 POE2 Module Timing......................................................................................... 1118 25.4.8 Watchdog Timer Timing..................................................................................... 1118 25.4.9 SCIF Module Timing.......................................................................................... 1119 25.4.10 IIC3 Module Timing........................................................................................... 1120 25.4.11 A/D Trigger Input Timing .................................................................................. 1121 25.4.12 I/O Port Timing................................................................................................... 1122 25.4.13 H-UDI Related Pin Timing................................................................................. 1123 25.4.14 AC Characteristics Measurement Conditions ..................................................... 1125 25.5 A/D Converter Characteristics ......................................................................................... 1126 25.6 D/A Converter Characteristics ......................................................................................... 1127 Appendix ...........................................................................................................1129 A. B. C. Pin States.......................................................................................................................... 1129 Product Lineup................................................................................................................. 1134 Package Dimensions ........................................................................................................ 1135 Main Revisions and Additions in This Edition..................................................1137 Index .................................................................................................................1153 Rev. 3.00 Jun. 18, 2008 Page xxiii of xxiv Rev. 3.00 Jun. 18, 2008 Page xxiv of xxiv Section 1 Overview Section 1 Overview 1.1 SH7206 Features This LSI is a single-chip RISC (Reduced Instruction Set Computer) microprocessor that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type instruction set and uses a superscalar architecture and a Harvard architecture, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microprocessors, such as realtime control, which demands high speeds. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a cache, a large-capacity RAM, a direct memory access controller (DMAC), multifunction timer pulse units 2 (MTU2 and MTU2S), a serial communication interface with FIFO (SCIF), an A/D converter, a D/A converter, an interrupt controller (INTC), I/O ports, and I2C bus interface 3 (IIC3). This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. Furthermore, I/O pins in this LSI have weak keeper circuits that prevent the pin voltage from entering an intermediate potential range. Therefore, no external circuits to fix the input level are required, which reduces the parts number considerably. The features of this LSI are listed in table 1.1. Rev. 3.00 Jun. 18, 2008 Page 1 of 1160 REJ09B0191-0300 Section 1 Overview Table 1.1 Items CPU SH7206 Features Specification * * * * Renesas Technology original SuperH architecture Compatible with SH-1 and SH-2 at object code level 32-bit internal data bus Support of an abundant register-set Sixteen 32-bit general registers Four 32-bit control registers Four 32-bit system registers Register bank for high-speed response to interrupts * RISC-type instruction set (upward compatible with SH series) Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability Load/store architecture Delayed branch instructions Instruction set based on C language * * * * * * Superscalar architecture to execute two instructions at one time Instruction execution time: Up to two instructions/cycle Address space: 4 Gbytes Internal multiplier Five-stage pipeline Harvard architecture Rev. 3.00 Jun. 18, 2008 Page 2 of 1160 REJ09B0191-0300 Section 1 Overview Items Cache memory Specification * * * * * Instruction cache: 8 Kbytes Operand cache: 8 Kbytes 128-entry/way, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache Write-back, write-through, LRU replacement algorithm Way lock function available (only for operand cache); ways 2 and 3 can be locked Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to PINT0) On-chip peripheral interrupts: Priority level set for each module 16 priority levels available Register bank enabling fast register saving and restoring in interrupt processing Address space divided into nine areas (0 to 8), each a maximum of 64 Mbytes The following features settable for each area independently Bus size (8, 16, or 32 bits): Available sizes depend on the area. Number of access wait cycles (different wait cycles can be specified for read and write access cycles in some areas) Idle wait cycle insertion (between same area access cycles or different area access cycles) Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or asynchronous). The address/data multiplexed I/O (MPX) interface and burst MPX-I/O interface are also available. PCMCIA interface Outputs a chip select signal (CS0 to CS8) according to the target area (CS assert or negate timing can be selected by software) * * SDRAM refresh Auto refresh or self refresh mode selectable SDRAM burst access Interrupt controller (INTC) * * * * Bus state controller (BSC) * * Rev. 3.00 Jun. 18, 2008 Page 3 of 1160 REJ09B0191-0300 Section 1 Overview Items Specification Eight channels; external request available for four of them Can be activated by on-chip peripheral modules Burst mode and cycle steal mode Intermittent mode available (16 and 64 cycles supported) Transfer information can be automatically reloaded Clock mode: Input clock can be selected from external input (EXTAL or CKIO) or crystal resonator Input clock can be multiplied by 16 (max.) by the internal PLL circuit Four types of clocks generated: CPU clock: Maximum 200 MHz Bus clock: Maximum 66 MHz Peripheral clock: Maximum 33 MHz MTU clock: Maximum 100 MHz Direct memory access * controller (DMAC) * * * * Clock pulse generator (CPG) * * * Watchdog timer (WDT) Power-down modes * * * On-chip one-channel watchdog timer A counter overflow can reset the LSI Three power-down modes provided to reduce the current consumption in this LSI Sleep mode Software standby mode Module standby mode Rev. 3.00 Jun. 18, 2008 Page 4 of 1160 REJ09B0191-0300 Section 1 Overview Items Multi-function timer pulse unit 2 (MTU2) Specification * * * * Maximum 16 lines of pulse input/output and 3 lines of pulse input based on six channels of 16-bit timers 21 output compare and input capture registers Input capture function Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes * * Synchronization of multiple counters Complementary PWM output mode Non-overlapping waveforms output for 3-phase inverter control Automatic dead time setting 0% to 100% PWM duty value specifiable A/D conversion delaying function Interrupt skipping at crest or trough * Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty value * Phase counting mode Two-phase encoder pulse counting available Subset of MTU2, included in channels 3 to 5 Operating at 100 MHz max. High-impedance control of high-current pins at a falling edge or lowlevel input on the POE pin Two-channel 16-bit counters Four types of clock can be selected (P/8, P/32, P/128, and P/512) DMA transfer request or interrupt request can be issued when a compare match occurs Four channels Clocked synchronous or asynchronous mode selectable Simultaneous transmission and reception (full-duplex communication) supported Dedicated baud rate generator Separate 16-stage FIFO registers for transmission and reception Modem control function (in asynchronous mode) Multi-function timer * pulse unit 2S (MTU2S) * Port output enable 2 (POE2) * Compare match timer * (CMT) * * Serial communication interface with FIFO (SCIF) * * * * * * Rev. 3.00 Jun. 18, 2008 Page 5 of 1160 REJ09B0191-0300 Section 1 Overview Items I C bus interface 3 (IIC3) I/O ports A/D converter (ADC) 2 Specification * * * * * * * * One channel Master mode and slave mode supported Input or output can be selected for each bit Internal weak keeper circuit 10-bit resolution Eight input channels Conversion can be carried out simultaneously on two channels. A/D conversion request by the external trigger or timer trigger 8-bit resolution Two output channels Two break channels Addresses, data values, type of access, and data size can all be set as break conditions E10A emulator support JTAG-standard pin assignment Four pages 128-Kbyte large-capacity memory Vcc: 1.15 to 1.35 V PVcc: 3.0 to 3.6 V LQFP2424-176Cu (0.5 pitch) D/A converter (DAC) User break controller (UBC) * * * * * * * * * * * High-performance user debugging interface (H-UDI) On-chip RAM Power supply voltage Packages Rev. 3.00 Jun. 18, 2008 Page 6 of 1160 REJ09B0191-0300 Section 1 Overview 1.2 Block Diagram SH-2A CPU core CPU instruction fetch bus (F bus) CPU bus (C bus) (I clock) CPU memory access bus (M bus) Cache controller Instruction cache memory 8 Kbytes Operand cache memory 8 Kbytes On-chip RAM 128 Kbytes User break controller (UBC) Port Port output enable 2 (POE2) Port POE input Serial communication interface with FIFO (SCIF) UBCTRG output Internal bus (I bus) (B clock) Bus state controller (BSC) Peripheral bus controller Direct memory access controller (DMAC) DREQ input DACK output TEND output Port External bus input/output External bus width mode input Peripheral bus (P clock) Pin function controller (PFC) I/O ports Clock pulse generator (CPG) Interrupt controller (INTC) Multi-function timer pulse unit 2 (MTU2) Multi-function timer pulse unit 2 subset (MTU2S) Port General input/output Port EXTAL input, XTAL output, CKIO input/output, Clock mode input Port RES input, MRES input, NMI input, IRQ input, PINT input, IRQOUT output Port Timer pulse input/output Port Timer pulse input/output High-performance user debugging interface (H-UDI) Power-down mode control D/A converter (DAC) A/D converter (ADC) I2C bus interface 3 (IIC3) Port JTAG input/output Port Analog output Port Analog input, ADTRG input Port Port Compare match timer (CMT) Watchdog timer (WDT) Port I2C bus input/output Port WDTOVF output Serial input/output Figure 1.1 Block Diagram Rev. 3.00 Jun. 18, 2008 Page 7 of 1160 REJ09B0191-0300 Section 1 Overview 1.3 Pin Arrangement D23/IRQ7/AUDSYNC/PD23 PVcc D24/DREQ0/TIOC4DS/PD24 D25/DREQ1/TIOC4CS/PD25 D26/DACK0/TIOC4BS/PD26 D27/DACK1/TIOC4AS/PD27 PVss PVcc D28/CS2/TIOC3DS/PD28 D29/CS3/TIOC3BS/PD29 D30/TIOC3CS/IRQOUT/PD30 D31/TIOC3AS/ADTRG/PD31 TDO ASEMD PVss PVcc TMS Vcc Vss PVss TDI TRST TCK BACK/TEND1/PINT3/PA19 PVcc ASEBCK WDTOVF TxD3/TIOC4A/PE12 ASEBRKAK/ASEBRK RxD3/TIOC3D/CTS3/PE11 Vss Vcc TxD2/TIOC3C/PE10 AVcc AVref AN7/DA1/PF7 AN6/DA0/PF6 AN5/PF5 AN4/PF4 AN3/PF3 AN2/PF2 AN1/PF1 AN0/PF0 AVss 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 Rev. 3.00 Jun. 18, 2008 Page 8 of 1160 REJ09B0191-0300 RD RDWR/IRQ2/TCLKC/PA8 PVss A1/PC1 A2 A3 A4 A5 A6 A7 A8 A9 Vcc Vss PVss PVcc A10 A11 A12 A13 A14 A15 A16 Vcc Vss A17 A18 A19 A20 BREQ/TEND0/PINT2/PA18 PVcc CKIO PVss PLLVss PLLVcc PVcc RES PVss XTAL EXTAL PVss PVcc NMI PVss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PVss D22/IRQ6/TIC5US/AUDCK/PD22 D21/IRQ5/TIC5VS/PD21 D20/IRQ4/TIC5WS/PD20 D19/IRQ3/POE7/AUDATA3/PD19 D18/IRQ2/POE6/AUDATA2/PD18 D17/IRQ1/POE5/AUDATA1/PD17 D16/IRQ0/POE4/AUDATA0/PD16 D15/TIOC4DS/PD15 D14/TIOC4CS/PD14 D13/TIOC4BS/PD13 Vss Vcc D12/TIOC4AS/PD12 PVss D11/TIOC3DS/PD11 PVcc D10/TIOC3CS/PD10 D9/TIOC3BS/PD9 D8/TIOC3AS/PD8 D7 D6 D5 D4 D3 Vss Vcc D2 D1 PVss PVcc D0 CASU/PINT5/CS5/CE1A/TIC5U/PA21 CASL/IRQ3/POE3/PB5 WE3/ICIOWR/AH/DQMUU/DREQ2/CKE/AUDSYNC/PA16 CS2/TCLKA/PA6 CS3/TCLKB/PA7 WE3/ICIOWR/AH/DQMUU/TIC5W/PA23 WE2/ICIORD/DQMUL/TIC5V/PA22 WE1/WE/DQMLU/POE7/PA13 WE0/DQMLL/POE6/PA12 RASL/IRQ2/POE2/PB4 RASU/PINT4/CS4/PA20 PVcc 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 LQFP-176 (Top view) 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 WE3/ICIOWR/AH/DQMUU/DACK0/TIOC4C/PE14 DREQ1/TIOC0C/PE2 IOIS16/RxD3/TIOC1A/AUDATA2/PE4 CS4/PINT0/RxD0/PA0 CS7/SCK3/TIOC2A/AUDATA0/PE6 TEND0/TIOC0B/PE1 CS6/CE1B/TxD3/TIOC1B/AUDATA1/PE5 CS5/CE1A/PINT1/TxD0/PA1 TEND1/TIOC0D/AUDATA3/PE3 Vcc Vss PVss PVcc DREQ0/TIOC0A/AUDCK/PE0 BS/RxD2/TIOC2B/UBCTRG/PE7 IRQ0/POE0/SCL/PB2 IRQ1/POE1/SDA/PB3 CE2B/DACK3/PINT7/POE8/PA25 CE2A/DREQ3/PINT6/PA24 SCK2/TIOC3A/PE8 CS1/POE5/PA11 CS0 MRES/TIOC4B/PE13 PVss PVss PVcc WAIT/DACK2/PA17 SCK3/TIOC3B/RTS3/PE9 FRAME/CKE/TCLKD/IRQ3/PA9 MD0 MD2 Vcc Vss MD_CLK0 MD_CLK2 DACK1/CKE/TIOC4D/IRQOUT/PE15 CS8/PE16 A0/PC0 A25/DREQ0/IRQ0/SCK0/PA2 A24/RxD1/PA3 A23/TxD1/PA4 A22/DREQ1/IRQ1/SCK1/PA5 A21/IRQ7/ADTRG/POE8/PB9 PVss Figure 1.2 Pin Arrangement Section 1 Overview 1.4 Table 1.2 Pin Functions Pin Functions Symbol Vcc I/O I Name Power supply Function Power supply pins. All the Vcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Ground pins. All the Vss pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. Classification Power supply Vss I Ground PVcc I Power supply for Power supply for I/O pins. All the I/O circuits PVcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Ground for I/O circuits Ground pins for I/O pins. All the PVss pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. PVss I PLLVcc PLLVss Clock EXTAL I I I Power supply for Power supply for the on-chip PLL PLL oscillator. Ground for PLL External clock Ground pin for the on-chip PLL oscillator. Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. Connected to a crystal resonator. XTAL CKIO O I/O Crystal System clock I/O Inputs an external clock or supplies the system clock to external devices. Rev. 3.00 Jun. 18, 2008 Page 9 of 1160 REJ09B0191-0300 Section 1 Overview Classification Operating mode control Symbol MD2, MD0 I/O I Name Mode set Function Sets the operating mode. Do not change the signal levels on these pins during operation. Sets the clock operating mode. Do not change the signal levels on these pins during operation. If a low level is input at the ASEMD pin while the RES pin is asserted, ASE mode is entered; if a high level is input, product chip mode is entered. In ASE mode, the emulator function is enabled. When this function is not in use, fix it high. MD_CLK2, MD_CLK0 ASEMD I Clock mode set I ASE mode System control RES MRES WDTOVF BREQ I I O I Power-on reset Manual reset Watchdog timer overflow Bus-mastership request Bus-mastership request acknowledge This LSI enters the power-on reset state when this signal goes low. This LSI enters the manual reset state when this signal goes low. Outputs an overflow signal from the WDT. A low level is input to this pin when an external device requests the release of the bus mastership. Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus. BACK O Rev. 3.00 Jun. 18, 2008 Page 10 of 1160 REJ09B0191-0300 Section 1 Overview Classification Interrupts Symbol NMI IRQ7 to IRQ0 I/O I I Name Non-maskable interrupt Function Non-maskable interrupt request pin. Fix it high when not in use. Interrupt requests Maskable interrupt request pins. 7 to 0 Level-input or edge-input detection can be selected. When the edgeinput detection is selected, the rising edge, falling edge, or both edges can also be selected. Interrupt requests Maskable interrupt request pins. 7 to 0 Only level-input detection can be selected. Interrupt request Indicates that an interrupt has output occurred, enabling external devices to be informed of an interrupt occurrence even while the bus mastership is released. Address bus Data bus Outputs addresses. Bidirectional data bus. PINT7 to PINT0 I IRQOUT O Address bus Data bus Bus control A25 to A0 D31 to D0 CS8 to CS0 RD RD/WR BS AH O I/O O O O O O Chip select 8 to 0 Chip-select signals for external memory or devices. Read Read/write Bus start Address hold Indicates that data is read from an external device. Read/write signal. Bus-cycle start signal. Address hold timing signal for the device that uses the address/datamultiplexed bus. Connected to the FRAME signal in the burst MPX-I/O interface. Input signal for inserting a wait cycle into the bus cycles during access to the external space. Indicates a write access to bits 7 to 0 of data of external memory or device. FRAME WAIT O I FRAME signal Wait WE0 O Byte select Rev. 3.00 Jun. 18, 2008 Page 11 of 1160 REJ09B0191-0300 Section 1 Overview Classification Bus control Symbol WE1 I/O O Name Byte select Function Indicates a write access to bits 15 to 8 of data of external memory or device. Indicates a write access to bits 23 to 16 of data of external memory or device. Indicates a write access to bits 31 to 24 of data of external memory or device. Selects bits D7 to D0 when SDRAM is connected. Selects bits D15 to D8 when SDRAM is connected. Selects bits D23 to D16 when SDRAM is connected. Selects bits D31 to D24 when SDRAM is connected. Connected to the RAS pin when SDRAM is connected. Connected to the CAS pin when SDRAM is connected. Connected to the CKE pin when SDRAM is connected. WE2 O Byte select WE3 O Byte select DQMLL DQMLU DQMUL DQMUU RASU, RASL CASU, CASL CKE CE1A, CE1B CE2A, CE2B ICIOWR ICIORD WE IOIS16 REFOUT O O O O O O O O O O O O I O Byte select Byte select Byte select Byte select RAS CAS CK enable Lower byte select Connected to PCMCIA card select for PCMCIA card signals D7 to D0. Upper byte select Connected to PCMCIA card select for PCMCIA card signals D15 to D8. Write strobe for PCMCIA I/O Read strobe for PCMCIA I/O Connected to the PCMCIA I/O write strobe signal. Connected to the PCMCIA I/O read strobe signal. Write strobe for Connected to the PCMCIA memory PCMCIA memory write strobe signal. PCMCIA dynamic Fix it low. bus sizing Refresh request Request signal for refresh execution. Rev. 3.00 Jun. 18, 2008 Page 12 of 1160 REJ09B0191-0300 Section 1 Overview Classification Symbol I/O I O Name DMA-transfer request DMA-transfer request accept Function Input pins to receive external requests for DMA transfer. Output pins for signals indicating acceptance of external requests from external devices. Direct memory DREQ3 to access controller DREQ0 (DMAC) DACK3 to DACK0 TEND1, TEND0 O Multi-function timer pulse unit 2 (MTU2) TCLKA, TCLKB, TCLKC, TCLKD TIOC0A, TIOC0B, TIOC0C, TIOC0D TIOC1A, TIOC1B I DMA-transfer end Output pins for DMA transfer end. output MTU2 timer clock External clock input pins for the input timer. I/O MTU2 input capture/output compare (channel 0) MTU2 input capture/output compare (channel 1) MTU2 input capture/output compare (channel 2) MTU2 input capture/output compare (channel 3) MTU2 input capture/output compare (channel 4) MTU2 input capture (channel 5) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. The TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. The TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. The TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. The TGRU_5, TGRV_5, and TGRW_5 input capture input/dead time compensation input pins. I/O TIOC2A, TIOC2B I/O TIOC3A, TIOC3B, TIOC3C, TIOC3D TIOC4A, TIOC4B, TIOC4C, TIOC4D TIOC5U, TIOC5V, TIOC5W I/O I/O I Rev. 3.00 Jun. 18, 2008 Page 13 of 1160 REJ09B0191-0300 Section 1 Overview Classification Multi-function timer pulse unit 2S (MTU2S) Symbol TIOC3AS, TIOC3BS, TIOC3CS, TIOC3DS TIOC4AS, TIOC4BS, TIOC4CS, TIOC4DS TIOC5US, TIOC5VS, TIOC5WS I/O I/O Name MTU2S input capture/output compare (channel 3) MTU2S input capture/output compare (channel 4) MTU2S input capture (channel 5) Port output control Port output control Transmit data Receive data Serial clock Function The TGRA_3S to TGRD_3S input capture input/output compare output/PWM output pins. The TGRA_4S and TGRB_4S input capture input/output compare output/PWM output pins. The TGRU_5S, TGRV_5S, and TGRW_5S input capture input/dead time compensation input pins. Request signal input to place the MTU2 high-current pins in the high impedance state. Request signal input to place the MTU2S high-current pins in the high impedance state. Data output pins. Data input pins. Clock input/output pins. I/O I Port output POE8, POE3 to enable 2 (POE2) POE0 POE7 to POE4 I I Serial communication interface with FIFO (SCIF) TxD3 to TxD0 RxD3 to RxD0 SCK3 to SCK0 RTS3 CTS3 O I I/O O I I/O I/O I I O I I I Transmit request Modem control pin. Transmit enable Serial clock pin Serial data pin Modem control pin. Serial clock input/output pin. Serial data input/output pin. I2C bus SCL interface 3 (IIC3) SDA A/D converter (ADC) AN7 to AN0 ADTRG DA1, DA0 AVcc AVss AVref Analog input pins Analog input pins. A/D conversion trigger input Analog output pins Analog power supply Analog ground External trigger input pin for starting A/D conversion. Analog output pins. Power supply pins for the A/D converter and D/A converter. Ground pins for the A/D converter and D/A converter. D/A converter (DAC) Common to analog-related items Analog reference Analog reference voltage pins for the voltage A/D converter and D/A converter. Rev. 3.00 Jun. 18, 2008 Page 14 of 1160 REJ09B0191-0300 Section 1 Overview Classification I/O ports Symbol I/O Name General port Function 23-bit general input/output port pins. PA25 to I/O PA16, PA13 to PA11, PA9 to PA0 PB9, PB5, PB4 PB3, PB2 PC1, PC0 I/O I I/O General port General port General port General port General port General port Test clock 3-bit general input/output port pins. 2-bit general input port pins. 2-bit general input/output port pins. 24-bit general input/output port pins. 16-bit general input/output port pins. 8-bit general input port pins. Test-clock input pin. PD31 to PD8 I/O PE15 to PE0 I/O PF7 to PF0 High-performance user debugging interface (H-UDI) TCK TMS TDI TDO TRST Emulator interface I I I I O I Test mode select Test-mode select signal input pin. Test data input Test data output Test reset AUD data AUD clock AUD sync signal Break mode acknowledge Break request ASECK output User break trigger output Serial input pin for instructions and data. Serial output pin for instructions and data. Initialization-signal input pin. Branch source or destination address output pins. Sync-clock output pin. Data start-position acknowledgesignal output pin. Indicates that the E10A-USB emulator has entered its break mode. E10A-USB emulator break input pin. Outputs the trace clock of the E10AUSB emulator. Trigger output pin for UBC condition match. AUDATA3 to O AUDATA0 AUDCK AUDSYNC ASEBRKAK O O O ASEBRK ASEBCK User break controller (UBC) UBCTRG I O O Rev. 3.00 Jun. 18, 2008 Page 15 of 1160 REJ09B0191-0300 Section 1 Overview 1.5 Table 1.3 Pin NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 List of Pins List of Pins Function 2 Function 3 Function 4 Function 5 Weak Pin Name RD PA8 PVss PC1 A2 A3 A4 A5 A6 A7 A8 A9 Vcc Vss PVss PVcc A10 A11 A12 A13 A14 A15 A16 Vcc Vss A17 A18 A19 O O O Yes Yes Yes Figure 1.9 Figure 1.9 Figure 1.9 O O O O O O O Yes Yes Yes Yes Yes Yes Yes Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 I/O O O O O O O O O A1 O Yes Yes Yes Yes Yes Yes Yes Yes Yes Figure 1.12 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 Figure 1.9 I/O O I/O Pin Name TCLKC I/O I(s) Pin Name IRQ2 I/O I(s) Pin Name I/O Pin Name RD/WR I/O O keeper Yes Yes Pull-up I/O Buffer Simplified Diagram Figure 1.9 Figure 1.14 Function 1 Rev. 3.00 Jun. 18, 2008 Page 16 of 1160 REJ09B0191-0300 Section 1 Overview Function 1 Pin NO. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin Name A20 PA18 PVcc CKIO PVss PLLVss PLLVcc PVcc RES PVss XTAL EXTAL PVss PVcc NMI PVss PVss PB9 PA5 PA4 PA3 PA2 PC0 PE16 PE15 I/O I/O I/O I/O I/O I/O I/O I/O I(s) O I I(s) I/O I/O O I/O Function 2 Function 3 Function 4 Function 5 Weak I/O Buffer Simplified Pull-up Diagram Figure 1.9 Figure 1.14 Pin Name BREQ I/O I Pin Name TEND0 I/O O Pin Name I/O Pin Name PINT2 I/O I(s) keeper Yes Yes Figure 1.11 Figure 1.4 Figure 1.3 Figure 1.3 Figure 1.5 IRQ7 SCK1 TxD1 RxD1 SCK0 A0 TIOC4D I(s) I(s)/O O I(s) I(s)/O O I(s)/O A21 DREQ1 DREQ0 DACK1 O I I O ADTRG IRQ1 IRQ0 IRQOUT/ REFOUT I I(s) I(s) O POE8 A22 A23 A24 A25 CS8 CKE I(s) O O O O O O Yes Yes Yes Yes Yes Yes Yes Yes Figure 1.14 Figure 1.14 Figure 1.12 Figure 1.14 Figure 1.14 Figure 1.12 Figure 1.12 Figure 1.14 54 55 56 57 58 MD_CLK2 MD_CLK0 Vss Vcc MD2 I(s) I(s) Figure 1.4 Figure 1.4 I(s) Figure 1.4 Rev. 3.00 Jun. 18, 2008 Page 17 of 1160 REJ09B0191-0300 Section 1 Overview Function 1 Pin NO. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name MD0 PA9 PE9 PA17 PVcc PVss PVss PE13 CS0 PA11 PE8 PA24 PA25 PB3 I/O O I/O I/O I/O I/O I(s) I/O I(s) I/O I/O I/O Function 2 Function 3 Function 4 Function 5 Weak I/O Buffer Simplified Pull-up Diagram Figure 1.4 Yes Yes Yes Figure 1.14 Figure 1.14 Figure 1.12 Pin Name TCLKD TIOC3B WAIT I/O I(s) I(s)/O I Pin Name IRQ3 SCK3 DACK2 I/O I(s) I(s)/O O Pin Name FRAME RTS3 I/O O I/O Pin Name CKE I/O O keeper TIOC4B CS1 TIOC3A CE2A CE2B IRQ1 I(s)/O O I(s)/O O O I(s) MRES SCK2 DREQ3 DACK3 POE1 I(s) I(s)/O I O I(s) POE5 PINT6 PINT7 SDA I(s) I(s) I(s) I(s)/ O(o) POE8 I(s) Yes Yes Yes Yes Yes Yes Figure 1.14 Figure 1.9 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.13 73 PB2 I(s) IRQ0 I(s) POE0 I(s) SCL I(s)/ O(o) Figure 1.13 74 75 76 77 78 79 80 81 82 83 84 85 86 87 PE7 PE0 PVcc PVss Vss Vcc PE3 PA1 PE5 PE1 PE6 PA0 PE4 PE2 I/O I/O TIOC2B TIOC0A I(s)/O I(s)/O RxD2 DREQ0 I(s) I BS AUDCK O O UBCTRG O Yes Yes Figure 1.16 Figure 1.14 I/O I/O I/O I/O I/O I/O I/O I/O TIOC0D TxD0 TIOC1B TIOC0B TIOC2A RxD0 TIOC1A TIOC0C I(s)/O O I(s)/O I(s)/O I(s)/O I(s) I(s)/O I(s)/O TEND1 TxD3 TEND0 SCK3 RxD3 DREQ1 O O O I(s)/O I(s) I AUDATA3 PINT1 AUDATA1 AUDATA0 PINT0 AUDATA2 O I(s) O O I(s) O CS5/CE1A CS6/CE1B CS7 CS4 IOIS16 O O O O I Yes Yes Yes Yes Yes Yes Yes Yes Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Rev. 3.00 Jun. 18, 2008 Page 18 of 1160 REJ09B0191-0300 Section 1 Overview Function 1 Pin NO. 88 Pin Name PE14 I/O I/O Function 2 Function 3 Function 4 Function 5 Weak I/O Buffer Simplified Pull-up Diagram Figure 1.14 Pin Name TIOC4C I/O I(s)/O Pin Name DACK0 I/O I/O Pin Name I/O Pin Name WE3/ DQMUU/AH/ ICIOWR I/O O keeper Yes 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 AVss PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 AVref AVcc PE10 Vcc Vss PE11 I/O TIOC3D I(s)/O RxD3 I(s) CTS3 I(s)/O Yes Yes Figure 1.14 Figure 1.15 I/O TIOC3C I(s)/O TxD2 O Yes Figure 1.14 I I I I I I I I AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I(a) I(a) I(a) I(a) I(a) I(a) I(a) I(a) DA0 DA1 O(a) O(a) Figure 1.17 Figure 1.17 Figure 1.17 Figure 1.17 Figure 1.17 Figure 1.17 Figure 1.18 Figure 1.18 ASEBRKAK/ I(s)/O ASEBRK 105 106 107 108 109 110 111 112 113 114 115 PE12 WDTOVF ASEBCK PVcc PA19 TCK TRST TDI PVss Vss Vcc I/O O O TIOC4A I(s)/O TxD3 O Yes Yes Figure 1.14 Figure 1.10 Figure 1.8 I/O I I(s) I BACK O TEND1 O PINT3 I(s) Yes Yes Yes Yes Figure 1.14 Figure 1.7 Figure 1.6 Figure 1.7 Rev. 3.00 Jun. 18, 2008 Page 19 of 1160 REJ09B0191-0300 Section 1 Overview Function 1 Pin NO. 116 117 118 119 120 121 122 Pin Name TMS PVcc PVss ASEMD TDO PD31 PD30 I(s) O I/O I/O I/O I Function 2 Function 3 Function 4 Function 5 Weak I/O Buffer Simplified Pull-up Yes Diagram Figure 1.7 Pin Name I/O Pin Name I/O Pin Name I/O Pin Name I/O keeper D31 D30 I/O I/O ADTRG IRQOUT/ REFOUT I O TIOC3AS TIOC3CS I(s)/O I(s)/O Yes Yes Figure 1.4 Figure 1.8 Figure 1.14 Figure 1.14 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 PD29 PD28 PVcc PVss PD27 PD26 PD25 PD24 PVcc PD23 PVss PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 Vss Vcc I/O I/O D29 D28 I/O I/O CS3 CS2 O O TIOC3BS TIOC3DS I(s)/O I(s)/O Yes Yes Figure 1.14 Figure 1.14 I/O I/O I/O I/O D27 D26 D25 D24 I/O I/O I/O I/O DACK1 DACK0 DREQ1 DREQ0 O O I I TIOC4AS TIOC4BS TIOC4CS TIOC4DS I(s)/O I(s)/O I(s)/O I(s)/O Yes Yes Yes Yes Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 I/O D23 I/O IRQ7 I(s) AUDSYNC O Yes Figure 1.14 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 I(s) I(s) I(s) I(s) I(s) I(s) I(s) TIC5US TIC5VS TIC5WS POE7 POE6 POE5 POE4 TIOC4DS TIOC4CS TIOC4BS I(s) I(s) I(s) I(s) I(s) I(s) I(s) I(s)/O I(s)/O I(s)/O AUDCK AUDATA3 AUDATA2 AUDATA1 AUDATA0 O O O O O Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.14 Rev. 3.00 Jun. 18, 2008 Page 20 of 1160 REJ09B0191-0300 Section 1 Overview Function 1 Pin NO. 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 Pin Name PD12 PVss PD11 PVcc PD10 PD9 PD8 D7 D6 D5 D4 D3 Vss Vcc D2 D1 PVss PVcc D0 PA21 PB5 PA16 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function 2 Function 3 Function 4 Function 5 Weak I/O Buffer Simplified Pull-up Diagram Figure 1.14 Pin Name D12 I/O I/O Pin Name I/O Pin Name TIOC4AS I/O I(s)/O Pin Name I/O keeper Yes D11 I/O TIOC3DS I(s)/O Yes Figure 1.14 D10 D9 D8 I/O I/O I/O TIOC3CS TIOC3BS TIOC3AS I(s)/O I(s)/O I(s)/O Yes Yes Yes Yes Yes Yes Yes Yes Figure 1.14 Figure 1.14 Figure 1.14 Figure 1.12 Figure 1.12 Figure 1.12 Figure 1.12 Figure 1.12 Yes Yes Figure 1.12 Figure 1.12 CS5/CE1A IRQ3 WE3/ DQMUU/ AH/ ICIOWR O I(s) O CASU POE3 DREQ2 O I(s) I TIC5U CASL AUDSYNC I(s) O O PINT5 CKE I(s) O Yes Yes Yes Yes Figure 1.12 Figure 1.14 Figure 1.14 Figure 1.12 168 169 170 PA6 PA7 PA23 I/O I/O I/O TCLKA TCLKB WE3/ DQMUU/ AH/ ICIOWR I(s) I(s) O CS2 CS3 O O TIC5W I(s) Yes Yes Yes Figure 1.14 Figure 1.14 Figure 1.14 Rev. 3.00 Jun. 18, 2008 Page 21 of 1160 REJ09B0191-0300 Section 1 Overview Function 1 Pin NO. 171 Pin Name PA22 I/O I/O Function 2 Function 3 Function 4 Function 5 Weak I/O Buffer Simplified Pull-up Diagram Figure 1.14 Pin Name WE2/ DQMUL/ ICIORD I/O O Pin Name I/O Pin Name TIC5V I/O I(s) Pin Name I/O keeper Yes 172 PA13 I/O WE1/ DQMLU/ WE O POE7 I(s) Yes Figure 1.14 173 PA12 I/O WE0/ DQMLL O POE6 I(s) Yes Figure 1.14 174 175 176 PB4 PA20 PVcc I/O I/O IRQ2 CS4 I(s) O POE2 RASU I(s) O RASL O PINT4 I(s) Yes Yes Figure 1.14 Figure 1.14 [Legend] (s): Schmitt (a): Analog (o): Open-drain Rev. 3.00 Jun. 18, 2008 Page 22 of 1160 REJ09B0191-0300 Section 1 Overview XOUT (XTAL) Input clock XIN (EXTAL) Input enable Figure 1.3 Simplified Circuit Diagram (Oscillation Buffer) PAD Input data Figure 1.4 Simplified Circuit Diagram (Schmitt Input Buffer) PAD Input data Input enable Figure 1.5 Simplified Circuit Diagram (Schmitt OR Input Buffer) PVcc PAD Input data Input enable Figure 1.6 Simplified Circuit Diagram (Schmitt OR Input Buffer with Pull-Up) Rev. 3.00 Jun. 18, 2008 Page 23 of 1160 REJ09B0191-0300 Section 1 Overview PVcc PAD Input data Input enable Figure 1.7 Simplified Circuit Diagram (TTL OR Input Buffer with Pull-Up) Output enable PAD Output data Figure 1.8 Simplified Circuit Diagram (Output Buffer with Enable) Output enable PAD Output data Figure 1.9 Simplified Circuit Diagram (Output Buffer with Enable and Weak Keeper) PVcc Output enable PAD Output data Figure 1.10 Simplified Circuit Diagram (Output Buffer with Enable and Pull-Up) Rev. 3.00 Jun. 18, 2008 Page 24 of 1160 REJ09B0191-0300 Section 1 Overview Output enable PAD Output data Input data Input enable Figure 1.11 Simplified Circuit Diagram (Bidirectional Buffer, TTL OR Input) Output enable PAD Output data Input data Input enable Figure 1.12 Simplified Circuit Diagram (Bidirectional Buffer, TTL OR Input, with Weak Keeper) PAD Output data Input data Input enable Figure 1.13 Simplified Circuit Diagram (Open-Drain Output, Schmitt OR Input Buffer) Rev. 3.00 Jun. 18, 2008 Page 25 of 1160 REJ09B0191-0300 Section 1 Overview Output enable PAD Output data TTL input data TTL input enable Schmitt input data Schmitt input enable Figure 1.14 Simplified Circuit Diagram (Bidirectional Buffer, TTL OR Input, Schmitt OR Input, with Weak Keeper) PVcc Output enable PAD Output data Input data Input enable Figure 1.15 Simplified Circuit Diagram (Bidirectional Buffer, Schmitt OR Input, with PullUp) Rev. 3.00 Jun. 18, 2008 Page 26 of 1160 REJ09B0191-0300 Section 1 Overview PVcc Output enable PAD Output data TTL input data TTL input enable Schmitt input data Schmitt input enable Figure 1.16 Simplified Circuit Diagram (Bidirectional Buffer, TTL OR Input, Schmitt OR Input, with Pull-Up) A/D analog input enable 0 A/D analog input data 0 A/D analog input enable 1 PAD A/D analog input data 1 TTL input data TTL input enable Figure 1.17 Simplified Circuit Diagram (TTL OR Input, Common Buffer for A/D 2-Channel Input) Rev. 3.00 Jun. 18, 2008 Page 27 of 1160 REJ09B0191-0300 Section 1 Overview D/A analog output enable D/A analog output data A/D analog input enable 0 A/D analog input data 0 A/D analog input enable 1 PAD A/D analog input data 1 TTL input data TTL input enable Figure 1.18 Simplified Circuit Diagram (TTL OR Input, Common Buffer for A/D 2-Channel Input and D/A Output) Rev. 3.00 Jun. 18, 2008 Page 28 of 1160 REJ09B0191-0300 Section 2 CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and restoring the status register (SR) and program counter (PC) in exception handling is accomplished by referencing the stack using R15. 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 0 Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers Rev. 3.00 Jun. 18, 2008 Page 29 of 1160 REJ09B0191-0300 Section 2 CPU 2.1.2 Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The global base register functions as a base address for the GBR indirect addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception handling vector area (including interrupts). The jump table base register functions as the base address of the function table area. 31 14 13 BO CS 9876543210 MQ I[3:0] ST Status register (SR) 31 GBR 0 Global base register (GBR) 0 VBR 31 Vector base register (VBR) 0 31 TBR Jump table base register (TBR) Figure 2.2 Control Registers (1) Status Register (SR) Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 BO 13 CS 12 - 11 - 10 - 9 M 8 Q 7 6 I[3:0] 5 4 3 - 2 - 1 S 0 T Initial value: R/W: 0 R 0 R/W 0 R/W 0 R 0 R 0 R R/W R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R 0 R R/W R/W Rev. 3.00 Jun. 18, 2008 Page 30 of 1160 REJ09B0191-0300 Section 2 CPU Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 15 -- 14 13 BO CS 0 0 R/W R/W BO Bit Indicates that a register bank has overflowed. CS Bit Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-limit value or fallen below the saturation lower-limit value. 12 to 10 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 to 4 3, 2 M Q I[3:0] -- -- -- 1111 All 0 R/W R/W R/W R M Bit Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Interrupt Mask Level Reserved These bits are always read as 0. The write value should always be 0. 1 S -- R/W S Bit Specifies a saturation operation for a MAC instruction. 0 T -- R/W T Bit True/false condition or carry/borrow bit (2) Global Base Register (GBR) GBR is referenced as the base address in a GBR-referencing MOV instruction. (3) Vector Base Register (VBR) VBR is referenced as the branch destination base address in the event of an exception or an interrupt. (4) Jump Table Base Register (TBR) TBR is referenced as the start address of a function table located in memory in a JSR/N@@(disp8,TBR) table-referencing subroutine call instruction. Rev. 3.00 Jun. 18, 2008 Page 31 of 1160 REJ09B0191-0300 Section 2 CPU 2.1.3 System Registers The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results of multiply or multiply and accumulate operations. PR stores the return address from a subroutine procedure. PC points four bytes ahead of the current instruction and controls the flow of the processing. 31 MACH MACL 31 PR 0 0 Multiply and accumulate register high (MACH) and multiply and accumulate register low (MACL): Store the results of multiply or multiply and accumulate operations. Procedure register (PR): Stores the return address from a subroutine procedure. 31 PC 0 Program counter (PC): Indicates the four bytes ahead of the current instruction. Figure 2.3 System Registers (1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate Register Low (MACL) MACH and MACL are used as the addition value in a MAC instruction, and store the result of a MAC or MUL instruction. (2) Procedure Register (PR) PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC) PC points four bytes ahead of the instruction being executed. Rev. 3.00 Jun. 18, 2008 Page 32 of 1160 REJ09B0191-0300 Section 2 CPU 2.1.4 Register Banks For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents are automatically saved in the bank after the CPU accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK instruction in an interrupt processing routine. This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 5.8, Register Banks. 2.1.5 Initial Values of Registers Table 2.1 lists the values of the registers after a reset. Table 2.1 Initial Values of Registers Register R0 to R14 R15 (SP) Control registers SR Initial Value Undefined Value of the stack pointer in the vector address table Bits I[3:0] are 1111 (H'F), BO and CS are 0, reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Classification General registers GBR, TBR VBR System registers MACH, MACL, PR PC Rev. 3.00 Jun. 18, 2008 Page 33 of 1160 REJ09B0191-0300 Section 2 CPU 2.2 2.2.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 Longword 0 Figure 2.4 Data Format in Registers 2.2.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored in a register in sign-extended or zero-extended form. A word operand should be accessed at a word boundary (an even address of multiple of two bytes: address 2n), and a longword operand at a longword boundary (an even address of multiple of four bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any address. Only big-endian byte order can be selected for the data format. Data formats in memory are shown in figure 2.5. Address m + 1 Address m 31 Byte Address 2n Address 4n Word Longword Big endian 23 Byte Address m + 3 Address m + 2 15 Byte Word 7 Byte 0 Figure 2.5 Data Formats in Memory Rev. 3.00 Jun. 18, 2008 Page 34 of 1160 REJ09B0191-0300 Section 2 CPU 2.2.3 Immediate Data Format Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. 20-bit immediate data is located in the code of a MOVI20 or MOVI20S 32-bit transfer instruction. The MOVI20 instruction stores immediate data in the destination register in sign-extended form. The MOVI20S instruction shifts immediate data by eight bits in the upper direction, and stores it in the destination register in sign-extended form. Word or longword immediate data is not located in the instruction code, but rather is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. See examples given in section 2.3.1 (10), Immediate Data. Rev. 3.00 Jun. 18, 2008 Page 35 of 1160 REJ09B0191-0300 Section 2 CPU 2.3 2.3.1 Instruction Features RISC-Type Instruction Set Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease of use. (3) One Instruction per State Each basic instruction can be executed in one cycle using the pipeline system. (4) Data Length Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data in memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It is also handled as longword data. Table 2.2 SH2-A CPU MOV.W ADD Sign Extension of Word Data Description @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD instruction. H'1234 Example of Other CPU ADD.W #H'1234,R0 .DATA.W Note: @(disp, PC) accesses the immediate data. (5) Load-Store Architecture Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Rev. 3.00 Jun. 18, 2008 Page 36 of 1160 REJ09B0191-0300 Section 2 CPU (6) Delayed Branch Instructions With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. This reduces disturbance of the pipeline control when a branch is taken. In a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution such as register updating excluding the actual branch operation, is performed in the order of delayed branch instruction delay slot instruction. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.3 SH-2A CPU BRA ADD TRGET R1,R0 Delayed Branch Instructions Description Executes the ADD before branching to TRGET. Example of Other CPU ADD.W BRA R1,R0 TRGET (7) Unconditional Branch Instructions with No Delay Slot The SH-2A additionally features unconditional branch instructions in which a delay slot instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code size. (8) Multiply/Multiply-and-Accumulate Operations 16-bit x 16-bit 32-bit multiply operations are executed in one to two cycles. 16-bit x 16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit x 32-bit 64-bit multiply and 32-bit x 32-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four cycles. (9) T Bit The T bit in the status register (SR) changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. Rev. 3.00 Jun. 18, 2008 Page 37 of 1160 REJ09B0191-0300 Section 2 CPU Table 2.4 SH-2A CPU CMP/GE BT BF ADD CMP/EQ BT T Bit Description R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 < R1. T bit is not changed by ADD. T bit is set when R0 = 0. The program branches if R0 = 0. Example of Other CPU CMP.W BGE BLT SUB.W BEQ R1,R0 TRGET0 TRGET1 #1,R0 TRGET (10) Immediate Data Byte immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for 21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a register. Table 2.5 Immediate Data Accessing SH-2A CPU MOV MOVI20 MOVI20 MOVI20S OR 32-bit immediate MOV.L #H'12,R0 #H'1234,R0 #H'12345,R0 #H'12345,R0 #H'67,R0 @(disp,PC),R0 ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. MOV.L #H'12345678,R0 Example of Other CPU MOV.B MOV.W MOV.L MOV.L #H'12,R0 #H'1234,R0 #H'12345,R0 #H'1234567,R0 Classification 8-bit immediate 16-bit immediate 20-bit immediate 28-bit immediate Rev. 3.00 Jun. 18, 2008 Page 38 of 1160 REJ09B0191-0300 Section 2 CPU (11) Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in register indirect addressing mode. With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also possible to transfer immediate data located in the instruction code to a register and to reference the data in register indirect addressing mode. However, when referencing data using an absolute address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register. Table 2.6 Absolute Address Accessing SH-2A CPU MOVI20 MOV.B 21 to 28 bits MOVI20S OR MOV.B 29 bits or more MOV.L MOV.B #H'12345,R1 @R1,R0 #H'12345,R1 #H'67,R1 @R1,R0 @(disp,PC),R1 @R1,R0 .................. .DATA.L H'12345678 MOV.B @H'12345678,R0 MOV.B @H'1234567,R0 Example of Other CPU MOV.B @H'12345,R0 Classification Up to 20 bits (12) 16-Bit/32-Bit Displacement When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indexed indirect register addressing mode. Table 2.7 Displacement Accessing SH-2A CPU MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .................. .DATA.W H'1234 Example of Other CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement Rev. 3.00 Jun. 18, 2008 Page 39 of 1160 REJ09B0191-0300 Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Mode Register direct Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Rn The effective address is register Rn. (The operand is the contents of register Rn.) Equation -- Register indirect @Rn The effective address is the contents of register Rn. Rn Rn Rn Register indirect @Rn+ with postincrement The effective address is the contents of register Rn. A constant is added to the contents of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn (After instruction execution) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Rn Register indirect @-Rn with predecrement The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn - 1/2/4 Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction is executed with Rn after this calculation) - Rn - 1/2/4 1/2/4 Rev. 3.00 Jun. 18, 2008 Page 40 of 1160 REJ09B0191-0300 Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation The effective address is the sum of Rn and a 4-bit displacement (disp). The value of disp is zeroextended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn Equation Register indirect @(disp:4, with Rn) displacement Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Register indirect @(disp:12, The effective address is the sum of Rn and a 12with Rn) bit displacement displacement (disp). The value of disp is zeroextended. Rn + disp (zero-extended) Rn + disp Byte: Rn + disp Word: Rn + disp Longword: Rn + disp Indexed register @(R0,Rn) indirect The effective address is the sum of Rn and R0. Rn + Rn + R0 Rn + R0 R0 GBR indirect with displacement @(disp:8, GBR) The effective address is the sum of GBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Rev. 3.00 Jun. 18, 2008 Page 41 of 1160 REJ09B0191-0300 Section 2 CPU Addressing Mode Indexed GBR indirect Instruction Format Effective Address Calculation Equation GBR + R0 @(R0, GBR) The effective address is the sum of GBR value and R0. GBR + GBR + R0 R0 TBR duplicate indirect with displacement @@ (disp:8, TBR) The effective address is the sum of TBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and is multiplied by 4. TBR disp (zero-extended) Contents of address (TBR + disp x 4) + TBR + disp x 4 x (TBR 4 + disp x 4) PC indirect with @(disp:8, displacement PC) The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & (for longword) Word: PC + disp x 2 Longword: PC & H'FFFFFFFC + disp x 4 H'FFFFFFFC disp (zero-extended) x + PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 2/4 Rev. 3.00 Jun. 18, 2008 Page 42 of 1160 REJ09B0191-0300 Section 2 CPU Addressing Mode PC relative Instruction Format Effective Address Calculation disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 8-bit displacement (disp). PC Equation PC + disp x 2 disp (sign-extended) x 2 + PC + disp x 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp). PC PC + disp x 2 disp (sign-extended) x 2 + PC + disp x 2 Rn The effective address is the sum of PC value and Rn. PC + PC + Rn PC + Rn Rn Rev. 3.00 Jun. 18, 2008 Page 43 of 1160 REJ09B0191-0300 Section 2 CPU Addressing Mode Immediate Instruction Format Effective Address Calculation #imm:20 The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended. 31 19 0 Signextended imm (20 bits) Equation -- The 20-bit immediate data (imm) for the MOVI20S -- instruction is shifted by eight bits to the left, the upper bits are sign-extended, and the lower bits are padded with zero. 31 27 8 0 imm (20 bits) 00000000 Sign-extended #imm:8 #imm:8 #imm:8 #imm:3 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. -- -- -- The 3-bit immediate data (imm) for the BAND, BOR, -- BXOR, BST, BLD, BSET, and BCLR instructions indicates the target bit location. Rev. 3.00 Jun. 18, 2008 Page 44 of 1160 REJ09B0191-0300 Section 2 CPU 2.3.3 Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: * * * * * xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Instruction Formats Source Operand -- 0 xxxx xxxx xxxx xxxx Table 2.9 Instruction Formats 0 format 15 Destination Operand -- Example NOP n format 15 xxxx 0 nnnn xxxx xxxx -- Control register or system register nnnn: Register direct nnnn: Register direct MOVT STS DIVU Rn MACH,Rn R0,Rn R0 (Register direct) nnnn: Register direct Control register or system register mmmm: Register direct R15 (Register indirect with postincrement) nnnn: Register indirect with predecrement R15 (Register indirect with predecrement) nnnn: Register direct STC.L SR,@-Rn MOVMU.L Rm,@-R15 MOVMU.L @R15+,Rn MOV.L R0,@Rn+ R0 (Register direct) nnnn: (Register indirect with postincrement) Rev. 3.00 Jun. 18, 2008 Page 45 of 1160 REJ09B0191-0300 Section 2 CPU Instruction Formats m format 15 xxxx mmmm xxxx xxxx 0 Source Operand mmmm: Register direct mmmm: Register indirect with postincrement mmmm: Register indirect mmmm: Register indirect with predecrement Destination Operand Control register or system register Control register or system register -- Example LDC Rm,SR LDC.L @Rm+,SR JMP @Rm R0 (Register direct) MOV.L @-Rm,R0 mmmm: PC relative -- using Rm nm format 15 xxxx nnnn mmmm xxxx 0 BRAF ADD Rm Rm,Rn mmmm: Register direct mmmm: Register direct nnnn: Register direct nnnn: Register indirect MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: Register MACH, MACL indirect with postincrement (multiplyand-accumulate) nnnn*: Register indirect with postincrement (multiplyand-accumulate) mmmm: Register indirect with postincrement mmmm: Register direct mmmm: Register direct md format 15 xxxx xxxx mmmm dddd 0 nnnn: Register direct nnnn: Register indirect with predecrement nnnn: Indexed register indirect MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) mmmmdddd: Register indirect with displacement R0 (Register direct) MOV.B @(disp,Rm),R0 Rev. 3.00 Jun. 18, 2008 Page 46 of 1160 REJ09B0191-0300 Section 2 CPU Instruction Formats nd4 format 15 xxxx xxxx nnnn dddd 0 Source Operand Destination Operand Example MOV.B R0,@(disp,Rn) R0 (Register direct) nnnndddd: Register indirect with displacement mmmm: Register direct mmmmdddd: Register indirect with displacement nmd format 15 xxxx nnnn mmmm dddd 0 nnnndddd: Register MOV.L indirect with Rm,@(disp,Rn) displacement nnnn: Register direct MOV.L @(disp,Rm),Rn nmd12 format 32 xxxx 15 xxxx 16 nnnn mmmm xxxx 0 dddd dddd dddd mmmm: Register direct mmmmdddd: Register indirect with displacement dddddddd: GBR indirect with displacement nnnndddd: Register MOV.L indirect with Rm,@(disp12,Rn) displacement nnnn: Register direct MOV.L @(disp12,Rm),Rn d format 15 xxxx xxxx dddd dddd 0 R0 (Register direct) MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR) R0 (Register direct) dddddddd: GBR indirect with displacement dddddddd: PC relative with displacement dddddddd: TBR duplicate indirect with displacement dddddddd: PC relative d12 format 15 xxxx dddd dddd dddd 0 R0 (Register direct) MOVA @(disp,PC),R0 -- JSR/N @@(disp8,TBR) BF BRA label label -- dddddddddddd: PC -- relative dddddddd: PC relative with displacement nnnn: Register direct (label = disp + PC) MOV.L @(disp,PC),Rn nd8 format 15 xxxx nnnn dddd dddd 0 Rev. 3.00 Jun. 18, 2008 Page 47 of 1160 REJ09B0191-0300 Section 2 CPU Instruction Formats i format 15 xxxx xxxx iiii 0 iiii Source Operand iiiiiiii: Immediate iiiiiiii: Immediate iiiiiiii: Immediate Destination Operand Indexed GBR indirect R0 (Register direct) -- Example AND.B #imm,@(R0,GBR) AND TRAPA #imm,R0 #imm #imm,Rn ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate nnnn: Register direct ADD ni3 format 15 xxxx xxxx nnnn x iii 0 nnnn: Register direct -- iii: Immediate -- BLD #imm3,Rn #imm3,Rn nnnn: Register direct BST iii: Immediate ni20 format 32 xxxx 15 iiii 16 nnnn iiii xxxx 0 iiii iiii iiii iiiiiiiiiiiiiiiiiiii: Immediate nnnn: Register direct MOVI20 #imm20, Rn nid format 32 xxxx 15 xxxx 16 nnnn xiii xxxx 0 dddd dddd dddd nnnndddddddddddd: -- Register indirect with displacement iii: Immediate -- BLD.B #imm3,@(disp12,Rn ) nnnndddddddddddd: BST.B Register indirect with #imm3,@(disp12,Rn displacement ) iii: Immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 3.00 Jun. 18, 2008 Page 48 of 1160 REJ09B0191-0300 Section 2 CPU 2.4 2.4.1 Instruction Set Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Classification Types Data transfer 13 Operation Code Function MOV Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer Reverse stack transfer MOVA MOVI20 MOVI20S MOVML MOVMU MOVRT MOVT MOVU NOTT PREF SWAP XTRCT Effective address transfer 20-bit immediate data transfer 20-bit immediate data transfer 8-bit left-shit R0-Rn register save/restore Rn-R14 and PR register save/restore T bit inversion and transfer to Rn T bit transfer Unsigned data transfer T bit inversion Prefetch to operand cache Swap of upper and lower bytes Extraction of the middle of registers connected No. of Instructions 62 Rev. 3.00 Jun. 18, 2008 Page 49 of 1160 REJ09B0191-0300 Section 2 CPU Classification Types Arithmetic operations 26 Operation Code Function ADD ADDC ADDV Binary addition Binary addition with carry Binary addition with overflow check No. of Instructions 40 CMP/cond Comparison CLIPS CLIPU DIVS DIVU DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULR MULS MULU NEG NEGC SUB SUBC SUBV Signed saturation value comparison Unsigned saturation value comparison Signed division (32 / 32) Unsigned division (32 / 32) One-step division Initialization of signed one-step division Initialization of unsigned one-step division Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-precision multiply-and-accumulate operation Double-precision multiply operation Signed multiplication with result storage in Rn Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Rev. 3.00 Jun. 18, 2008 Page 50 of 1160 REJ09B0191-0300 Section 2 CPU Classification Types Logic operations 6 Operation Code Function AND NOT OR TAS TST XOR Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit Dynamic arithmetic shift One-bit arithmetic left shift One-bit arithmetic right shift Dynamic logical shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift No. of Instructions 14 Shift 12 ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLLn SHLR SHLRn 16 Branch 10 BF BT BRA BRAF BSR BSRF JMP JSR RTS RTV/N Conditional branch, conditional delayed branch 15 (branch when T = 0) Conditional branch, conditional delayed branch (branch when T = 1) Unconditional delayed branch Unconditional delayed branch Delayed branch to subroutine procedure Delayed branch to subroutine procedure Unconditional delayed branch Branch to subroutine procedure Delayed branch to subroutine procedure Return from subroutine procedure Delayed return from subroutine procedure Return from subroutine procedure with Rm R0 transfer Rev. 3.00 Jun. 18, 2008 Page 51 of 1160 REJ09B0191-0300 Section 2 CPU Classification Types System control 14 Operation Code Function CLRT CLRMAC LDBANK LDC LDS NOP T bit clear MAC register clear Register restoration from specified register bank entry Load to control register Load to system register No operation No. of Instructions 36 RESBANK Register restoration from register bank RTE SETT SLEEP STBANK STC STS TRAPA Bit manipulation 10 BAND BCLR BLD BOR BSET BST BXOR Return from exception handling T bit set Transition to power-down mode Register save to specified register bank entry Store control register data Store system register data Trap exception handling Bit AND Bit clear Bit load Bit OR Bit set Bit store Bit exclusive OR 14 BANDNOT Bit NOT AND BORNOT BLDNOT Total: 91 Bit NOT OR Bit NOT load 197 Rev. 3.00 Jun. 18, 2008 Page 52 of 1160 REJ09B0191-0300 Section 2 CPU The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Instruction Indicated by mnemonic. Instruction Code Indicated in MSB LSB order. Operation Indicates summary of operation. Execution States Value when no wait states are inserted.*1 T Bit Value of T bit after instruction is executed. Explanation of Symbols --: No change [Legend] Rm: Rn: Source register Destination register [Legend] mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: dddd: Immediate data Displacement [Legend] , : (xx): Transfer direction Memory operand imm: Immediate data disp: Displacement*2 M/Q/T: Flag bits in SR &: |: ^: ~: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit < Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory register) is the same as the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by x1, x2, or x4. For details, refer to the SH-2A, SH2A-FPU Software Manual. Rev. 3.00 Jun. 18, 2008 Page 53 of 1160 REJ09B0191-0300 Section 2 CPU 2.4.2 Data Transfer Instructions Table 2.11 Data Transfer Instructions Execution Instruction MOV MOV.W #imm,Rn @(disp,PC),Rn Instruction Code Operation Cycles 1 1 Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes SH-2A Yes Yes 1110nnnniiiiiiii imm sign extension Rn 1001nnnndddddddd (disp x 2 + PC) sign extension Rn 1101nnnndddddddd (disp x 4 + PC) Rn 0110nnnnmmmm0011 Rm Rn 0010nnnnmmmm0000 Rm (Rn) 0010nnnnmmmm0001 Rm (Rn) 0010nnnnmmmm0010 Rm (Rn) 0110nnnnmmmm0000 (Rm) sign extension Rn 0110nnnnmmmm0001 (Rm) sign extension Rn 0110nnnnmmmm0010 (Rm) Rn 0010nnnnmmmm0100 Rn-1 Rn, Rm (Rn) 0010nnnnmmmm0101 Rn-2 Rn, Rm (Rn) 0010nnnnmmmm0110 Rn-4 Rn, Rm (Rn) Rm + 1 Rm MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn 1 1 1 1 1 1 1 1 1 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 0110nnnnmmmm0100 (Rm) sign extension Rn, 1 0110nnnnmmmm0101 (Rm) sign extension Rn, 1 Rm + 2 Rm 0110nnnnmmmm0110 (Rm) Rn, Rm + 4 Rm 10000000nnnndddd R0 (disp + Rn) 10000001nnnndddd R0 (disp x 2 + Rn) 0001nnnnmmmmdddd Rm (disp x 4 + Rn) 10000100mmmmdddd (disp + Rm) sign extension R0 10000101mmmmdddd (disp x 2 + Rm) sign extension R0 0101nnnnmmmmdddd (disp x 4 + Rm) Rn 0000nnnnmmmm0100 Rm (R0 + Rn) 0000nnnnmmmm0101 Rm (R0 + Rn) MOV.W @Rm+,Rn Yes Yes Yes MOV.L MOV.B MOV.W MOV.L MOV.B @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 1 1 1 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes MOV.W @(disp,Rm),R0 1 Yes Yes Yes MOV.L MOV.B MOV.W @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) 1 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Rev. 3.00 Jun. 18, 2008 Page 54 of 1160 REJ09B0191-0300 Section 2 CPU Execution Instruction MOV.L MOV.B Rm,@(R0,Rn) @(R0,Rm),Rn Instruction Code Operation Cycles 1 1 Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes SH-2A Yes Yes 0000nnnnmmmm0110 Rm (R0 + Rn) 0000nnnnmmmm1100 (R0 + Rm) sign extension Rn 0000nnnnmmmm1101 (R0 + Rm) sign extension Rn 0000nnnnmmmm1110 (R0 + Rm) Rn 11000000dddddddd R0 (disp + GBR) 11000001dddddddd R0 (disp x 2 + GBR) 11000010dddddddd R0 (disp x 4 + GBR) 11000100dddddddd (disp + GBR) sign extension R0 11000101dddddddd (disp x 2 + GBR) sign extension R0 11000110dddddddd (disp x 4 + GBR) R0 0100nnnn10001011 R0 (Rn), Rn + 1 Rn 0100nnnn10011011 R0 (Rn), Rn + 2 Rn 0100nnnn10101011 R0 Rn), Rn + 4 Rn 0100mmmm11001011 Rm-1 Rm, (Rm) sign extension R0 0100mmmm11011011 Rm-2 Rm, (Rm) sign extension R0 0100mmmm11101011 Rm-4 Rm, (Rm) R0 MOV.W @(R0,Rm),Rn 1 Yes Yes Yes MOV.L MOV.B MOV.W MOV.L MOV.B @(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 1 1 1 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes MOV.W @(disp,GBR),R0 1 Yes Yes Yes MOV.L MOV.B MOV.W MOV.L MOV.B @(disp,GBR),R0 R0,@Rn+ R0,@Rn+ R0,@Rn+ @-Rm,R0 1 1 1 1 1 Yes Yes Yes Yes Yes Yes Yes MOV.W @-Rm,R0 1 Yes MOV.L MOV.B @-Rm,R0 1 1 Yes Yes Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm (disp + Rn) 0000dddddddddddd MOV.W Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm (disp x 2 + Rn) 0001dddddddddddd 1 Yes MOV.L Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm (disp x 4 + Rn) 0010dddddddddddd 1 Yes MOV.B @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) 0100dddddddddddd sign extension Rn 1 Yes MOV.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp x 2 + Rm) 0101dddddddddddd sign extension Rn 1 Yes Rev. 3.00 Jun. 18, 2008 Page 55 of 1160 REJ09B0191-0300 Section 2 CPU Execution Instruction MOV.L Instruction Code Operation Cycles 1 Compatibility SH2, T Bit SH2E SH4 SH-2A Yes @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp x 4 + Rm) Rn 0110dddddddddddd MOVA MOVI20 @(disp,PC),R0 #imm20,Rn 11000111dddddddd disp x 4 + PC R0 0000nnnniiii0000 imm sign extension Rn iiiiiiiiiiiiiiii 1 1 Yes Yes Yes Yes MOVI20S #imm20,Rn 0000nnnniiii0001 imm << 8 sign extension iiiiiiiiiiiiiiii Rn 1 Yes MOVML.L Rm,@-R15 0100mmmm11110001 R15-4 R15, Rm (R15) R15-4 R15, Rm-1 (R15) : R15-4 R15, R0 (R15) Note: When Rm = R15, read Rm as PR 1 to 16 Yes MOVML.L @R15+,Rn 0100nnnn11110101 (R15) R0, R15 + 4 R15 (R15) R1, R15 + 4 R15 : (R15) Rn Note: When Rn = R15, read Rn as PR 1 to 16 Yes MOVMU.L Rm,@-R15 0100mmmm11110000 R15-4 R15, PR (R15) R15-4 R15, R14 (R15) : R15-4 R15, Rm (R15) Note: When Rm = R15, read Rm as PR 1 to 16 Yes MOVMU.L @R15+,Rn 0100nnnn11110100 (R15) Rn, R15 + 4 R15 (R15) Rn + 1, R15 + 4 R15 : (R15) R14, R15 + 4 R15 (R15) PR Note: When Rn = R15, read Rn as PR 1 to 16 Yes MOVRT MOVT Rn Rn 0000nnnn00111001 ~T Rn 0000nnnn00101001 T Rn 1 1 Yes Yes Yes Yes Rev. 3.00 Jun. 18, 2008 Page 56 of 1160 REJ09B0191-0300 Section 2 CPU Execution Instruction MOVU.B Instruction Code Operation Cycles 1 Compatibility SH2, T Bit SH2E SH4 SH-2A Yes @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) 1000dddddddddddd zero extension Rn MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp x 2 + Rm) 1001dddddddddddd NOTT zero extension Rn 1 Yes 0000000001101000 ~T T 1 Operation result Yes PREF SWAP.B @Rn Rm,Rn 0000nnnn10000011 (Rn) operand cache 0110nnnnmmmm1000 Rm swap lower 2 bytes Rn 0110nnnnmmmm1001 Rm swap upper and lower words Rn 1 1 Yes Yes Yes Yes Yes SWAP.W Rm,Rn 1 Yes Yes Yes XTRCT Rm,Rn 0010nnnnmmmm1101 Middle 32 bits of Rm:Rn Rn 1 Yes Yes Yes Rev. 3.00 Jun. 18, 2008 Page 57 of 1160 REJ09B0191-0300 Section 2 CPU 2.4.3 Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Execution Instruction ADD ADD ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 Operation Rn + Rm Rn Rn + imm Rn Cycles 1 1 T Bit Carry Overflow CMP/EQ #imm,R0 10001000iiiiiiii When R0 = imm, 1 T Otherwise, 0 T When Rn = Rm, 1 T Otherwise, 0 T When Rn Rm (unsigned), 1T Otherwise, 0 T CMP/GE Rm,Rn 0011nnnnmmmm0011 When Rn Rm (signed), 1T Otherwise, 0 T CMP/HI Rm,Rn 0011nnnnmmmm0110 When Rn > Rm (unsigned), 1T Otherwise, 0 T CMP/GT Rm,Rn 0011nnnnmmmm0111 When Rn > Rm (signed), 1T Otherwise, 0 T CMP/PL Rn 0100nnnn00010101 When Rn > 0, 1 T Otherwise, 0 T When Rn 0, 1 T Otherwise, 0 T 1 1 1 1 1 Comparison result CMP/EQ Rm,Rn 0011nnnnmmmm0000 1 Comparison result CMP/HS Rm,Rn 0011nnnnmmmm0010 1 Comparison result Comparison result Comparison result Comparison result Comparison result CMP/PZ Rn 0100nnnn00010001 1 Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 When any bytes are equal, 1T Otherwise, 0 T 1 Comparison result Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Compatibility SH2, SH2E SH4 Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Rn + Rm + T Rn, carry T 1 Rn + Rm Rn, overflow T 1 Rev. 3.00 Jun. 18, 2008 Page 58 of 1160 REJ09B0191-0300 Section 2 CPU Execution Instruction CLIPS.B Rn Instruction Code 0100nnnn10010001 Operation When Rn > (H'0000007F), (H'0000007F) Rn, 1 CS when Rn < (H'FFFFFF80), (H'FFFFFF80) Rn, 1 CS CLIPS.W Rn 0100nnnn10010101 When Rn > (H'00007FFF), (H'00007FFF) Rn, 1 CS When Rn < (H'FFFF8000), (H'FFFF8000) Rn, 1 CS CLIPU.B Rn 0100nnnn10000001 When Rn > (H'000000FF), (H'000000FF) Rn, 1 CS CLIPU.W Rn 0100nnnn10000101 When Rn > (H'0000FFFF), (H'0000FFFF) Rn, 1 CS DIV1 Rm,Rn 0011nnnnmmmm0100 1-step division (Rn / Rm) 1 Calculation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T Signed operation of Rn / R0 Rn 32 / 32 32 bits DIVU R0,Rn 0100nnnn10000100 Unsigned operation of Rn / R0 34 Rn 32 / 32 32 bits DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits DT Rn 0100nnnn00010000 Rn - 1 Rn When Rn is 0, 1 T When Rn is not 0, 0 T EXTS.B Rm,Rn 0110nnnnmmmm1110 Byte in Rm is sign-extended Rn EXTS.W Rm,Rn 0110nnnnmmmm1111 Word in Rm is sign-extended Rn 1 1 1 2 2 1 Calculation result DIV0U DIVS R0,Rn 0000000000011001 0100nnnn10010100 1 36 0 1 1 1 Cycles 1 T Bit Compatibility SH2, SH2E SH4 SH-2A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Compa- Yes rison result Yes Yes Yes Yes Yes Yes Yes Yes Rev. 3.00 Jun. 18, 2008 Page 59 of 1160 REJ09B0191-0300 Section 2 CPU Execution Instruction EXTU.B Rm,Rn Instruction Code 0110nnnnmmmm1100 Operation Byte in Rm is zero-extended Rn EXTU.W Rm,Rn 0110nnnnmmmm1101 Word in Rm is zero-extended Rn MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) x (Rm) + MAC MAC 32 x 32 + 64 64 bits MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bits MUL.L Rm,Rn 0000nnnnmmmm0111 Rn x Rm MACL 32 x 32 32 bits MULR R0,Rn 0100nnnn10000000 R0 x Rn Rn 32 x 32 32 bits MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn x Rm MACL 16 x 16 32 bits MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn x Rm MACL 16 x 16 32 bits NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 0-Rm Rn 0-Rm-T Rn, borrow T Rn-Rm Rn Rn-Rm-T Rn, borrow T Rn-Rm Rn, underflow T 1 1 1 1 1 1 1 2 2 3 4 1 Cycles 1 T Bit Compatibility SH2, SH2E SH4 SH-2A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Borrow Yes Yes Borrow Yes Overflow Yes Rev. 3.00 Jun. 18, 2008 Page 60 of 1160 REJ09B0191-0300 Section 2 CPU 2.4.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Execution Instruction AND AND AND.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) TAS.B @Rn 0100nnnn00011011 When (Rn) is 0, 1 T Otherwise, 0 T, 1 MSB of(Rn) TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm When the result is 0, 1 T Otherwise, 0 T TST #imm,R0 11001000iiiiiiii R0 & imm When the result is 0, 1 T Otherwise, 0 T TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm When the result is 0, 1 T Otherwise, 0 T XOR XOR XOR.B Rm,Rn #imm,R0 #imm,@(R0,GBR) 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR) 1 1 3 Yes Yes Yes Yes Yes Yes Yes Yes Yes 3 Test result Yes Yes Yes 1 Test result Yes Yes Yes 1 Test result Yes Yes Yes 3 Test result Yes Yes Yes 1 1 1 3 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Cycles 1 1 3 Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Rev. 3.00 Jun. 18, 2008 Page 61 of 1160 REJ09B0191-0300 Section 2 CPU 2.4.5 Shift Instructions Table 2.14 Shift Instructions Execution Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Operation T Rn MSB LSB Rn T T Rn T T Rn T When Rm 0, Rn << Rm Rn When Rm < 0, Rn >> |Rm| [MSB Rn] SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 T Rn 0 MSB Rn T When Rm 0, Rn << Rm Rn When Rm < 0, Rn >> |Rm| [0 Rn] SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn 1 1 1 1 1 1 1 1 MSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 1 1 MSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Cycles 1 1 1 1 1 Compatibility SH2, T Bit SH2E SH4 MSB LSB MSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Yes Rev. 3.00 Jun. 18, 2008 Page 62 of 1160 REJ09B0191-0300 Section 2 CPU 2.4.6 Branch Instructions Table 2.15 Branch Instructions Execution Instruction BF label Instruction Code 10001011dddddddd Operation When T = 0, disp x 2 + PC PC, When T = 1, nop BF/S label 10001111dddddddd Delayed branch When T = 0, disp x 2 + PC PC, When T = 1, nop BT label 10001001dddddddd When T = 1, disp x 2 + PC PC, When T = 0, nop BT/S label 10001101dddddddd Delayed branch When T = 1, disp x 2 + PC PC, When T = 0, nop BRA label 1010dddddddddddd Delayed branch, disp x 2 + PC PC BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC PC BSR label 1011dddddddddddd Delayed branch, PC PR, disp x 2 + PC PC BSRF Rm 0000mmmm00000011 Delayed branch, PC PR, Rm + PC PC JMP JSR @Rm @Rm 0100mmmm00101011 0100mmmm00001011 Delayed branch, Rm PC Delayed branch, PC PR, Rm PC PC-2 PR, Rm PC PC-2 PR, (disp x 4 + TBR) PC RTS RTS/N RTV/N Rm 0000000000001011 0000000001101011 0000mmmm01111011 Delayed branch, PR PC PR PC Rm R0, PR PC 2 3 3 Yes Yes Yes Yes Yes 2 2 Yes Yes Yes Yes Yes Yes 2 Yes Yes Yes 2 Yes Yes Yes 2 Yes Yes Yes 2 Yes Yes Yes 2/1* Yes Yes Yes 3/1* Yes Yes Yes 2/1* Yes Yes Yes Cycles 3/1* Compatibility SH2, T Bit SH2E SH4 Yes Yes SH-2A Yes JSR/N JSR/N @Rm 0100mmmm01001011 3 5 Yes Yes @@(disp8,TBR) 10000011dddddddd Note: * One cycle when the program does not branch. Rev. 3.00 Jun. 18, 2008 Page 63 of 1160 REJ09B0191-0300 Section 2 CPU 2.4.7 System Control Instructions Table 2.16 System Control Instructions Execution Instruction CLRT CLRMAC LDBANK @Rm,R0 Instruction Code 0000000000001000 0000000000101000 0100mmmm11100101 Operation 0T 0 MACH,MACL R0 LDC LDC LDC LDC LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP RESBANK Rm,SR Rm,TBR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR 0100mmmm00001110 0100mmmm01001010 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000001011011 Rm SR Rm TBR Rm GBR Rm VBR (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm Rm MACH Rm MACL Rm PR 3 1 1 1 5 1 1 1 1 1 LSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Cycles 1 1 Compatibility SH2, T Bit SH2E SH4 0 Yes Yes Yes Yes SH-2A Yes Yes Yes (Specified register bank entry) 6 (Rm) MACH, Rm + 4 Rm 1 (Rm) MACL, Rm + 4 Rm 1 (Rm) PR, Rm + 4 Rm No operation Bank R0 to R14, GBR, MACH, MACL, PR 1 1 9* RTE 0000000000101011 Delayed branch, stack area PC/SR 6 Yes Yes Yes SETT SLEEP STBANK R0,@Rn 0000000000011000 0000000000011011 0100nnnn11100001 1T Sleep R0 (specified register bank entry) SR Rn TBR Rn 1 5 7 1 Yes Yes Yes Yes Yes Yes Yes STC STC SR,Rn TBR,Rn 0000nnnn00000010 0000nnnn01001010 2 1 Yes Yes Yes Yes Rev. 3.00 Jun. 18, 2008 Page 64 of 1160 REJ09B0191-0300 Section 2 CPU Execution Instruction STC STC STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L TRAPA GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation GBR Rn VBR Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) MACH Rn MACL Rn PR Rn Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC/SR stack area, (imm x 4 + VBR) PC Cycles 1 1 2 1 1 1 1 1 1 1 1 5 Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Notes: Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory register) is the same as the register used by the next instruction. * In the event of bank overflow, the number of cycles is 19. Rev. 3.00 Jun. 18, 2008 Page 65 of 1160 REJ09B0191-0300 Section 2 CPU 2.4.8 Bit Manipulation Instructions Table 2.17 Bit Manipulation Instructions Execution Instruction BAND.B #imm3,@(disp12,Rn) Instruction Code 0011nnnn0iii1001 0100dddddddddddd BANDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~(imm of (disp + Rn)) & T T 3 1100dddddddddddd BCLR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0 (imm of (disp + Rn)) 0000dddddddddddd BCLR BLD.B #imm3,Rn #imm3,@(disp12,Rn) 10000110nnnn0iii 0 imm of Rn 0011nnnn0iii1001 (imm of (disp + Rn)) 0011dddddddddddd BLD #imm3,Rn 10000111nnnn1iii imm of Rn T 1 1 3 Operation result Operation result BLDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~(imm of (disp + Rn)) 1011dddddddddddd BOR.B #imm3,@(disp12,Rn) T 3 Operation result 3 Operation result Operation result 3 Yes Yes Yes Yes Yes Yes Yes 3 Operation (imm of (disp + Rn)) & T Compatibility SH2, Cycles T Bit SH2E SH4 SH-2A 3 Operation result Operation result Yes Yes Yes 0011nnnn0iii1001 ( imm of (disp + Rn)) | T T 0101dddddddddddd BORNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~( imm of (disp + Rn)) | T T 3 1101dddddddddddd BSET.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1 ( imm of (disp + Rn)) 0001dddddddddddd BSET BST.B #imm3,Rn #imm3,@(disp12,Rn) 10000110nnnn1iii 1 imm of Rn 0011nnnn0iii1001 T (imm of (disp + Rn)) 0010dddddddddddd 1 3 Yes Yes BST #imm3,Rn 10000111nnnn0iii T imm of Rn 1 Yes Rev. 3.00 Jun. 18, 2008 Page 66 of 1160 REJ09B0191-0300 Section 2 CPU Execution Instruction BXOR.B #imm3,@(disp12,Rn) Instruction Code Operation Compatibility SH2, Cycles T Bit SH2E SH4 SH-2A 3 Operation result Yes 0011nnnn0iii1001 (imm of (disp + Rn)) ^ T T 0110dddddddddddd 2.5 Processing States The CPU has five processing states: reset, exception handling, bus-released, program execution, and power-down. Figure 2.6 shows the transitions between the states. Power-on reset from any state Manual reset from any state Power-on reset state Manual reset state Reset canceled Reset state Interrupt source or DMA address error occurs Bus request cleared Exception handling state Bus request generated Exception handling source occurs Exception handling ends NMI interrupt or IRQ interrupt occurs Bus-released state Bus request generated Bus request generated Bus request cleared Bus request cleared Program execution state STBY bit set for SLEEP instruction STBY bit cleared for SLEEP instruction Sleep mode Software standby mode Power-down state Figure 2.6 Transitions between Processing States Rev. 3.00 Jun. 18, 2008 Page 67 of 1160 REJ09B0191-0300 Section 2 CPU (1) Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State The exception handling state is a transient state that occurs when exception handling sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception handling vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception handling vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. (3) Program Execution State In the program execution state, the CPU sequentially executes the program. (4) Power-Down State In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. (5) Bus-Released State In the bus-released state, the CPU releases bus to a device that has requested it. Rev. 3.00 Jun. 18, 2008 Page 68 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) Section 3 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (I), a peripheral clock (P), a bus clock (B), and an MTU clock (M). The CPG consists of a crystal oscillator, PLL circuits, and divider circuits. 3.1 Features * Two clock operating modes The mode is selected from among the two clock operating modes by the selection of the following three conditions: the frequency-divisor in use, whether the PLLs are on or off, and whether the internal crystal resonator or the input on the external clock-signal line is used. * Four clocks generated independently An internal clock (I) for the CPU and cache; a peripheral clock (P) for the on-chip peripheral modules; a bus clock (B = CKIO) for the external bus interface; an MTU clock (M) for the MTU2S module. * Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL (phase locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control The clock can be stopped for sleep mode and software standby mode, and specific modules can be stopped using the module standby function. For details on clock control in the power-down modes, see section 22, Power-Down Modes. Rev. 3.00 Jun. 18, 2008 Page 69 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) Figure 3.1 shows a block diagram of the clock pulse generator. On-chip oscillator Divider 2 x1 x1/2 x1/3 x1/4 Divider 1 x1 x1/2 x1/3 x1/4 x1/6 x1/8 x1/12 MTU clock (M, Max. 100 MHz) PLL circuit 1 (x1, 2, 3, 4, 6, 8) Internal clock (I, Max. 200 MHz) CKIO Bus clock (B = CKIO, Max. 66.67 MHz) XTAL EXTAL Crystal oscillator PLL circuit 2 (x4) Peripheral clock (P, Max. 33.33 MHz) CPG control unit MD_CLK2 MD_CLK0 Clock frequency control circuit Standby control circuit FRQCR MCLKCR STBCR STBCR2 STBCR3 STBCR4 Bus interface [Legend] FRQCR: MCLKCR: STBCR: STBCR2: STBCR3: STBCR4: Peripheral bus Frequency control register MTU clock frequency control register Standby control register Standby control register 2 Standby control register 3 Standby control register 4 Figure 3.1 Block Diagram of Clock Pulse Generator Rev. 3.00 Jun. 18, 2008 Page 70 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: (1) PLL Circuit 1 PLL circuit 1 multiplies the input clock frequency from the CKIO pin by 1, 2, 3, 4, 6, or 8. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge of the CKIO pin. (2) PLL Circuit 2 PLL circuit 2 multiplies the input clock frequency from the crystal oscillator or EXTAL pin by 4. The multiplication rate is fixed according to the clock operating mode. The clock operating mode is specified by the MD_CLK0 and MD_CLK2 pins. For details on the clock operating mode, see table 3.2. (3) Crystal Oscillator The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the XTAL pin or EXTAL pin. This can be used according to the clock operating mode. (4) Divider 1 Divider 1 generates a clock signal at the operating frequency used by the internal or peripheral clock. The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8, or 1/12 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the frequency control register (FRQCR). (5) Divider 2 Divider 2 generates a clock signal at the operating frequency used by the MTU2S. The operating frequency of the MTU2S can be 1, 1/2, 1/3, or 1/4 times the output frequency of PLL circuit 1, while it is an integer multiple of the peripheral clock (P). The division ratio is set by the MTU clock frequency control register. (6) Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency using the MD_CLK0 and MD_CLK2 pins and the frequency control register (FRQCR). Rev. 3.00 Jun. 18, 2008 Page 71 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) (7) Standby Control Circuit The standby control circuit controls the states of the clock pulse generator and other modules during clock switching, or sleep or software standby mode. (8) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin during software standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock (P). (9) MTU Clock Frequency Control Register (MCLKCR) The MTU clock frequency control register (MCLKCR) has control bits assigned for the following functions: MTU clock output/non-output and the frequency division ratio. (10) Standby Control Register The standby control register has bits for controlling the power-down modes. See section 22, Power-Down Modes, for more information. Rev. 3.00 Jun. 18, 2008 Page 72 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.2 Input/Output Pins Table 3.1 lists the clock pulse generator pins and their functions. Table 3.1 Pin Name Mode control pins Pin Configuration and Functions of the Clock Pulse Generator Symbol MD_CLK0 MD_CLK2 I/O Input Input Function (Clock Operating Mode 2) Sets the clock operating mode. Sets the clock operating mode. Function (Clock Operating Mode 7) Sets the clock operating mode. Sets the clock operating mode. Crystal input/output XTAL pins (clock input pins) EXTAL Output Connected to the crystal resonator. Leave this pin open. (Leave this pin open when the crystal resonator is not in use.) Input Connected to the crystal resonator or used to input an external clock. Fix (pull up/pull down/connect to power supply/connect to ground) this pin. Clock input pin. Clock input/output pin CKIO I/O Clock output pin. Rev. 3.00 Jun. 18, 2008 Page 73 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.3 Clock Operating Modes Table 3.2 shows the relationship between the combinations of the mode control pins (MD_CLK2 and MD_CLK0) and the clock operating modes. Table 3.3 shows the usable frequency ranges in the clock operating modes. Table 3.2 Clock Operating Modes Pin Values Mode MD_CLK2 2 7 0 1 MD_CLK0 Clock I/O Source EXTAL or crystal resonator CKIO Output CKIO PLL Circuit 2 PLL Circuit 1 On/Off On/Off ON (x4) OFF CKIO Frequency 0 1 ON (x1, 2, 3, 4) (EXTAL or crystal resonator) x4 ON (x1, 2, 3, 4, (CKIO) 6, 8) * Mode 2 The frequency of the signal received from the EXTAL pin or crystal resonator LSI is quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This enables to use the external clock of lower frequency. Either a crystal resonator with a frequency in the range from 10 to 16.67 MHz or an external signal in the same frequency range input on the EXTAL pin may be used. The frequency range of CKIO is from 40 to 66.67 MHz. * Mode 7 In mode 7, the CKIO pin functions as an input pin and draws an external clock signal. The PLL circuit 1 shapes its waveform and the setting of the frequency control register multiplies its frequency before the clock enters the LSI. For reduced current and hence power consumption, fix (pull up/pull down/connect to power supply/connect to ground) the EXTAL pin and open the XTAL pin when the LSI is used in mode 7. Rev. 3.00 Jun. 18, 2008 Page 74 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) Table 3.3 Relationship between Clock Operating Mode and Frequency Range PLL Frequency Ratio of Internal Clock Frequencies (I:B:P)* 4:4:2 4:4:4/3 4:4:1 4:4:2/3 4:4:1/2 4:4:1/3 8:4:2 8:4:4/3 8:4:1 8:4:2/3 4:4:2 4:4:4/3 4:4:1 4:4:2/3 12:4:2 12:4:1 4:4:2 4:4:1 16:4:2 16:4:4/3 8:4:2 8:4:4/3 4:4:2 4:4:4/3 1:1:1 1:1:1/2 1:1:1/3 1:1:1/4 1 Clock Operating FRQCR Mode 2 Setting H'1001 H'1002 H'1003 H'1004 H'1005 H'1006 H'1103 H'1104 H'1105 H'1106 H'1113 H'1114 H'1115 H'1116 H'120C H'120E H'122C H'122E H'1305 H'1306 H'1315 H'1316 H'1335 H'1336 7 H'1000 H'1001 H'1002 H'1003 PLL Multiplier PLL Circuit 2 ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) OFF OFF OFF OFF Selectable Frequency Range (MHz) Output Clock Input Clock*2 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 12.5 10 to 12.5 10 to 12.5 10 to 12.5 10 to 12.5 10 to 12.5 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 (CKIO Pin) 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 50 40 to 50 40 to 50 40 to 50 40 to 50 40 to 50 Internal Clock Bus Clock (I) 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 80 to 133.36 80 to 133.36 80 to 133.36 80 to 133.36 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 120 to 200 120 to 200 40 to 66.67 40 to 66.67 160 to 200 160 to 200 80 to 100 80 to 100 40 to 50 40 to 50 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 (B) 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 66.67 40 to 50 40 to 50 40 to 50 40 to 50 40 to 50 40 to 50 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 Peripheral Clock (P) 20 to 33.33 13.33 to 22.23 10 to 16.67 6.7 to 11.11 5 to 8.34 3.33 to 5.56 20 to 33.33 13.33 to 22.23 10 to 16.67 6.7 to 11.11 20 to 33.33 13.33 to 22.23 10 to 16.67 6.7 to 11.11 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 25 13.33 to 16.67 20 to 25 13.33 to 16.67 20 to 25 13.33 to 16.67 20 to 33.33 10 to 33.33 6.67 to 22.22 5 to 16.67 Circuit 1 ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x1) ON (x1) ON (x1) ON (x1) Rev. 3.00 Jun. 18, 2008 Page 75 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) PLL Frequency Clock Operating FRQCR Mode 7 Setting H'1004 H'1005 H'1006 H'1101 H'1103 H'1104 H'1105 H'1106 H'1111 H'1113 H'1114 H'1115 H'1116 H'1202 H'1204 H'120C H'1206 H'120E H'1222 H'1224 H'122C H'1226 H'122E H'1303 H'1305 H'1306 H'1313 H'1315 H'1316 PLL Circuit 1 ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) Multiplier PLL Circuit 2 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Ratio of Internal Clock Frequencies (I:B:P)* 1:1:1/6 1:1:1/8 1:1:1/12 2:1:1 2:1:1/2 2:1:1/3 2:1:1/4 2:1:1/6 1:1:1 1:1:1/2 1:1:1/3 1:1:1/4 1:1:1/6 3:1:1 3:1:1/2 3:1:1/2 3:1:1/4 3:1:1/4 1:1:1 1:1:1/2 1:1:1/2 1:1:1/4 1:1:1/4 4:1:1 4:1:1/2 4:1:1/3 2:1:1 2:1:1/2 2:1:1/3 1 Selectable Frequency Range (MHz) Output Clock Input Clock*2 20 to 66.67 20 to 66.67 20 to 66.67 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 20 to 66.67 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 20 to 66.67 20 to 33.33 20 to 40 40 to 66.67 20 to 40 40 to 66.67 20 to 33.33 20 to 40 40 to 66.67 20 to 40 40 to 66.67 20 to 33.33 20 to 50 20 to 50 20 to 33.33 20 to 50 20 to 50 (CKIO Pin) Internal Clock Bus Clock (I) 20 to 66.67 20 to 66.67 20 to 66.67 40 to 66.67 40 to 133.34 40 to 133.34 40 to 133.34 40 to 133.34 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 20 to 66.67 60 to 100 60 to 120 120 to 200 60 to 120 120 to 200 20 to 33.33 20 to 40 40 to 66.67 20 to 40 40 to 66.67 80 to 133.34 80 to 200 80 to 200 40 to 66.67 40 to 100 40 to 100 (B) 20 to 66.67 20 to 66.67 20 to 66.67 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 20 to 66.67 20 to 33.33 20 to 66.67 20 to 66.67 20 to 66.67 20 to 66.67 20 to 33.33 20 to 40 40 to 66.67 20 to 40 40 to 66.67 20 to 33.33 20 to 40 40 to 66.67 20 to 40 40 to 66.67 20 to 33.33 20 to 50 20 to 50 20 to 33.33 20 to 50 20 to 50 Peripheral Clock (P) 3.33 to 11.11 2.5 to 8.33 1.67 to 5.56 20 to 33.33 10 to 33.33 6.67 to 22.22 5 to 16.67 3.33 to 11.11 20 to 33.33 10 to 33.33 6.67 to 22.22 5 to 16.67 3.33 to 11.11 20 to 33.33 10 to 20 20 to 33.33 5 to 10 10 to 16.67 20 to 33.33 10 to 20 20 to 33.33 5 to 10 10 to 16.67 20 to 33.33 10 to 25 6.67 to 16.67 20 to 33.33 10 to 25 6.67 to 16.7 Rev. 3.00 Jun. 18, 2008 Page 76 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) PLL Frequency Clock Operating FRQCR Mode 7 Setting H'1333 H'1335 H'1336 H'1404 H'1406 H'1414 H'1416 H'1424 H'1426 H'1444 H'1446 H'1505 H'1515 H'1535 H'1555 PLL Circuit 1 ON (x4) ON (x4) ON (x4) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x8) ON (x8) ON (x8) ON (x8) Multiplier PLL Circuit 2 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Ratio of Internal Clock Frequencies (I:B:P)* 1:1:1 1:1:1/2 1:1:1/3 6:1:1 6:1:1/2 3:1:1 3:1:1/2 2:1:1 2:1:1/2 1:1:1 1:1:1/2 8:1:1 4:1:1 2:1:1 1:1:1 1 Selectable Frequency Range (MHz) Output Clock Input Clock*2 20 to 33.33 20 to 50 20 to 50 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 25 20 to 25 20 to 25 20 to 25 (CKIO Pin) Internal Clock Bus Clock (I) 20 to 33.33 20 to 50 20 to 50 120 to 200 120 to 200 60 to 100 60 to 100 40 to 66.67 40 to 66.67 20 to 33.33 20 to 33.33 160 to 200 80 to 100 40 to 50 20 to 25 (B) 20 to 33.33 20 to 50 20 to 50 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 25 20 to 25 20 to 25 20 to 25 Peripheral Clock (P) 20 to 33.33 10 to 25 6.67 to 16.67 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 25 20 to 25 20 to 25 20 to 25 Notes: Caution: 1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1. 2. In mode 2, the frequency of the clock input from the EXTAL pin or the frequency of the crystal resonator. In mode 7, the frequency of the clock input from the CKIO pin. 1. The frequency of the internal clock is the frequency of the signal input to the CKIO pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Do not set a frequency for the internal clock below the frequency of the signal on the CKIO pin. 2. The frequency of the peripheral clock is the frequency of the signal input to the CKIO pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Set the frequency of the peripheral clock to 33.33 MHz or below. In addition, do not set a higher frequency for the internal clock than the frequency on the CKIO pin. 3. The frequency multiplier of PLL circuit 1 can be selected as x1, x2, x3, x4, x6, or x8. The divisor of the divider can be selected as x1, x1/2, x1/3, x1/4, x1/6, x1/8, or x1/12. The settings are made in the frequency-control register (FRQCR). 4. The signal output by PLL circuit 1 is the signal on the CKIO pin multiplied by the frequency multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL circuit 1 is no more than 200 MHz. Rev. 3.00 Jun. 18, 2008 Page 77 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.4 Register Descriptions The clock pulse generator has the following registers. Table 3.4 Register Configuration Abbreviation R/W FRQCR R/W R/W Initial Value Address H'1003 H'43 Access Size Register Name Frequency control register H'FFFE0010 16 H'FFFE0410 8 MTU clock frequency control MCLKCR register Rev. 3.00 Jun. 18, 2008 Page 78 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and peripheral clock (P). Only word access can be used on FRQCR. FRQCR is initialized to H'1003 only by a power-on reset. FRQCR retains its previous value by a manual reset or in software standby mode. The previous value is also retained when an internal reset is triggered by an overflow of the WDT. Bit: 15 - 14 - 13 - 12 CKOEN 11 - 10 9 STC[2:0] 8 7 - 6 5 IFC[2:0] 4 3 RNGS 2 1 PFC[2:0] 0 Initial value: R/W: 0 R 0 R 0 R 1 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 CKOEN 1 R/W Clock Output Enable Specifies whether a clock is output from the CKIO pin, or whether the CKIO pin is placed in the level-fixed state during standby mode or cancellation of standby mode. If this bit is cleared to 0, the CKIO pin is fixed at low during standby mode or cancellation of standby mode. Therefore, the malfunction of an external circuit because of an unstable CKIO clock during cancellation of standby mode can be prevented. In clock operating mode 7, the CKIO pin functions as an input regardless of this bit value. 0: The CKIO pin is fixed to the low level during standby mode or cancellation of standby mode. (Clock is output during the period other than standby mode or cancellation of standby mode.) 1: Clock is output from CKIO pin (placed in the highimpedance state during standby mode). Rev. 3.00 Jun. 18, 2008 Page 79 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) Bit 11 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 STC[2:0] 000 R/W Frequency multiplication ratio of PLL circuit 1 000: x 1 time 001: x 2 times 010: x 3 times 011: x 4 times 100: x 6 times 101: x 8 times 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 IFC[2:0] 000 R/W Internal Clock Frequency Division Ratio These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. 000: x 1 time 001: x 1/2 time 010: x 1/3 time 011: x 1/4 time 100: x 1/6 time 101: x 1/8 time 3 RNGS 0 R/W PLL Circuit 1 Output Range Select Set this bit according to the output frequency of PLL circuit 1 when the multiplication ratio of PLL circuit 1 is set to 3 times. When any other multiplication ratio is set, clear this bit to 0. 0: Low frequency mode (when output frequency of PLL circuit 1 is 120 MHz or less) 1: High frequency mode (when multiplication ratio of PLL circuit 1 is 3 times while its output frequency exceeds 120 MHz) Rev. 3.00 Jun. 18, 2008 Page 80 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) Bit 2 to 0 Bit Name PFC[2:0] Initial Value 011 R/W R/W Description Peripheral Clock Frequency Division Ratio These bits specify the frequency division ratio of the peripheral clock with respect to the output frequency of PLL circuit 1. 000: x 1 time 001: x 1/2 time 010: x 1/3 time 011: x 1/4 time 100: x 1/6 time 101: x 1/8 time 110: x 1/12 time Rev. 3.00 Jun. 18, 2008 Page 81 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.4.2 MTU Clock Frequency Control Register (MCLKCR) MCLKCR is an 8-bit readable/writable register. Only byte access can be used on MCLKCR. MCLKCR is initialized to H'43 only by a power-on reset. MCLKCR retains its previous value by a manual reset or in software standby mode. Bit: 7 6 5 - 4 - 3 - 2 - 1 0 MSSCS[1:0] MSDIVS[1:0] Initial value: R/W: 0 R/W 1 R/W 0 R 0 R 0 R 0 R 1 R/W 1 R/W Bit 7, 6 Bit Name Initial Value R/W R/W Description Source Clock Select These bits select the source clock. 00: Clock stop 01: PLL1 output clock 10: Reserved (setting prohibited) 11: Reserved (setting prohibited) MSSCS[1:0] 01 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 MSDIVS[1:0] 11 R/W Division Ratio Select These bits specify the frequency division ratio of the source clock. Set these bits so that the output clock is 100 MHz or less, and also an integer multiple of the peripheral clock frequency (P). 00: x 1 time 01: x 1/2 time 10: x 1/3 time 11: x 1/4 time Rev. 3.00 Jun. 18, 2008 Page 82 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.5 Changing the Frequency The frequency of the internal clock (I) and peripheral clock (P) can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these are controlled by software through the frequency control register (FRQCR). The methods are described below. 3.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of oscillation circuit 1 is changed. The on-chip WDT counts the settling time. The oscillation stabilization time becomes the same time as that of recovery from the software standby mode. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1 time. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR.TME = 0: WDT stops WTCSR.CKS[2:0]: Division ratio of WDT count clock WTCNT counter: Initial counter value (The WDT count is incremented using the clock after the setting.) 3. Set the desired value in the STC[2:0] bits. The division ratio can also be set in the IFC[2:0] and PFC[2:0] bits. 4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral clocks both stop and the WDT is supplied with the clock. The clock will continue to be output at the CKIO pin. This state is the same as software standby mode. Whether or not registers are initialized depends on the module. For details, see section 24.3, Register States in Each Operating Mode. 5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins operating again. The WDT stops after it overflows. Rev. 3.00 Jun. 18, 2008 Page 83 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.5.2 Changing the Division Ratio Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not. 1. In the initial state, IFC[2:0] = B'000 and PFC[2:0] = B'011. 2. Set the desired value in the IFC[2:0] and PFC[2:0] bits. The values that can be set are limited by the clock operating mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, this LSI will malfunction. 3. After the register bits (IFC[2:0] and PFC[2:0]) have been set, the clock is supplied of the new division ratio. Note: When executing the SLEEP instruction after the frequency has been changed, be sure to read the frequency control register (FRQCR) three times before executing the SLEEP instruction. Rev. 3.00 Jun. 18, 2008 Page 84 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.6 3.6.1 Notes on Board Design Note on Inputting External Clock Figure 3.2 is an example of connecting the external clock input. When putting the XTAL pin in open state, make sure the parasitic capacitance is less than or equal to 10 pF. To stably input the external clock at power on or releasing the standby, wait longer than the oscillation stabilizing time. EXTAL External clock input XTAL Open state Example of connection with XTAL pin open Figure 3.2 Example of Connecting External Clock For details on input conditions of the external clock, see section 25.4.1, Clock Timing. 3.6.2 Note on Using an External Crystal Resonator Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close to these components. Signal lines prohibited CL1 CL2 Reference value CL1 = 10 pF CL2 = 10 pF EXTAL XTAL This LSI Note: The values for CL1 and CL2 should be determined after consultation with the crystal resonator manufacturer. Figure 3.3 Note on Using a Crystal Resonator Rev. 3.00 Jun. 18, 2008 Page 85 of 1160 REJ09B0191-0300 Section 3 Clock Pulse Generator (CPG) 3.6.3 Note on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the parameters for the oscillation circuit will depend on the floating capacitance of the resonator and the user board, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. 3.6.4 Note on Bypass Capacitor A multilayer ceramic capacitor should be inserted for each pair of Vss and Vcc as a bypass capacitor as many as possible. The bypass capacitor must be inserted as close to the power supply pins of the LSI as possible. Note that the capacitance and frequency characteristics of the bypass capacitor must be appropriate for the operating frequency of the LSI. 3.6.5 Note on Using a PLL Oscillation Circuit In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. To prevent such malfunction, the analog power supply pin Vcc and digital power supply pin PVcc should not supply the same resources on the board if at all possible. Signal lines prohibited Power supply PLLVcc Vcc PLLVss Vss Figure 3.4 Note on Using a PLL Oscillation Circuit Rev. 3.00 Jun. 18, 2008 Page 86 of 1160 REJ09B0191-0300 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Types of Exception Handling and Priority Exception handling is started by sources, such as resets, address errors, register bank errors, interrupts, and instructions. Table 4.1 shows their priorities. When several exception handling sources occur at once, they are processed according to the priority shown. Table 4.1 Type Reset Types of Exception Handling and Priority Order Exception Handling Power-on reset Manual reset Priority High Address error Instruction CPU address error DMAC address error Integer division exception (division by zero) Integer division exception (overflow) Register bank error Interrupt Bank underflow Bank overflow NMI User break H-UDI IRQ PINT On-chip peripheral modules A/D converter (ADC) Direct memory access controller (DMAC) Compare match timer (CMT) Bus state controller (BSC) Watchdog timer (WDT) Multi-function timer pulse unit 2 (MTU2) Port output enable 2 (POE2): OEI1 and OEI2 interrupts Low Rev. 3.00 Jun. 18, 2008 Page 87 of 1160 REJ09B0191-0300 Section 4 Exception Handling Type Interrupt Exception Handling On-chip peripheral modules Priority Multi-function timer pulse unit 2S (MTU2S) High Port output enable 2 (POE2): OEI3 interrupt I2C bus interface 3 (IIC3) Serial communication interface with FIFO (SCIF) Instruction Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed 1 2 branch instruction* , instructions that rewrite the PC* , 32-bit 3 instructions* , RESBANK instruction, DIVS instruction, and DIVU instruction) Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N. 3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. Rev. 3.00 Jun. 18, 2008 Page 88 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.1.2 Exception Handling Operations The exception handling sources are detected and begin processing according to the timing shown in table 4.2. Table 4.2 Exception Reset Timing of Exception Source Detection and Start of Exception Handling Source Power-on reset Timing of Source Detection and Start of Handling Starts when the RES pin changes from low to high, when the H-UDI reset negate command is set after the H-UDI reset assert command has been set, or when the WDT overflows. Starts when the MRES pin changes from low to high or when the WDT overflows. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Starts upon attempted execution of a RESBANK instruction when saving has not been performed to register banks. In the state where saving has been performed to all register bank areas, starts when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except immediately after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed immediately after a delayed branch instruction (delay slot), of instructions that rewrite the PC, of 32-bit instructions, of the RESBANK instruction, of the DIVS instruction, or of the DIVU instruction. Starts when detecting division-by-zero exception or overflow exception caused by division of the negative maximum value (H'80000000) by -1. Manual reset Address error Interrupts Register bank Bank underflow error Bank overflow Instructions Trap instruction General illegal instructions Slot illegal instructions Integer division exceptions Rev. 3.00 Jun. 18, 2008 Page 89 of 1160 REJ09B0191-0300 Section 4 Exception Handling When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 4.1.3, Exception Handling Vector Table, for more information. The vector base register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the interrupt controller (INTC) is also initialized to 0. The program begins running from the PC address fetched from the exception handling vector table. (2) Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts, and Instructions SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling other than NMI or user breaks with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved to the register banks. In the case of exception handling due to an address error, register bank error, NMI interrupt, user break interrupt, or instruction, saving to a register bank is not performed. When saving is performed to all register banks, automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow exception will be generated. In the case of interrupt exception handling, the interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to an address error or instruction, the I3 to I0 bits are not affected. The exception service routine start address is then fetched from the exception handling vector table and the program begins running from that address. Rev. 3.00 Jun. 18, 2008 Page 90 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.1.3 Exception Handling Vector Table Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception handling, the start addresses of the exception service routines are fetched from the exception handling vector table, which is indicated by this vector table address. Table 4.3 shows the vector numbers and vector table address offsets. Table 4.4 shows how vector table addresses are calculated. Table 4.3 Exception Handling Vector Table Vector Numbers PC SP Manual reset PC SP General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) 0 1 2 3 4 5 6 7 8 CPU address error DMAC address error Interrupts NMI User break (Reserved by system) H-UDI Bank overflow Bank underflow 9 10 11 12 13 14 15 16 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 H'00000038 to H'0000003B H'0000003C to H'0000003F H'00000040 to H'00000043 Exception Sources Power-on reset Rev. 3.00 Jun. 18, 2008 Page 91 of 1160 REJ09B0191-0300 Section 4 Exception Handling Exception Sources Integer division exception (division by zero) Integer division exception (overflow) (Reserved by system) Vector Numbers 17 18 19 : 31 Vector Table Address Offset H'00000044 to H'00000047 H'00000048 to H'0000004B H'0000004C to H'0000004F : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF H'00000100 to H'00000103 : H'000007FC to H'000007FF Trap instruction (user vector) 32 : 63 External interrupts (IRQ, PINT), on-chip peripheral module interrupts* 64 : 511 Note: * The vector numbers and vector table address offsets for each external interrupt and onchip peripheral module interrupt are given in table 5.4 in section 5, Interrupt Controller (INTC). Table 4.4 Calculating Exception Handling Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) x 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4 Exception Source Resets Address errors, register bank errors, interrupts, instructions Notes: 1. Vector table address offset: See table 4.3. 2. Vector number: See table 4.3. Rev. 3.00 Jun. 18, 2008 Page 92 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.2 4.2.1 Resets Input/Output Pins Table 4.5 shows the reset-related pin configuration. Table 4.5 Pin Name Power-on reset Manual reset Pin Configuration Symbol I/O Input Input Function When this pin is driven low, this LSI shifts to the poweron reset processing When this pin is driven low, this LSI shifts to the manual reset processing. RES MRES 4.2.2 Types of Reset A reset is the highest-priority exception handling source. There are two kinds of reset, power-on and manual. As shown in table 4.6, the CPU state is initialized in both a power-on reset and a manual reset. On-chip peripheral module registers are initialized by a power-on reset, but not by a manual reset. Table 4.6 Reset States Conditions for Transition to Reset State WDT Overflow -- -- Power-on reset -- Internal States WRCSR of On-Chip WDT, FRQCR of Peripheral Modules, I/O Port CPG Initialized Initialized Not initialized Type Power-on reset RES Low High High H-UDI Command -- MRES -- CPU Initialized Initialized Initialized Initialized Initialized Initialized H-UDI reset assert -- command is set Command other than H-UDI reset assert is set Command other than H-UDI reset assert is set Command other than H-UDI reset assert is set -- Manual reset High Low Initialized Not initialized* Not initialized High High Manual reset Initialized Not initialized* Not initialized Note: * The BN bit in IBNR of the INTC is initialized. Rev. 3.00 Jun. 18, 2008 Page 93 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.2.3 (1) Power-On Reset Power-On Reset by Means of RES Pin When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc (unfixed) when the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip peripheral module registers are initialized. See appendix A, Pin States, for the status of individual pins during the power-on reset state. In the power-on reset state, power-on reset exception handling starts when the RES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the INTC is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. (2) Power-On Reset by Means of H-UDI Reset Assert Command When the H-UDI reset assert command is set, this LSI enters the power-on reset state. Power-on reset by means of an H-UDI reset assert command is equivalent to power-on reset by means of the RES pin. Setting the H-UDI reset negate command cancels the power-on reset state. The time required between an H-UDI reset assert command and H-UDI reset negate command is the same as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state generated by an H-UDI reset assert command, setting the H-UDI reset negate command starts power-on reset exception handling. The CPU operates in the same way as when a power-on reset was caused by the RES pin. Rev. 3.00 Jun. 18, 2008 Page 94 of 1160 REJ09B0191-0300 Section 4 Exception Handling (3) Power-On Reset Initiated by WDT When a setting is made for a power-on reset to be generated in the WDT's watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the power-on reset state. In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal generated by the WDT. If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset exception processing is started by the WDT, the CPU operates in the same way as when a poweron reset was caused by the RES pin. Rev. 3.00 Jun. 18, 2008 Page 95 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.2.4 (1) Manual Reset Manual Reset by Means of MRES Pin When the MRES pin is driven low, this LSI enters the manual reset state. In the manual reset state, the CPU's internal state is initialized, but all the on-chip peripheral module registers are not initialized. In the manual reset state, manual reset exception handling starts when the MRES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the INTC is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. (2) Manual Reset Initiated by WDT When a setting is made for a manual reset to be generated in the WDT's watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the manual reset state. When manual reset exception processing is started by the WDT, the CPU operates in the same way as when a manual reset was caused by the MRES pin. (3) Note on Manual Reset When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception handling will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the interval which MRES pin driven at low level or the fixed internal manual reset interval cycles, the manual reset source is ignored instead of being deferred, and manual reset exception handling is not executed. Rev. 3.00 Jun. 18, 2008 Page 96 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.3 4.3.1 Address Errors Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 4.7. Table 4.7 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* Instruction fetched from on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* Data read/write CPU or DMAC Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* Note: * Address Errors None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) None (normal) See section 8, Bus State Controller (BSC), for details of the on-chip peripheral module space and on-chip RAM space. Rev. 3.00 Jun. 18, 2008 Page 97 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.3.2 Address Error Exception Handling When an address error occurs, the bus cycle in which the address error occurred ends.* When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the address error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Note: * In the case of an address error caused by instruction fetching when data is read or written, if the bus cycle on which the address error occurred is not completed by the end of the operations described above, the CPU will recommence address error exception processing until the end of that bus cycle. Rev. 3.00 Jun. 18, 2008 Page 98 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.4 4.4.1 (1) Register Bank Errors Register Bank Error Sources Bank Overflow In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. (2) Bank Underflow Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving has not been performed to register banks. 4.4.2 Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a bank overflow, and the start address of the executed RESBANK instruction for a bank underflow. To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Rev. 3.00 Jun. 18, 2008 Page 99 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.5 4.5.1 Interrupts Interrupt Sources Table 4.8 shows the sources that start up interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules. Table 4.8 Type NMI User break H-UDI IRQ PINT On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) User break controller (UBC) High-performance user debugging interface (H-UDI) IRQ0 to IRQ7 pins (external input) PINT0 to PINT7 pins (external input) A/D converter (ADC) Direct memory access controller (DMAC) Compare match timer (CMT) Bus state controller (BSC) Watchdog timer (WDT) Multi-function timer pulse unit 2 (MTU2) Multi-function timer pulse unit 2S (MTU2S) Port output enable 2 (POE2) I C bus interface 3 (IIC3) Serial communication interface with FIFO (SCIF) 2 Number of Sources 1 1 1 8 8 2 16 2 1 1 26 13 3 5 16 Each interrupt source is allocated a different vector number and vector table offset. See table 5.4 in section 5, Interrupt Controller (INTC), for more information on vector numbers and vector table address offsets. Rev. 3.00 Jun. 18, 2008 Page 100 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.5.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts processing according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt priority registers 01, 02, and 05 to 14 (IPR01, IPR02, and IPR05 to IPR14) of the INTC as shown in table 4.9. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 5.3.1, Interrupt Priority Registers 01, 02, 05 to 14 (IPR01, IPR02, IPR05 to IPR14), for details of IPR01, IPR02, and IPR05 to IPR14. Table 4.9 Type NMI User break H-UDI IRQ PINT On-chip peripheral module Interrupt Priority Order Priority Level 16 15 15 0 to 15 Comment Fixed priority level. Cannot be masked. Fixed priority level. Fixed priority level. Set with interrupt priority registers 01, 02, and 05 to 14 (IPR01, IPR02, and IPR05 to IPR14). Rev. 3.00 Jun. 18, 2008 Page 101 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.5.3 Interrupt Exception Handling When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR). When an interrupt is accepted, interrupt exception handling begins. In interrupt exception handling, the CPU fetches the exception service routine start address which corresponds to the accepted interrupt from the exception handling vector table, and saves SR and the program counter (PC) to the stack. In the case of interrupt exception handling other than NMI or user breaks with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved in the register banks. In the case of exception handling due to an address error, NMI interrupt, user break interrupt, or instruction, saving is not performed to the register banks. If saving has been performed to all register banks (0 to 14), automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow exception occurs. Next, the priority level value of the accepted interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority level is 16, but the value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. See section 5.6, Operation, for further details of interrupt exception handling. Rev. 3.00 Jun. 18, 2008 Page 102 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.6 4.6.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, and integer division exceptions, as shown in table 4.10. Table 4.10 Types of Exceptions Triggered by Instructions Type Trap instruction Slot illegal instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot), instructions that rewrite the PC, 32-bit instructions, RESBANK instruction, DIVS instruction, and DIVU instruction Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. Comment General illegal instructions Integer division exceptions Undefined code anywhere besides in a delay slot Division by zero Negative maximum value / (-1) DIVU, DIVS DIVS Rev. 3.00 Jun. 18, 2008 Page 103 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.6.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 4.6.3 Slot Illegal Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, an instruction that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction, slot illegal exception handling starts when such kind of instruction is decoded. The CPU operates as follows: 1. The exception service routine start address is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code, the instruction that rewrites the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 4.6.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot illegal instructions, however, the program counter value stored is the start address of the undefined code. Rev. 3.00 Jun. 18, 2008 Page 104 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.6.5 Integer Division Exceptions When an integer division instruction performs division by zero or the result of integer division overflows, integer division instruction exception handling starts. The instructions that may become the source of division-by-zero exception are DIVU and DIVS. The only source instruction of overflow exception is DIVS, and overflow exception occurs only when the negative maximum value is divided by -1. The CPU operates as follows: 1. The exception service routine start address which corresponds to the integer division instruction exception that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the integer division instruction at which the exception occurred. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Rev. 3.00 Jun. 18, 2008 Page 105 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.7 When Exception Sources Are Not Accepted When an address error, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown in table 4.11. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 4.11 Exception Source Generation Immediately after Delayed Branch Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction* Note: * Address Error Not accepted Register Bank Error (Overflow) Not accepted Interrupt Not accepted Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Rev. 3.00 Jun. 18, 2008 Page 106 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.8 Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 4.12. Table 4.12 Stack Status After Exception Handling Ends Exception Type Address error SP Stack Status Address of instruction after executed instruction SR 32 bits 32 bits Interrupt SP Address of instruction after executed instruction SR 32 bits 32 bits Register bank error (overflow) SP Address of instruction after executed instruction SR 32 bits 32 bits Register bank error (underflow) SP Start address of relevant RESBANK instruction SR 32 bits 32 bits Trap instruction SP Address of instruction after TRAPA instruction SR 32 bits 32 bits Slot illegal instruction SP Jump destination address of delayed branch instruction SR 32 bits 32 bits Rev. 3.00 Jun. 18, 2008 Page 107 of 1160 REJ09B0191-0300 Section 4 Exception Handling Exception Type General illegal instruction Stack Status SP Start address of general illegal instruction SR 32 bits 32 bits Integer division exception SP Start address of relevant integer division instruction SR 32 bits 32 bits Rev. 3.00 Jun. 18, 2008 Page 108 of 1160 REJ09B0191-0300 Section 4 Exception Handling 4.9 4.9.1 Usage Notes Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 4.9.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 4.9.3 Address Errors Caused by Stacking of Address Error Exception Handling When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception handling (interrupts, etc.) and address error exception handling will start up as soon as the first exception handling is ended. Address errors will then also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. Rev. 3.00 Jun. 18, 2008 Page 109 of 1160 REJ09B0191-0300 Section 4 Exception Handling Rev. 3.00 Jun. 18, 2008 Page 110 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Section 5 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 5.1 Features * 16 levels of interrupt priority can be set By setting the twelve interrupt priority registers, the priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request sources. * NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as the noise canceler function. * Occurrence of interrupt can be reported externally (IRQOUT pin) For example, when this LSI has released the bus mastership, this LSI can inform the external bus master of occurrence of an on-chip peripheral module interrupt and request for the bus mastership. * Register banks This LSI has register banks that enable register saving and restoration required in the interrupt processing to be performed at high speed. Rev. 3.00 Jun. 18, 2008 Page 111 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Figure 5.1 shows a block diagram of the INTC. IRQOUT NMI IRQ7 to IRQ0 PINT7 to PINT0 UBC H-UDI DMAC CMT BSC WDT MTU2 MTU2S POE2 ADC IIC3 SCIF Input control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Comparator Priority identifier Interrupt request SR I3 I2 I1 I0 CPU ICR0 ICR2 PINTER IBCR ICR1 IRQRR PIRR IBNR IPR IPR01, IPR02, IPR05 to IPR14 Module bus INTC [Legend] UBC: User break controller H-UDI: High-performance user debugging interface DMAC: Direct memory access controller CMT: Compare match timer BSC: Bus state controller WDT: Watchdog timer MTU2: Multi-function timer pulse unit 2 MTU2S: Multi-function timer pulse unit 2S POE2: Port output enable 2 ADC: A/D converter IIC3: I2C bus interface 3 SCIF: Serial communication interface with FIFO Bus interface ICR0: Interrupt control register 0 ICR1: Interrupt control register 1 ICR2: Interrupt control register 2 IRQRR: IRQ interrupt request register PINTER: PINT interrupt enable register PIRR: PINT interrupt request register IBCR: Bank control register IBNR: Bank number register IPR01, IPR02, IPR05 to IPR14: Interrupt priority registers 01, 02, 05 to 14 Figure 5.1 Block Diagram of INTC Rev. 3.00 Jun. 18, 2008 Page 112 of 1160 REJ09B0191-0300 Peripheral bus Section 5 Interrupt Controller (INTC) 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the INTC. Table 5.1 Pin Name Nonmaskable interrupt input pin Interrupt request input pins Pin Configuration Symbol NMI IRQ7 to IRQ0 IRQOUT I/O Input Input Function Input of nonmaskable interrupt request signal Input of maskable interrupt request signals Output of signal to report occurrence of interrupt source PINT7 to PINT0 Input Interrupt request output pin Output Rev. 3.00 Jun. 18, 2008 Page 113 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3 Register Descriptions The INTC has the following registers. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 5.2 Register Configuration Abbreviation R/W ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR IPR01 IPR02 IPR05 IPR06 IPR07 IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 R/W R/W R/W R/(W)* R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Register Name Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 IRQ interrupt request register PINT interrupt enable register PINT interrupt request register Bank control register Bank number register Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 05 Interrupt priority register 06 Interrupt priority register 07 Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt priority register 14 Initial Value *1 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFE0800 H'FFFE0802 H'FFFE0804 H'FFFE0806 H'FFFE0808 H'FFFE080A H'FFFE080C H'FFFE080E H'FFFE0818 H'FFFE081A H'FFFE0820 H'FFFE0C00 H'FFFE0C02 H'FFFE0C04 H'FFFE0C06 H'FFFE0C08 H'FFFE0C0A H'FFFE0C0C H'FFFE0C0E H'FFFE0C10 Access Size 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 Notes: 1. When the NMI pin is high, becomes H'8000; when low, becomes H'0000. 2. Only 0 can be written after reading 1, to clear the flag. Rev. 3.00 Jun. 18, 2008 Page 114 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.1 Interrupt Priority Registers 01, 02, 05 to 14 (IPR01, IPR02, IPR05 to IPR14) IPR01, IPR02, and IPR05 to IPR14 are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. Table 5.3 shows the correspondence between the interrupt request sources and the bits in IPR01, IPR02, and IPR05 to IPR14. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Table 5.3 Interrupt Request Sources and IPR01, IPR02, and IPR05 to IPR14 Bits 15 to 12 IRQ0 IRQ4 PINT7 to PINT0 DMAC0 DMAC4 CMT0 Bits 11 to 8 IRQ1 IRQ5 Reserved DMAC1 DMAC5 CMT1 Bits 7 to 4 IRQ2 IRQ6 ADI0 DMAC2 DMAC6 BSC MTU1 (TGI1A, TGI1B) Bits 3 to 0 IRQ3 IRQ7 ADI1 DMAC3 DMAC7 WDT MTU1 (TCI1V, TCI1U) Register Name Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 05 Interrupt priority register 06 Interrupt priority register 07 Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 MTU0 MTU0 (TGI0A to TGI0D) (TCI0V, TGI0E, TGI0F) MTU2 (TGI2A, TGI2B) MTU2 (TCI2V, TCI2U) MTU3 MTU3 (TGI3A to TGI3D) (TCI3V) MTU5 (TGI5U, TGI5V, TGI5W) POE2 (OEI1, OEI2) MTU4 MTU4 (TGI4A to TGI4D) (TCI4V) MTU3S MTU3S (TGI3A to TGI3D) (TCI3V) MTU4S MTU4S (TGI4A to TGI4D) (TCI4V) Rev. 3.00 Jun. 18, 2008 Page 115 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Register Name Interrupt priority register 13 Interrupt priority register 14 Bits 15 to 12 MTU5S (TGI5U, TGI5V, TGI5W) SCIF0 Bits 11 to 8 POE2 (OEI3) SCIF1 Bits 7 to 4 IIC3 Bits 3 to 0 Reserved SCIF2 SCIF3 As shown in table 5.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set. Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the highest level). IPR01, IPR02, and IPR05 to IPR14 are initialized to H'0000 by a power-on reset. Rev. 3.00 Jun. 18, 2008 Page 116 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. ICR0 is initialized by a power-on reset. Bit: 15 NMIL 14 - 13 - 12 - 11 - 10 - 9 - 8 NMIE 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: * R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: * 1 when the NMI pin is high, and 0 when the NMI pin is low. Bit 15 Bit Name NMIL Initial Value * R/W R Description NMI Input Level Sets the level of the signal input at the NMI pin. The NMI pin level can be obtained by reading this bit. This bit cannot be modified. 0: Low level is input to NMI pin 1: High level is input to NMI pin 14 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal on the NMI pin is detected. 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 117 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [Legend] n = 7 to 0 Bit Name IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQ Sense Select These bits select whether interrupt signals corresponding to pins IRQ7 to IRQ0 are detected by a low level, falling edge, rising edge, or both edges. 00: Interrupt request is detected on low level of IRQn input 01: Interrupt request is detected on falling edge of IRQn input 10: Interrupt request is detected on rising edge of IRQn input 11: Interrupt request is detected on both edges of IRQn input Rev. 3.00 Jun. 18, 2008 Page 118 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7 to PINT0 individually: low level or high level. ICR2 is initialized by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 [Legend] n = 7 to 0 PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PINT Sense Select These bits select whether interrupt signals corresponding to pins PINT7 to PINT0 are detected by a low level or high level. 0: Interrupt request is detected on low level of PINTn input 1: Interrupt request is detected on high level of PINTn input Rev. 3.00 Jun. 18, 2008 Page 119 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.5 IRQ Interrupt Request Register (IRQRR) IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the retained interrupts. IRQRR is initialized by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 120 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description IRQ Interrupt Request These bits indicate the status of the IRQ7 to IRQ0 interrupt requests. Level detection: 0: IRQn interrupt request has not occurred [Clearing condition] R/(W)* * IRQn input is high R/(W)* 1: IRQn interrupt has occurred [Setting condition] R/(W)* * IRQn input is low Edge detection: 0: IRQn interrupt request is not detected [Clearing conditions] * * Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF Cleared by executing IRQn interrupt exception handling 1: IRQn interrupt request is detected [Setting condition] * [Legend] n = 7 to 0 Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at IRQn pin Rev. 3.00 Jun. 18, 2008 Page 121 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.6 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit register that enables interrupt request inputs to external interrupt input pins PINT7 to PINT0. PINTER is initialized by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 [Legend] n = 7 to 0 PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PINT Enable These bits select whether to enable interrupt request inputs to external interrupt input pins PINT7 to PINT0. 0: PINTn input interrupt request is disabled 1: PINTn input interrupt request is enabled Rev. 3.00 Jun. 18, 2008 Page 122 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.7 PINT Interrupt Request Register (PIRR) PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to PINT0. PIRR is initialized by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 [Legend] n = 7 to 0 PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R 0 0 0 0 0 0 0 0 R R R R R R R R PINT Interrupt Request These bits indicate the status of the PINT7 to PINT0 interrupt requests. 0: No interrupt request at PINTn pin 1: Interrupt request at PINTn pin Rev. 3.00 Jun. 18, 2008 Page 123 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.8 Bank Control Register (IBCR) IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. IBCR is initialized to H'0000 by a power-on reset. Bit: 15 E15 14 E14 13 E13 12 E12 11 E11 10 E10 9 E9 8 E8 7 E7 6 E6 5 E5 4 E4 3 E3 2 E2 1 E1 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Description Enable These bits enable or disable use of register banks for interrupt priority levels 15 to 1. However, use of register banks is always disabled for the user break interrupts. 0: Use of register banks is disabled 1: Use of register banks is enabled Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 124 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.3.9 Bank Number Register (IBNR) IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to BN0. IBNR is initialized to H'0000 by a power-on reset. Bit: 15 14 13 BOVE 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 1 0 BE[1:0] BN[3:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15, 14 Bit Name BE[1:0] Initial Value 00 R/W R/W Description Register Bank Enable These bits enable or disable use of register banks. 00: Use of register banks is disabled for all interrupts. The setting of IBCR is ignored. 01: Use of register banks is enabled for all interrupts except NMI and user break. The setting of IBCR is ignored. 10: Reserved (setting prohibited) 11: Use of register banks is controlled by the setting of IBCR. 13 BOVE 0 R/W Register Bank Overflow Enable Enables of disables register bank overflow exception. 0: Generation of register bank overflow exception is disabled 1: Generation of register bank overflow exception is enabled 12 to 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 125 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Bit 3 to 0 Bit Name BN[3:0] Initial Value 0000 R/W R Description Bank Number These bits indicate the bank number to which saving is performed next. When an interrupt using register banks is accepted, saving is performed to the register bank indicated by these bits, and BN is incremented by 1. After BN is decremented by 1 due to execution of a RESBANK (restore from register bank) instruction, restoration from the register bank is performed. Rev. 3.00 Jun. 18, 2008 Page 126 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.4 Interrupt Sources There are six types of interrupt sources: NMI, user break, H-UDI, IRQ, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to level 0, that interrupt is masked at all times. 5.4.1 NMI Interrupt The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) selects whether the rising edge or falling edge is detected. Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. 5.4.2 User Break Interrupt A user break interrupt which occurs when a break condition set in the user break controller (UBC) matches has a priority level of 15. The user break interrupt exception handling sets the I3 to I0 bits in SR to level 15. For user break interrupts, see section 6, User Break Controller (UBC). 5.4.3 H-UDI Interrupt The high-performance user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial input of an H-UDI interrupt instruction. H-UDI interrupt requests are edgedetected and retained until they are accepted. The H-UDI interrupt exception handling sets the I3 to I0 bits in SR to level 15. For H-UDI interrupts, see section 23, High-Performance User Debugging Interface (H-UDI). Rev. 3.00 Jun. 18, 2008 Page 127 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.4.4 IRQ Interrupts IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority registers 01 and 02 (IPR01 and IPR02). When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the INTC while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR). When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ interrupt request detection is retained until that interrupt request is accepted. Whether IRQ interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request detection. The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted IRQ interrupt. When returning from IRQ interrupt exception service routine, execute the RTE instruction after confirming that the interrupt request has been cleared by the IRQ interrupt request register (IRQRR) so as not to accidentally receive the interrupt request again. 5.4.5 PINT Interrupts PINT interrupts are input from pins PINT7 to PINT0. Input of the interrupt requests is enabled by the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable register (PINTER). For the PINT7 to PINT0 interrupts, low-level or high-level detection can be selected individually for each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt control register 2 (ICR2). A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0 interrupts by bits 15 to 12 in interrupt priority register 05 (IPR05). When using low-level sensing for the PINT7 to PINT0 interrupts, an interrupt request signal is sent to the INTC while the PINT7 to PINT0 pins are low. An interrupt request signal is stopped being sent to the INTC when the PINT7 to PINT0 pins are driven high. The status of the interrupt requests can be checked by reading the PINT interrupt request bits (PINT7R to PINT0R) in the Rev. 3.00 Jun. 18, 2008 Page 128 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) PINT interrupt request register (PIRR). The above description also applies to when using highlevel sensing, except for the polarity being reversed. The PINT interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the PINT interrupt. When returning from IRQ interrupt exception service routine, execute the RTE instruction after confirming that the interrupt request has been cleared by the PINT interrupt request register (PIRR) so as not to accidentally receive the interrupt request again. 5.4.6 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following on-chip peripheral modules: * * * * * * * * * * A/D converter (ADC) Direct memory access controller (DMAC) Compare match timer (CMT) Bus state controller (BSC) Watchdog timer (WDT) Multi-function timer pulse unit 2 (MTU2) Multi-function timer pulse unit 2S (MTU2S) Port output enable 2 (POE2) I2C bus interface 3 (IIC3) Serial communication interface with FIFO (SCIF) As every source is assigned a different interrupt vector, the source does not need to be identified in the exception service routine. A priority level in a range from 0 to 15 can be set for each module by interrupt priority registers 05 to 14 (IPR05 to IPR14). The on-chip peripheral module interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip peripheral module interrupt. Rev. 3.00 Jun. 18, 2008 Page 129 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.5 Interrupt Exception Handling Vector Table and Priority Table 5.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and vector table address offsets. In interrupt exception handling, the interrupt exception service routine start address is fetched from the vector table indicated by the vector table address. For details of calculation of the vector table address, see table 4.4, Calculating Exception Handling Vector Table Addresses, in section 4, Exception Handling. The priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 05 to 14 (IPR01, IPR02, and IPR05 to IPR14). However, if two or more interrupts specified by the same IPR among IPR05 to IPR14 occur, the priorities are defined as shown in the IPR setting unit internal priority of table 5.4, and the priorities cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priorities indicated in table 5.4. Rev. 3.00 Jun. 18, 2008 Page 130 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Table 5.4 Interrupt Exception Handling Vectors and Priorities Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000038 to H'0000003B H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B H'0000011C to H'0000011F 16 15 15 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR Setting Unit Internal Priority Interrupt Source NMI User break H-UDI IRQ IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Vector 11 12 14 64 65 66 67 68 69 70 71 Default Priority High IPR01 (15 to 12) IPR01 (11 to 8) IPR01 (7 to 4) IPR01 (3 to 0) IPR02 (15 to 12) IPR02 (11 to 8) IPR02 (7 to 4) IPR02 (3 to 0) Low Rev. 3.00 Jun. 18, 2008 Page 131 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'00000140 to H'00000143 H'00000144 to H'00000147 H'00000148 to H'0000014B H'0000014C to H'0000014F H'00000150 to H'00000153 H'00000154 to H'00000157 H'00000158 to H'0000015B H'0000015C to H'0000015F H'00000170 to H'00000173 H'00000180 to H'00000183 H'000001B0 to H'000001B3 H'000001B4 to H'000001B7 H'000001C0 to H'000001C3 H'000001C4 to H'000001C7 H'000001D0 to H'000001D3 H'000001D4 to H'000001D7 0 to 15 (0) IPR06 (7 to 4) 0 to 15 (0) IPR06 (11 to 8) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR05 (7 to 4) IPR05 (3 to 0) 0 to 15 (0) Interrupt Source PINT PINT0 PINT1 PINT2 PINT3 PINT4 PINT5 PINT6 PINT7 ADC ADI0 ADI1 DMAC DMAC0 DEI0 HEI0 DMAC1 DEI1 HEI1 DMAC2 DEI2 HEI2 Vector 80 81 82 83 84 85 86 87 92 96 108 109 112 113 116 117 IPR Setting Unit Internal Priority Default Priority High IPR05 (15 to 12) 1 2 3 4 5 6 7 8 IPR06 (15 to 12) 1 2 1 2 1 2 Low Rev. 3.00 Jun. 18, 2008 Page 132 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'000001E0 to H'000001E3 H'000001E4 to H'000001E7 H'000001F0 to H'000001F3 H'000001F4 to H'000001F7 H'00000200 to H'00000203 H'00000204 to H'00000207 H'00000210 to H'00000213 H'00000214 to H'00000217 H'00000220 to H'00000223 H'00000224 to H'00000227 H'00000230 to H'00000233 H'00000240 to H'00000243 H'00000250 to H'00000253 H'00000260 to H'00000263 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR07 (3 to 0) 0 to 15 (0) IPR07 (7 to 4) 0 to 15 (0) IPR07 (11 to 8) 0 to 15 (0) 0 to 15 (0) IPR06 (3 to 0) Interrupt Source DMAC DMAC3 DEI3 HEI3 DMAC4 DEI4 HEI4 DMAC5 DEI5 HEI5 DMAC6 DEI6 HEI6 DMAC7 DEI7 HEI7 CMT CMI0 CMI1 BSC WDT CMI ITI Vector 120 121 124 125 128 129 132 133 136 137 140 144 148 152 IPR Setting Unit Internal Priority 1 2 Default Priority High IPR07 (15 to 12) 1 2 1 2 1 2 1 2 IPR08 (15 to 12) IPR08 (11 to 8) IPR08 (7 to 4) IPR08 (3 to 0) Low Rev. 3.00 Jun. 18, 2008 Page 133 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'00000270 to H'00000273 H'00000274 to H'00000277 H'00000278 to H'0000027B H'0000027C to H'0000027F H'00000280 to H'00000283 H'00000284 to H'00000287 H'00000288 to H'0000028B H'00000290 to H'00000293 H'00000294 to H'00000297 H'000002A0 to H'000002A3 H'000002A4 to H'000002A7 H'000002B0 to H'000002B3 H'000002B4 to H'000002B7 H'000002C0 to H'000002C3 H'000002C4 to H'000002C7 0 to 15 (0) IPR10 (11 to 8) 0 to 15 (0) 0 to 15 (0) IPR09 (3 to 0) 0 to 15 (0) IPR09 (7 to 4) 0 to 15 (0) IPR09 (11 to 8) 0 to 15 (0) Interrupt Source MTU2 MTU0 TGI0A TGI0B TGI0C TGI0D TCI0V TGI0E TGI0F MTU1 TGI1A TGI1B TCI1V TCI1U MTU2 TGI2A TGI2B TCI2V TCI2U Vector 156 157 158 159 160 161 162 164 165 168 169 172 173 176 177 IPR Setting Unit Internal Priority Default Priority High IPR09 (15 to 12) 1 2 3 4 1 2 3 1 2 1 2 IPR10 (15 to 12) 1 2 1 2 Low Rev. 3.00 Jun. 18, 2008 Page 134 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'000002D0 to H'000002D3 H'000002D4 to H'000002D7 H'000002D8 to H'000002DB H'000002DC to H'000002DF H'000002E0 to H'000002E3 H'000002F0 to H'000002F3 H'000002F4 to H'000002F7 H'000002F8 to H'000002FB H'000002FC to H'000002FF H'00000300 to H'00000303 H'00000310 to H'00000313 H'00000314 to H'00000317 H'00000318 to H'0000031B H'00000320 to H'00000323 H'00000324 to H'00000327 0 to 15 (0) IPR11 (3 to 0) 0 to 15 (0) 0 to 15 (0) IPR11 (11 to 8) IPR11 (7 to 4) 0 to 15 (0) 0 to 15 (0) IPR10 (3 to 0) 0 to 15 (0) IPR10 (7 to 4) Interrupt Source MTU2 MTU3 TGI3A TGI3B TGI3C TGI3D TCI3V MTU4 TGI4A TGI4B TGI4C TGI4D TCI4V MTU5 TGI5U TGI5V Vector 180 181 182 183 184 188 189 190 191 192 196 197 IPR Setting Unit Internal Priority 1 2 3 4 Default Priority High IPR11 (15 to 12) 1 2 3 4 1 2 3 1 2 Low TGI5W 198 POE2 OEI1 OEI2 200 201 Rev. 3.00 Jun. 18, 2008 Page 135 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'00000330 to H'00000333 H'00000334 to H'00000337 H'00000338 to H'0000033B H'0000033C to H'0000033F H'00000340 to H'00000343 H'00000350 to H'00000353 H'00000354 to H'00000357 H'00000358 to H'0000035B H'0000035C to H'0000035F H'00000360 to H'00000363 H'00000370 to H'00000373 H'00000374 to H'00000377 H'00000378 to H'0000037B H'00000380 to H'00000383 0 to 15 (0) IPR13 (11 to 8) 0 to 15 (0) 0 to 15 (0) IPR12 (3 to 0) 0 to 15 (0) 0 to 15 (0) IPR12 (11 to 8) IPR12 (7 to 4) 0 to 15 (0) Interrupt Source MTU2S MTU3S TGI3A TGI3B TGI3C TGI3D TCI3V MTU4S TGI4A TGI4B TGI4C TGI4D TCI4V MTU5S TGI5U TGI5V TGI5W POE2 OEI3 Vector 204 205 206 207 208 212 213 214 215 216 220 221 222 224 IPR Setting Unit Internal Priority Default Priority High IPR12 (15 to 12) 1 2 3 4 1 2 3 4 IPR13 (15 to 12) 1 2 3 Low Rev. 3.00 Jun. 18, 2008 Page 136 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'00000390 to H'00000393 H'00000394 to H'00000397 H'00000398 to H'0000039B H'0000039C to H'0000039F H'000003A0 to H'000003A3 H'000003C0 to H'000003C3 H'000003C4 to H'000003C7 H'000003C8 to H'000003CB H'000003CC to H'000003CF H'000003D0 to H'000003D3 H'000003D4 to H'000003D7 H'000003D8 to H'000003DB H'000003DC to H'000003DF H'000003E0 to H'000003E3 H'000003E4 to H'000003E7 H'000003E8 to H'000003EB H'000003EC to H'000003EF 0 to 15 (0) IPR14 (7 to 4) 0 to 15 (0) IPR14 (11 to 8) 0 to 15 (0) 0 to 15 (0) IPR13 (7 to 4) Interrupt Source IIC3 STPI NAKI RXI TXI TEI SCIF SCIF0 BRI0 ERI0 RXI0 TXI0 SCIF1 BRI1 ERI1 RXI1 TXI1 SCIF2 BRI2 ERI2 RXI2 TXI2 Vector 228 229 230 231 232 240 241 242 243 244 245 246 247 248 249 250 251 IPR Setting Unit Internal Priority 1 2 3 4 5 Default Priority High IPR14 (15 to 12) 1 2 3 4 1 2 3 4 1 2 3 4 Low Rev. 3.00 Jun. 18, 2008 Page 137 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'000003F0 to H'000003F3 H'000003F4 to H'000003F7 H'000003F8 to H'000003FB H'000003FC to H'000003FF 0 to 15 (0) IPR14 (3 to 0) Interrupt Source SCIF SCIF3 BRI3 ERI3 RXI3 TXI3 Vector 252 253 254 255 IPR Setting Unit Internal Priority 1 2 3 4 Default Priority High Low Rev. 3.00 Jun. 18, 2008 Page 138 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.6 5.6.1 Operation Interrupt Operation Sequence The sequence of interrupt operations is described below. Figure 5.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers 01, 02, and 05 to 14 (IPR01, IPR02, and IPR05 to IPR14). Lower priority interrupts are ignored*. If two of these interrupts have the same priority level or if multiple interrupts occur within a single IPR, the interrupt with the highest priority is selected, according to the default priority and IPR setting unit internal priority shown in table 5.4. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling (figure 5.4). 6. The interrupt exception service routine start address is fetched from the exception handling vector table corresponding to the accepted interrupt. 7. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt is copied to bits I3 to I0 in SR. 8. The program counter (PC) is saved onto the stack. 9. The CPU jumps to the fetched interrupt exception service routine start address and starts executing the program. The jump that occurs is not a delayed branch. 10. A high level is output from the IRQOUT pin. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just being accepted, the IRQOUT pin holds low level. Rev. 3.00 Jun. 18, 2008 Page 139 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 5.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-sensing are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ interrupt request register (IRQRR). For details, see section 5.4.4, IRQ Interrupts. Interrupts held pending due to edge-sensing are cleared by a power-on reset. Rev. 3.00 Jun. 18, 2008 Page 140 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Program execution state Interrupt? No Yes No NMI? Yes User break? No Yes H-UDI interrupt? No No No No Yes Level 15 interrupt? Yes Yes I3 to I0 level 14? Level 14 interrupt? Yes I3 to I0 level 13? Level 1 interrupt? No Yes Yes I3 to I0 = level 0? No IRQOUT = low Read exception handling vector table Save SR to stack Copy accept-interrupt level to I3 to I0 Save PC to stack Branch to interrupt exception service routine IRQOUT = high No Figure 5.2 Interrupt Operation Flow Rev. 3.00 Jun. 18, 2008 Page 141 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.6.2 Stack after Interrupt Exception Handling Figure 5.3 shows the stack after interrupt exception handling. Address 4n - 8 4n - 4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. 2. PC: Start address of the next instruction (return destination instruction) after the executed instruction Always make sure that SP is a multiple of 4. Figure 5.3 Stack after Interrupt Exception Handling Rev. 3.00 Jun. 18, 2008 Page 142 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.7 Interrupt Response Time Table 5.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the exception service routine begins. The interrupt processing operations differ in the cases when banking is disabled, when banking is enabled without register bank overflow, and when banking is enabled with register bank overflow. Figures 5.4 and 5.5 show examples of pipeline operation when banking is disabled. Figures 5.6 and 5.7 show examples of pipeline operation when banking is enabled without register bank overflow. Figures 5.8 and 5.9 show examples of pipeline operation when banking is enabled with register bank overflow. Table 5.5 Interrupt Response Time Number of States Peripheral Item Time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU Time from input of interrupt request signal to CPU until sequence currently being executed is completed, interrupt exception handling starts, and first instruction in interrupt exception service routine is fetched No register banking Min. Max. NMI 2 Icyc + 2 Bcyc + 1 Pcyc User Break 3 Icyc H-UDI 2 Icyc + 1 Pcyc IRQ, PINT 2 Icyc + 3 Bcyc + 1 Pcyc Module 2 Icyc + 1 Bcyc + 1 Pcyc Remarks 3 Icyc + m1 + m2 4 Icyc + 2(m1 + m2) + m3 Min. is when the interrupt wait time is zero. Max. is when a higherpriority interrupt request has occurred during interrupt exception handling. 3 Icyc + m1 + m2 12 Icyc + m1 + m2 Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Register banking without register bank overflow Register banking with register bank overflow Min. Max. Min. Max. 3 Icyc + m1 + m2 3 Icyc + m1 + m2 + 19(m4) Rev. 3.00 Jun. 18, 2008 Page 143 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Number of States Peripheral Module 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 6 Icyc + 1 Bcyc + 1 Pcyc + 2(m1 + m2) + m3 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 14 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 200-MHz operation*1*2: Item Interrupt response time No register banking Min. NMI 5 Icyc + 2 Bcyc + 1 Pcyc + m1 + m2 Max. 6 Icyc + 2 Bcyc + 1 Pcyc + 2(m1 + m2) + m3 Register banking without register bank overflow Min. User Break 6 Icyc + m1 + m2 H-UDI 5 Icyc + 1 Pcyc + m1 + m2 IRQ, PINT 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 6 Icyc + 3 Bcyc + 1 Pcyc + 2(m1 + m2) + m3 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 14 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + Remarks 200-MHz operation*1*2: 0.040 to 0.110 s 7 Icyc + 2(m1 + m2) + m3 6 Icyc + 1 Pcyc + 2(m1 + m2) + m3 200-MHz operation*1*2: 0.060 to 0.130 s 5 Icyc + 1 Pcyc + m1 + m2 200-MHz operation*1*2: 0.040 to 0.110 s Max. 14 Icyc + 1 Pcyc + m1 + m2 200-MHz operation*1*2: 0.085 to 0.155 s Register banking with register bank overflow Min. 5 Icyc + 1 Pcyc + m1 + m2 200-MHz operation*1*2: 0.040 to 0.110 s Max. 5 Icyc + 1 Pcyc + m1 + 3 Bcyc + 1 Bcyc + 0.135 to 0.205 s m2 + 19(m4) 1 Pcyc + m1 + 1 Pcyc + m1 + m2 + 19(m4) m2 + 19(m4) Notes: m1 to m4 are the number of states needed for the following memory accesses. m1: Vector address read (longword read) m2: SR save (longword write) m3: PC save (longword write) m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. 1. In the case that m1 = m2 = m3 = m4 = 1 Icyc. 2. In the case that (I, B, P) = (200 MHz, 66 MHz, 33 MHz). Rev. 3.00 Jun. 18, 2008 Page 144 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3 Instruction (instruction replacing interrupt exception handling) F D E E M M M First instruction in interrupt exception service routine F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Instruction fetch. Instruction is fetched from memory in which program is stored. F: Instruction decoding. Fetched instruction is decoded. D: Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding. E: Memory access. Memory data access is performed. M: Figure 5.4 Example of Pipeline Operation when IRQ Interrupt is Accepted (No Register Banking) Rev. 3.00 Jun. 18, 2008 Page 145 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc + m1 1 Icyc + m1 + 2(m2) + m3 IRQ m1 F First instruction in interrupt exception service routine First instruction in multiple interrupt exception service routine m2 M m3 M m1 m2 D E E M F D D E E M M M F D Interrupt acceptance [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Multiple interrupt acceptance Figure 5.5 Example of Pipeline Operation for Multiple Interrupts (No Register Banking) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3 Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E M M M E F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 5.6 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking without Register Bank Overflow) Rev. 3.00 Jun. 18, 2008 Page 146 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 9 Icyc 3 Icyc + m1 + m2 RESBANK instruction F D E E E E E E E E E m1 m2 M m3 M E Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine D E E M F D [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance Figure 5.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking without Register Bank Overflow) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine 3 Icyc m1 m2 m3 F D E E M M M ... M F ... ... D [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 5.8 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking with Register Bank Overflow) Rev. 3.00 Jun. 18, 2008 Page 147 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 2 Icyc + 17(m4) 1 Icyc + m1 + m2 + 2(m4) m4 m4 m1 W m2 m3 RESBANK instruction F D E M M M ... M M M Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine D E E M M M ... F ... D Interrupt acceptance [Legend] m1: m2: m3: m4: Vector address read Saving of SR (stack) Saving of PC (stack) Restoration of banked registers Figure 5.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking with Register Bank Overflow) Rev. 3.00 Jun. 18, 2008 Page 148 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.8 Register Banks This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 5.10 shows the register bank configuration. Registers General registers R0 R1 : : R14 R15 Control registers SR GBR VBR TBR MACH MACL PR PC Interrupt generated (save) Register banks R0 R1 : : R14 GBR MACH MACL PR Bank 0 Bank 1 .... Bank 14 System registers RESBANK instruction (restore) VTO Bank control registers (interrupt controller) Bank control register Bank number register IBCR IBNR Note: VTO: : Banked register Vector table address offset Figure 5.10 Overview of Register Bank Configuration Rev. 3.00 Jun. 18, 2008 Page 149 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.8.1 (1) Banked Register and Input/Output of Banks Banked Register The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table address offset are banked. (2) Input/Output of Banks This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in lastout (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes place in the reverse order, beginning from the last bank saved to. 5.8.2 (1) Bank Save and Restore Operations Saving to Bank Figure 5.11 shows register bank save operations. The following operations are performed when an interrupt for which usage of register banks is allowed is accepted by the CPU: a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the interrupt is generated. b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN, bank i. c. The BN value is incremented by 1. Register banks +1 (c) BN (a) Registers Bank 0 Bank 1 : : Bank i Bank i + 1 : : Bank 14 R0 to R14 (b) GBR MACH MACL PR VTO Figure 5.11 Bank Save Operations Rev. 3.00 Jun. 18, 2008 Page 150 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) Figure 5.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the interrupt exception service routine. 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3 Instruction (instruction replacing interrupt exception handling) F D E E M M M E (1) VTO, PR, GBR, MACL (2) R12, R13, R14, MACH (3) R8, R9, R10, R11 Saved to bank Overrun fetch First instruction in interrupt exception service routine (4) R4, R5, R6, R7 (5) R0, R1, R2, R3 F F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 5.12 Bank Save Timing (2) Restoration from Bank The RESBANK (restore from register bank) instruction is used to restore data saved in a register bank. After restoring data from the register banks with the RESBANK instruction at the end of the interrupt exception service routine, execute the RTE instruction to return from interrupt exception service routine. Rev. 3.00 Jun. 18, 2008 Page 151 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.8.3 Save and Restore Operations after Saving to All Banks If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to all register banks, automatic saving to the stack is performed instead of register bank saving if the BOVE bit in the bank number register (IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception occurs and data is not saved to the stack. Save and restore operations when using the stack are as follows: (1) Saving to Stack 1. The status register (SR) and program counter (PC) are saved to the stack during interrupt exception handling. 2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14, R13, ..., R1, and R0. 3. The register bank overflow bit (BO) in SR is set to 1. 4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. (2) Restoration from Stack When the RESBANK (restore from register bank) instruction is executed with the register bank overflow bit (BO) in SR set to 1, the CPU operates as follows: 1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. The registers are restored from the stack in the order of R0, R1, ..., R13, R14, PR, GBR, MACH, and MACL. 2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. Rev. 3.00 Jun. 18, 2008 Page 152 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.8.4 Register Bank Exception There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow This exception occurs if, after data has been saved to all of the register banks, an interrupt for which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number register (IBNR) remains set to the bank count of 15 and saving is not performed to the register bank. (2) Register Bank Underflow This exception occurs if the RESBANK (restore from register bank) instruction is executed when no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH, MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number register (IBNR) remains set to 0. 5.8.5 Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. When this happens, the CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a register bank overflow, and the start address of the executed RESBANK instruction for a register bank underflow. To prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. Program execution starts from the exception service routine start address. Rev. 3.00 Jun. 18, 2008 Page 153 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.9 Data Transfer with Interrupt Request Signals Interrupt request signals can be used to activate the DMAC and transfer data. Interrupt sources that are designated to activate the DMAC are masked without being input to the INTC. The mask condition is as follows: Mask condition = DME * (DE0 * interrupt source select 0 + DE1 * interrupt source select 1 + DE2 * interrupt source select 2 + DE3 * interrupt source select 3 + DE4 * interrupt source select 4 + DE5 * interrupt source select 5 + DE6 * interrupt source select 6 + DE7 * interrupt source select 7) Figure 5.13 shows a block diagram of interrupt control. Here, DME is bit 0 in DMAOR of the DMAC, and DEn (n = 0 to 7) is bit 0 in CHCR0 to CHCR7 of the DMAC. For details, see section 9, Direct Memory Access Controller (DMAC). Interrupt source DMAC Interrupt source flag clearing (by DMAC) Interrupt source (not specified as DMAC activating source) CPU interrupt request INTC CPU Figure 5.13 Interrupt Control Block Diagram Rev. 3.00 Jun. 18, 2008 Page 154 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC Activating 1 Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC. 2. When interrupts occur, interrupt requests are sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt exception service routine. 5.9.2 Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU Interrupt 1. Select DMAC activating sources and set both the DE and DME bits to 1. This masks CPU interrupt sources regardless of the interrupt priority register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears the interrupt sources when starting transfer. Rev. 3.00 Jun. 18, 2008 Page 155 of 1160 REJ09B0191-0300 Section 5 Interrupt Controller (INTC) 5.10 5.10.1 Usage Note Timing to Clear an Interrupt Source The interrupt source flags should be cleared in the interrupt exception service routine. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 5.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. 5.10.2 Timing of IRQOUT Negation Once the interrupt controller has accepted an interrupt request, the low level is output from the IRQOUT pin until the CPU jumps to the first address of the interrupt exception service routine, after which the high level is output from the IRQOUT pin. If, however, the interrupt controller has accepted an interrupt request and the low level is being output from the IRQOUT pin, but the interrupt request is canceled before the CPU has jumped to the first address of the interrupt exception service routine, the low level continues to be output from the IRQOUT pin until the CPU has jumped to the first address of the interrupt exception service routine for the next interrupt request. Rev. 3.00 Jun. 18, 2008 Page 156 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) Section 6 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Instruction fetch or data read/write (bus master (CPU or DMAC) selection in the case of data read/write), data size, data contents, address value, and stop timing in the case of instruction fetch are break conditions that can be set in the UBC. Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus is performed by issuing bus cycles on the memory access bus (M bus). The UBC monitors the C bus and internal bus (I bus). 6.1 Features 1. The following break comparison conditions can be set. Number of break channels: two channels (channels 0 and 1) User break can be requested as the independent condition on channels 0 and 1. * Address Comparison of the 32-bit address is maskable in 1-bit units. One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus (IAB)) can be selected. * Data Comparison of the 32-bit data is maskable in 1-bit units. One of the two data buses (M data bus (MDB) and I data bus (IDB)) can be selected. * Bus master when I bus is selected Selection of CPU cycles or DMAC cycles * Bus cycle Instruction fetch (only when C bus is selected) or data access * Read/write * Operand size Byte, word, and longword 2. In an instruction fetch cycle, it can be selected whether the start of user break interrupt exception processing is set before or after an instruction is executed. 3. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin. Rev. 3.00 Jun. 18, 2008 Page 157 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) Figure 6.1 shows a block diagram of the UBC. I bus Access control IDB IAB C bus MDB MAB FAB Access comparator BBR_0 BAR_0 Address comparator BAMR_0 I bus Data comparator BDR_0 BDMR_0 Channel 0 Access comparator BBR_1 BAR_1 Address comparator BAMR_1 Data comparator BDR_1 BDMR_1 Channel 1 BRCR Control User break interrupt request UBCTRG pin output [Legend] BBR: Break bus cycle register BAR: Break address register BAMR: Break address mask register BDR: Break data register BDMR: Break data mask registe BRCR: Break control register Figure 6.1 Block Diagram of UBC Rev. 3.00 Jun. 18, 2008 Page 158 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.2 Input/Output Pin Table 6.1 shows the pin configuration of the UBC. Table 6.1 Pin Name UBC trigger Pin Configuration Symbol UBCTRG I/O Output Function Indicates that a setting condition is satisfied on either channel 0 or 1 of the UBC. Rev. 3.00 Jun. 18, 2008 Page 159 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.3 Register Descriptions The UBC has the following registers. Five control registers for each channel and one common control register for channel 0 and channel 1 are available. A register for each channel is described as BAR_0 for the BAR register in channel 0. Table 6.2 Channel 0 Register Configuration Register Name Break address register_0 Break address mask register_0 Break bus cycle register_0 Break data register_0 Break data mask register_0 Abbreviation BAR_0 BAMR_0 BBR_0 BDR_0 BDMR_0 BAR_1 BAMR_1 BBR_1 BDR_1 BDMR_1 BRCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 Address H'FFFC0400 H'FFFC0404 Access Size 32 32 H'FFFC04A0 16 H'FFFC0408 32 H'FFFC040C 32 H'FFFC0410 H'FFFC0414 32 32 1 Break address register_1 Break address mask register_1 Break bus cycle register_1 Break data register_1 Break data mask register_1 H'FFFC04B0 16 H'FFFC0418 32 H'FFFC041C 32 H'FFFC04C0 32 Common Break control register Rev. 3.00 Jun. 18, 2008 Page 160 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.3.1 Break Address Register (BAR) BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in each channel. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the three address buses for a break condition. BAR is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. Bit: 31 BA31 30 BA30 29 BA29 28 BA28 27 BA27 26 BA26 25 BA25 24 BA24 23 BA23 22 BA22 21 BA21 20 BA20 19 BA19 18 BA18 17 BA17 16 BA16 Initial value: R/W: Bit: Initial value: R/W: 0 R/W 15 BA15 0 R/W 14 BA14 0 R/W 13 BA13 0 R/W 12 BA12 0 R/W 11 BA11 0 R/W 10 BA10 0 R/W 9 BA9 0 R/W 8 BA8 0 R/W 7 BA7 0 R/W 6 BA6 0 R/W 5 BA5 0 R/W 4 BA4 0 R/W 3 BA3 0 R/W 2 BA2 0 R/W 1 BA1 0 R/W 0 BA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name Initial Value R/W R/W Description Break Address Store an address on the CPU address bus (FAB or MAB) or IAB specifying break conditions. When the C bus and instruction fetch cycle are selected by BBR, specify an FAB address in bits BA31 to BA0. When the C bus and data access cycle are selected by BBR, specify an MAB address in bits BA31 to BA0. BA31 to BA0 All 0 Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0. Rev. 3.00 Jun. 18, 2008 Page 161 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.3.2 Break Address Mask Register (BAMR) BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address bits specified by BAR. BAMR is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 Initial value: R/W: Bit: Initial value: R/W: 0 R/W 15 0 R/W 0 R/W 14 0 R/W 0 R/W 13 0 R/W 0 R/W 12 0 R/W 0 R/W 11 0 R/W 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R/W 8 0 R/W 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 0 R/W 0 R/W 0 0 R/W BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 Bit 31 to 0 Bit Name BAM31 to BAM0 Initial Value All 0 R/W R/W Description Break Address Mask Specify bits masked in the break address bits specified by BAR (BA31 to BA0). 0: Break address bit BAn is included in the break condition 1: Break address bit BAn is masked and not included in the break condition Note: n = 31 to 0 Rev. 3.00 Jun. 18, 2008 Page 162 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.3.3 Break Data Register (BDR) BDR is a 32-bit readable/writable register. The control bits CD[1:0]in the break bus cycle register (BBR) select one of the two data buses for a break condition. BDR is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. Bit: 31 BD31 30 BD30 29 BD29 28 BD28 27 BD27 26 BD26 25 BD25 24 BD24 23 BD23 22 BD22 21 BD21 20 BD20 19 BD19 18 BD18 17 BD17 16 BD16 Initial value: R/W: Bit: Initial value: R/W: 0 R/W 15 BD15 0 R/W 14 BD14 0 R/W 13 BD13 0 R/W 12 BD12 0 R/W 11 BD11 0 R/W 10 BD10 0 R/W 9 BD9 0 R/W 8 BD8 0 R/W 7 BD7 0 R/W 6 BD6 0 R/W 5 BD5 0 R/W 4 BD4 0 R/W 3 BD3 0 R/W 2 BD2 0 R/W 1 BD1 0 R/W 0 BD0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name Initial Value R/W R/W Description Break Data Bits Store data which specifies a break condition. If the I bus is selected in BBR, specify the break data on IDB in bits BD31 to BD0. If the C bus is selected in BBR, specify the break data on MDB is set in bits BD31 to BD0. BD31 to BD0 All 0 Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0. Rev. 3.00 Jun. 18, 2008 Page 163 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.3.4 Break Data Mask Register (BDMR) BDMR is a 32-bit readable/writable register. BDMR specifies bits masked in the break data bits specified by BDR. BDMR is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16 Initial value: R/W: Bit: Initial value: R/W: 0 R/W 15 0 R/W 0 R/W 14 0 R/W 0 R/W 13 0 R/W 0 R/W 12 0 R/W 0 R/W 11 0 R/W 0 R/W 10 0 R/W 0 R/W 9 0 R/W 0 R/W 8 0 R/W 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 0 R/W 0 R/W 0 0 R/W BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0 Bit 31 to 0 Bit Name BDM31 to BDM0 Initial Value All 0 R/W R/W Description Break Data Mask Specify bits masked in the break data bits specified by BDR (BD31 to BD0). 0: Break data bit BDn is included in the break condition 1: Break data bit BDn is masked and not included in the break condition Note: n = 31 to 0 Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDMR as the break mask data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0. Rev. 3.00 Jun. 18, 2008 Page 164 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.3.5 Break Bus Cycle Register (BBR) BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupt requests, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions. BBR is initialized to H'0000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. Bit: 15 - 14 - 13 UBID 12 DBE 11 - 10 - 9 8 7 6 5 ID[1:0] 4 3 2 1 0 SZ[1:0] CP[1:0] CD[1:0] RW[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 UBID 0 R/W User Break Interrupt Disable Disables or enables user break interrupt requests when a break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled 12 DBE 0 R/W Data Break Enable Selects whether the data bus condition is included in the break conditions. 0: Data bus condition is not included in break conditions 1: Data bus condition is included in break conditions 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 CP[1:0] 00 R/W I-Bus Bus Master Select Select the bus master when the bus cycle of the break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). x1: CPU cycle is included in break conditions 1x: DMAC cycle is included in break conditions Rev. 3.00 Jun. 18, 2008 Page 165 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) Bit 7, 6 Bit Name CD[1:0] Initial Value 00 R/W R/W Description C Bus Cycle/I Bus Cycle Select Select the C bus cycle or I bus cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle 5, 4 ID[1:0] 00 R/W Instruction Fetch/Data Access Select Select the instruction fetch cycle or data access cycle as the bus cycle of the break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle 3, 2 RW[1:0] 00 R/W Read/Write Select Select the read cycle or write cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle 1, 0 SZ[1:0] 00 R/W Operand Size Select Select the operand size of the bus cycle for the break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access [Legend] x: Don't care Rev. 3.00 Jun. 18, 2008 Page 166 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.3.6 Break Control Register (BRCR) BRCR sets the following conditions: 1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle is set before or after instruction execution. 2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied. BRCR is a 32-bit readable/writable register that has break condition match flags and bits for setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid (previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or in software standby mode or sleep mode. Bit: 31 Initial value: R/W: Bit: Initial value: R/W: 0 R 15 0 R/W 30 0 R 14 0 R/W 29 0 R 13 0 R/W 28 0 R 12 0 R/W 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R/W 21 0 R 5 0 R/W 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 16 CKS[1:0] 0 R/W 1 0 R 0 R/W 0 0 R SCMFC SCMFC SCMFD SCMFD 0 1 0 1 PCB1 PCB0 Bit 31 to 18 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 17, 16 CKS[1:0] 00 R/W Clock Select Specifies the pulse width output to the UBCTRG pin when a break condition is satisfied. 00: Pulse width of UBCTRG is one bus clock cycle 01: Pulse width of UBCTRG is two bus clock cycles 10: Pulse width of UBCTRG is four bus clock cycles 11: Pulse width of UBCTRG is eight bus clock cycles Rev. 3.00 Jun. 18, 2008 Page 167 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) Bit 15 Bit Name SCMFC0 Initial Value 0 R/W R/W Description C Bus Cycle Condition Match Flag 0 When the C bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 0 does not match 1: The C bus cycle condition for channel 0 matches 14 SCMFC1 0 R/W C Bus Cycle Condition Match Flag 1 When the C bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 1 does not match 1: The C bus cycle condition for channel 1 matches 13 SCMFD0 0 R/W I Bus Cycle Condition Match Flag 0 When the I bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 0 does not match 1: The I bus cycle condition for channel 0 matches 12 SCMFD1 0 R/W I Bus Cycle Condition Match Flag 1 When the I bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 1 does not match 1: The I bus cycle condition for channel 1 matches 11 to 7 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 PCB1 0 R/W PC Break Select 1 Selects the break timing of the instruction fetch cycle for channel 1 as before or after instruction execution. 0: PC break of channel 1 is generated before instruction execution 1: PC break of channel 1 is generated after instruction execution Rev. 3.00 Jun. 18, 2008 Page 168 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) Bit 5 Bit Name PCB0 Initial Value 0 R/W R/W Description PC Break Select 0 Selects the break timing of the instruction fetch cycle for channel 0 as before or after instruction execution. 0: PC break of channel 0 is generated before instruction execution 1: PC break of channel 0 is generated after instruction execution 4 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 169 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.4 6.4.1 Operation Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception handling is described below: 1. The break address is set in a break address register (BAR). The masked address bits are set in a break address mask register (BAMR). The break data is set in the break data register (BDR). The masked data bits are set in the break data mask register (BDMR). The bus break conditions are set in the break bus cycle register (BBR). Three control bit groups of BBR (C bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set to 00. The relevant break control conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBR, and branch after reading from the last written register. The newly written register values become valid from the instruction at the branch destination. 2. In the case where the break conditions are satisfied and the user break interrupt request is enabled, the UBC sends a user break interrupt request to the INTC, sets the C bus condition match flag (SCMFC) or I bus condition match flag (SCMFD) for the appropriate channel, and outputs a pulse to the UBCTRG pin with the width set by the CKS[1:0] bits. Setting the UBID bit in BBR to 1 enables external monitoring of the trigger output without requesting user break interrupts. 3. On receiving a user break interrupt request signal, the INTC determines its priority. Since the user break interrupt has a priority level of 15, it is accepted when the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are checked, and condition match flags are set if the conditions match. For details on ascertaining the priority, see section 5, Interrupt Controller (INTC). 4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been satisfied. Clear the condition match flags during the user break interrupt exception processing routine. The interrupt occurs again if this operation is not performed. 5. There is a chance that the break set in channel 0 and the break set in channel 1 occur around the same time. In this case, there will be only one user break request to the INTC, but these two break channel match flags may both be set. 6. When selecting the I bus as the break condition, note as follows: Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC monitors bus cycles generated by the bus master specified by BBR, and determines the condition match. Rev. 3.00 Jun. 18, 2008 Page 170 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) Whether or not an access issued on the C bus by the CPU is issued on the I bus depends on the cache settings. Regarding the I bus operation under cache conditions, see table 7.8 in section 7, Cache. When a break condition is specified for the I bus, only the data access cycle is monitored. The instruction fetch cycle (including the cache renewal cycle) is not monitored. The DMAC only issues data access cycles for I bus cycles. If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the user break interrupt request is to be accepted cannot be clearly defined. Rev. 3.00 Jun. 18, 2008 Page 171 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.4.2 Break on Instruction Fetch Cycle 1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBR), the break condition is the FAB bus instruction fetch cycle. Whether a start of user break interrupt exception processing is set before or after the execution of the instruction can then be selected with the PCB0 or PCB1 bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear BA0 bit in the break address register (BAR) to 0. A break cannot be generated as long as this bit is set to 1. 2. A break for instruction fetch which is set as a break before instruction execution occurs when it is confirmed that the instruction has been fetched and will be executed. This means a break does not occur for instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the user break interrupt request is not received until the execution of the first instruction at the branch destination. Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When setting a break condition for break after instruction execution, the instruction set with the break condition is executed and then the break is generated prior to execution of the next instruction. As with pre-execution breaks, a break does not occur with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, the user break interrupt request is not received until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated. Rev. 3.00 Jun. 18, 2008 Page 172 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.4.3 Break on Data Access Cycle 1. If the C bus is specified as a break condition for data access break, condition comparison is performed for the addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles that are issued by the bus master specified by the bits to select the bus master of the I bus, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 6. in section 6.4.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 6.3. Table 6.3 Access Size Longword Word Byte Data Access Cycle Addresses and Operand Size Comparison Conditions Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BAR), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size in the break bus cycle register (BBR). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in the four bytes at bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 of the break data register (BDR) and break data mask register (BDMR). To specify word data for this case, set the same data in the two words at bits 31 to 16 and 15 to 0. 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5. If the data access cycle is selected, the instruction at which the break will occur cannot be determined. Rev. 3.00 Jun. 18, 2008 Page 173 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.4.4 Value of Saved Program Counter When a user break interrupt request is received, the address of the instruction from where execution is to be resumed is saved to the stack, and the exception handling state is entered. If the C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access cycle is specified as a break condition, the instruction at which the break should occur cannot be uniquely determined. 1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved to the stack. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved to the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition: The address after executing several instructions of the instruction that matched the break condition is saved to the stack. Rev. 3.00 Jun. 18, 2008 Page 174 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.4.5 (1) Usage Examples Break Condition Specified for C Bus Instruction Fetch Cycle (Example 1-1) * Register specifications BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 Rev. 3.00 Jun. 18, 2008 Page 175 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) (Example 1-3) * Register specifications BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_0 = H'0054, BAR_1= H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 (Example 2-1) * Register specifications BAR_0 = H'00123456, BAMR_0 = H'00000000, BBR_0 = H'0064, BAR_1= H'000ABCDE, BAMR_1 = H'000000FF, BBR_1 = H'106A, BDR_1 = H'A512A512, BDMR_1 = H'00000000, BRCR = H'00000000 Rev. 3.00 Jun. 18, 2008 Page 176 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) (3) Break Condition Specified for I Bus Data Access Cycle (Example 3-1) * Register specifications BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0094, BAR_1= H'00055555, BAMR_1 = H'00000000, BBR_1 = H'12A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F, BRCR = H'00000000 Rev. 3.00 Jun. 18, 2008 Page 177 of 1160 REJ09B0191-0300 Section 6 User Break Controller (UBC) 6.5 Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. The UBC cannot monitor access to the C bus and I bus cycles in the same channel. 3. When a user break interrupt request and another exception source occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 4.1 in section 4, Exception Handling. If an exception source with higher priority occurs, the user break interrupt request is not received. 4. Note the following when a break occurs in a delay slot. If a pre-execution break is set at a delay slot instruction, the user break interrupt request is not received immediately before execution of the branch destination. 5. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. 6. Do not set an address within an interrupt exception handling routine whose interrupt priority level is at least 15 (including user break interrupts) as a break address. 7. Do not set break after instruction execution for the SLEEP instruction or for the delayed branch instruction where the SLEEP instruction is placed at its delay slot. 8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are placed. If the address of the lower 16 bits is set and a break before instruction execution is set as a break condition, the break is handled as a break after instruction execution. 9. Do not set a user break before instruction execution for the instruction following the DIVU or DIVS instruction. If a user break before instruction execution is set for the instruction following the DIVU or DIVS instruction and an exception or interrupt occurs during execution of the DIVU or DIVS instruction, a user break occurs before instruction execution even though execution of the DIVU or DIVS instruction is halted. 10. Do not set a user break both before instruction execution and after instruction execution for instruction of the same address. If, for example, a user break before instruction execution on channel 0 and a user break after instruction on channel 1 are set at the instruction of the same address, the condition match flag for the channel 1 is set even though a user break on channel 0 occurs before instruction execution. Rev. 3.00 Jun. 18, 2008 Page 178 of 1160 REJ09B0191-0300 Section 7 Cache Section 7 Cache 7.1 Features * Capacity Instruction cache: 8 Kbytes Operand cache: 8 Kbytes * Structure: Instructions/data separated, 4-way set associative * Way lock function (only for operand cache): Way 2 and way 3 are lockable * Line size: 16 bytes * Number of entries: 128 entries/way * Write system: Write-back/write-through selectable * Replacement method: Least-recently-used (LRU) algorithm 7.1.1 Cache Structure The cache separates data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 128 entries per way. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 2 Kbytes (16 bytes x 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure 7.1 shows the operand cache structure. The instruction cache structure is the same as the operand cache structure except for not having the U bit. Rev. 3.00 Jun. 18, 2008 Page 179 of 1160 REJ09B0191-0300 Section 7 Cache Address array (ways 0 to 3) Data array (ways 0 to 3) LRU Entry 0 Entry 1 . . . . . . V U Tag address 0 1 . . . . . . LW0 LW1 LW2 LW3 0 1 . . . . . . Entry 127 23 (1 + 1 + 21) bits 127 128 (32 x 4) bits LW0 to LW3: Longword data 0 to 3 127 6 bits Figure 7.1 Operand Cache Structure (1) Address Array The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit (only for operand cache) indicates whether the entry has been written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical address used in the external memory access. It consists of 21 bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses of the cache-enabled space are H'00000000 to H'1FFFFFFF (see section 8, Bus State Controller (BSC)), and therefore the upper three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in software standby mode. The tag address is not initialized by a power-on reset or manual reset or in software standby mode. (2) Data Array Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on reset or manual reset or in software standby mode. Rev. 3.00 Jun. 18, 2008 Page 180 of 1160 REJ09B0191-0300 Section 7 Cache (3) LRU With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way that has been least recently accessed. Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between LRU and way replacement is shown in table 7.1 when the cache lock function (only for operand cache) is not used (concerning the case where the cache lock function is used, see section 7.2.2, Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 7.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 7.1. The LRU bits are initialized to B'000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Table 7.1 LRU and Way Replacement (Cache Lock Function Not Used) Way to be Replaced 3 2 1 0 LRU (Bits 5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 Rev. 3.00 Jun. 18, 2008 Page 181 of 1160 REJ09B0191-0300 Section 7 Cache 7.2 Register Descriptions The cache has the following registers. Table 7.2 Register Configuration Abbreviation CCR1 CCR2 R/W R/W R/W Initial Value H'00000000 H'00000000 Address H'FFFC1000 H'FFFC1004 Access Size 32 32 Register Name Cache control register 1 Cache control register 2 7.2.1 Cache Control Register 1 (CCR1) The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or write-back mode for operand cache. Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR1. CCR1 is initialized to H'00000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 ICF 10 - 9 - 8 ICE 7 - 6 - 5 - 4 - 3 OCF 2 - 1 WT 0 OCE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 182 of 1160 REJ09B0191-0300 Section 7 Cache Bit 31 to 12 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Flush Writing 1 flushes all instruction cache entries (clears the V and LRU bits of all instruction cache entries to 0). Always reads 0. Write-back to external memory is not performed when the instruction cache is flushed. Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Enable Indicates whether the instruction cache function is enabled/disabled. 0: Instruction cache disable 1: Instruction cache enable 11 ICF 0 R/W 10, 9 All 0 R 8 ICE 0 R/W 7 to 4 All 0 R 3 OCF 0 R/W 2 0 R 1 WT 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Operand Cache Flush Writing 1 flushes all operand cache entries (clears the V, U, and LRU bits of all operand cache entries to 0). Always reads 0. Write-back to external memory is not performed when the operand cache is flushed. Reserved This bit is always read as 0. The write value should always be 0. Write Through Selects write-back mode or write-through mode. 0: Write-back mode 1: Write-through mode 0 OCE 0 R/W Operand Cache Enable Indicates whether the operand cache function is enabled/disabled. 0: Operand cache disable 1: Operand cache enable Rev. 3.00 Jun. 18, 2008 Page 183 of 1160 REJ09B0191-0300 Section 7 Cache 7.2.2 Cache Control Register 2 (CCR2) CCR2 is used to enable or disable the cache locking function for operand cache and is valid in cache locking mode only. In cache locking mode, the lock enable bit (the LE bit) in CCR2 is set to 1. In non-cache-locking mode, the cache locking function is invalid. When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF @Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The relationship between the setting of each bit and a way, to be replaced when the prefetch instruction is executed, are listed in table 7.3. On the other hand, when the prefetch instruction is executed and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1 specified in cache locking mode while one-line data already exists in way 0 which is specified by Rn, a cache hit occurs and data is not fetched to way 3. In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in CCR2 and ways to be replaced are listed in table 7.4. Programs that change the contents of CCR2 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR2. CCR2 is initialized to H'00000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 LE Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 0 W3 W3 LOAD* LOCK W2 W2 LOAD* LOCK Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Rev. 3.00 Jun. 18, 2008 Page 184 of 1160 REJ09B0191-0300 Section 7 Cache Bit 31 to 17 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 16 LE 0 R/W Lock Enable Controls the cache locking function. 0: Not cache locking mode 1: Cache locking mode 15 to 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 8 W3LOAD* W3LOCK 0 0 R/W R/W Way 3 Load Way 3 Lock When a cache miss occurs by the prefetch instruction while W3LOAD = 1 and W3LOCK = 1 in cache locking mode, the data is always loaded into way 3. Under any other condition, the cache miss data is loaded into the way to which LRU points. 7 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 W2LOAD* W2LOCK 0 0 R/W R/W Way 2 Load Way 2 Lock When a cache miss occurs by the prefetch instruction while W2LOAD = 1 and W2LOCK =1 in cache locking mode, the data is always loaded into way 2. Under any other condition, the cache miss data is loaded into the way to which LRU points. Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Rev. 3.00 Jun. 18, 2008 Page 185 of 1160 REJ09B0191-0300 Section 7 Cache Table 7.3 LE 0 1 1 1 1 1 1 Way to be Replaced when a Cache Miss Occurs in PREF Instruction W3LOAD* x x x 0 0 0 1 W3LOCK x 0 0 1 1 x 1 W2LOAD* x x 0 x 0 1 0 W2LOCK x 0 1 0 1 1 x Way to be Replaced Decided by LRU (table 7.1) Decided by LRU (table 7.1) Decided by LRU (table 7.5) Decided by LRU (table 7.6) Decided by LRU (table 7.7) Way 2 Way 3 [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 7.4 LE 0 1 1 1 1 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction W3LOAD* x x x x x W3LOCK x 0 0 1 1 W2LOAD* x x x x x W2LOCK x 0 1 0 1 Way to be Replaced Decided by LRU (table 7.1) Decided by LRU (table 7.1) Decided by LRU (table 7.5) Decided by LRU (table 7.6) Decided by LRU (table 7.7) [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 7.5 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0) Way to be Replaced 3 1 0 LRU (Bits 5 to 0) 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 3.00 Jun. 18, 2008 Page 186 of 1160 REJ09B0191-0300 Section 7 Cache Table 7.6 LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1) Way to be Replaced 2 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Table 7.7 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) Way to be Replaced 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 3.00 Jun. 18, 2008 Page 187 of 1160 REJ09B0191-0300 Section 7 Cache 7.3 Operation Operations for the operand cache are described here. Operations for the instruction cache are similar to those for the operand cache except for the address array not having the U bit, and there being no prefetch operation or write operation, or a write-back buffer. 7.3.1 Searching Cache If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is accessed, the cache will be searched to see if the desired data is in the cache. Figure 7.2 illustrates the method by which the cache is searched. Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits 31 to 11 of the address used to access memory are compared with the read tag address. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 7.2 shows a hit on way 1. Rev. 3.00 Jun. 18, 2008 Page 188 of 1160 REJ09B0191-0300 Section 7 Cache Access address 31 11 10 4 3 210 Entry selection Address array (ways 0 to 3) Longword (LW) selection Data array (ways 0 to 3) Entry 0 Entry 1 V U Tag address Entry 0 Entry 1 LW0 LW1 LW2 LW3 . . . . . . . . . Entry 127 . . . . . . . . . Entry 127 CMP0 CMP1 CMP2 CMP3 Hit signal (way 1) [Legend] CMP0 to CMP3: Comparison circuits 0 to 3 Figure 7.2 Cache Search Scheme Rev. 3.00 Jun. 18, 2008 Page 189 of 1160 REJ09B0191-0300 Section 7 Cache 7.3.2 (1) Read Access Read Hit In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. (2) Read Miss An external bus cycle starts and the entry is updated. The way replaced follows table 7.4. Entries are updated in 16-byte units. When the desired data that caused the miss is loaded from external memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. The update of cache and write-back to memory are performed in wrap around method. For example, the lower four bits of the address at which a read miss occurs indicate H'4, the update of cache and write-back to memory are performed in the order of H'4, H'8, H'C, H'0, which are the lower four bits of the address. 7.3.3 (1) Prefetch Operation (Only for Operand Cache) Prefetch Hit LRU is updated so that the hit way becomes the latest. The contents in other caches are not modified. No data is transferred to the CPU. (2) Prefetch Miss No data is transferred to the CPU. The way to be replaced follows table 7.3. Other operations are the same in case of read miss. Rev. 3.00 Jun. 18, 2008 Page 190 of 1160 REJ09B0191-0300 Section 7 Cache 7.3.4 (1) Write Operation (Only for Operand Cache) Write Hit In a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit way becomes the latest. In write-through mode, the data is written to the cache and an external memory write cycle is issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way becomes the latest. (2) Write Miss In write-back mode, an external bus cycle starts when a write miss occurs, and the entry is updated. The way to be replaced follows table 7.4. When the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way becomes the latest. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. The update of cache and write-back to memory are performed in wrap around method. For example, the lower four bits of the address at which a write miss occurs indicate H'4, the update of cache and write-back to memory are performed in the order of H'4, H'8, H'C, H'0, which are the lower four bits of the address. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 7.3.5 Write-Back Buffer (Only for Operand Cache) When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the cache completes to fetch the new entry, the write-back buffer writes the entry back to external memory. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 7.3 shows the configuration of the write-back buffer. Rev. 3.00 Jun. 18, 2008 Page 191 of 1160 REJ09B0191-0300 Section 7 Cache A (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 A (31 to 4): Physical address written to external memory (upper three bits are 0) Longword 0 to 3: One line of cache data to be written to external memory Figure 7.3 Write-Back Buffer Configuration Operations in sections 7.3.2 to 7.3.5 are compiled in table 7.8. Table 7.8 Cache Operations Write-Back Mode/ Hit/ Cache Instruction cache CPU Cycle Instruction fetch Miss Cache renewal cycle is generated Operand cache Prefetch/ read Miss Hit Either mode is available Write-through mode Write-back mode 0 Cache renewal cycle is generated Cache renewal cycle is generated 1 Cache renewal cycle is generated. Succeedingly write-back cycle in write-back buffer is generated. Renewed to new values by cache renewal cycle Renewed to new values by cache renewal cycle Renewed to new values by cache renewal cycle x Not generated Renewed to new values by cache renewal cycle Not renewed Miss Hit Write-Through Mode U Bit External Memory Accession (through Internal Bus) Not generated Cache Contents Not renewed Rev. 3.00 Jun. 18, 2008 Page 192 of 1160 REJ09B0191-0300 Section 7 Cache Write-Back Mode/ Hit/ Cache Operand cache CPU Cycle Write Miss Hit Write-Through Mode Write-through mode Write-back mode x U Bit External Memory Accession (through Internal Bus) Write cycle CPU issues is generated. Not generated Cache Contents Renewed to new values by write cycle the CPU issues Renewed to new values by write cycle the CPU issues Miss Write-through mode Write-back mode Write cycle CPU issues is generated. Not renewed* 0 Cache renewal cycle is generated Renewed to new values by cache renewal cycle. Subsequently renewed again to new values in write cycle CPU issues. 1 Cache renewal cycle is generated. Succeedingly buffer is generated. Renewed to new values by cache renewal cycle. new values in write cycle CPU issues. write-back cycle in write-back Subsequently renewed again to [Legend] x: Don't care. Notes: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte write access * Neither LRU renewed. LRU is renewed in all other cases. 7.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is mapped in the cache-enabled space, operate the memorymapped cache to invalidate and write back as required. Rev. 3.00 Jun. 18, 2008 Page 193 of 1160 REJ09B0191-0300 Section 7 Cache 7.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 7.4.1 Address Array To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. In the address field, specify the entry address selecting the entry, The W bit for selecting the way, and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is fixed at longword, specify B'00 for bits 1 and 0 of the address. The tag address, LRU bits, U bit (only for operand cache), and V bit are specified as data. Always specify 0 for the upper three bits (bits 31 to 29) of the tag address. For the address and data formats, see figure 7.4. The following three operations are possible for the address array. (1) Address Array Read The tag address, LRU bits, U bit (only for operand cache), and V bit are read from the entry address specified by the address and the entry corresponding to the way. For the read operation, associative operation is not performed regardless of whether the associative bit (A bit) specified by the address is 1 or 0. (2) Address-Array Write (Non-Associative Operation) When the associative bit (A bit) in the address field is cleared to 0, write the tag address, LRU bits, U bit (only for operand cache), and V bit, specified by the data field, to the entry address specified by the address and the entry corresponding to the way. When writing to a cache line for which the U bit = 1 and the V bit =1 in the operand cache address array, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. The write-back to Rev. 3.00 Jun. 18, 2008 Page 194 of 1160 REJ09B0191-0300 Section 7 Cache memory is performed in the order of H'0, H'4, H'8, H'C, which are the lower four bits of the address. (3) Address-Array Write (Associative Operation) When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four ways for the entry specified by the address field are compared with the tag address that is specified by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When there is no way that has a hit, nothing is written and there is no operation. This function is used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1 in the operand cache, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. The write-back to memory is performed in the order of H'0, H'4, H'8, H'C, which are the lower four bits of the address. 7.4.2 Data Array To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. Specify the entry address for selecting the entry, the L bit indicating the longword position within the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword, specify B'00 for bits 1 and 0 of the address. For the address and data formats, see figure 7.4. The following two operations are possible for the data array. Information in the address array is not modified by this operation. (1) Data Array Read The data specified by the L bit in the address is read from the entry address specified by the address and the entry corresponding to the way. (2) Data Array Write The longword data specified by the data is written to the position specified by the L bit in the address from the entry address specified by the address and the entry corresponding to the way. Rev. 3.00 Jun. 18, 2008 Page 195 of 1160 REJ09B0191-0300 Section 7 Cache 1. Instruction cache 1.1 Address array access (a) Address specification Read access 31 23 22 2. Operand cache 2.1 Address array access (a) Address specification Read access 13 12 11 10 4 3 0 2 * 1 0 0 0 31 23 22 13 12 11 10 4 3 0 2 * 1 0 0 0 111100000 *----------* W Entry address 111100001 *----------* W Entry address Write access 31 23 22 Write access 13 12 11 10 4 3 A 2 * 1 0 0 0 31 23 22 13 12 11 10 4 3 A 2 * 1 0 0 0 111100000 *----------* W Entry address 111100001 *----------* W Entry address (b) Data specification (both read and write accesses) 31 29 28 11 10 9 4 3 2 1 0 (b) Data specification (both read and write accesses) 31 29 28 11 10 9 4 3 2 1 0 0 0 0 Tag address (28 to 11) E LRU X X X V 0 0 0 Tag address (28 to 11) E LRU X X U V 1.2 Data array access (both read and write accesses) (a) Address specification 31 23 22 13 12 11 10 4 3 L 2.2 Data array access (both read and write accesses) (a) Address specification 2 1 0 0 0 31 23 22 13 12 11 10 4 3 L 2 1 0 0 0 111100010 *----------* W Entry address 111100011 *----------* W Entry address (b) Data specification 31 Longword data (b) Data specification 0 31 0 Longword data [Legend] *: Don't care E: Bit 10 of entry address for read, don't care for write X: 0 for read, don't care for write Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access Rev. 3.00 Jun. 18, 2008 Page 196 of 1160 REJ09B0191-0300 Section 7 Cache 7.4.3 (1) Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found. If no match is found, there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. An example when a write data is specified in R0 and an address is specified in R1 is shown below. ; R0=H'0110 0010; tag address(28-11)=B'0 0001 0001 0000 0000 0, U=0, V=0 ; R1=H'F080 0088; operand cache address array access, entry=B'000 1000, A=1 ; MOV.L R0,@R1 (2) Reading the Data of a Specific Entry The data section of a specific cache entry can be read by the memory mapping cache access. The longword indicated in the data field of the data array in figure 7.4 is read into the register. An example when an address is specified in R0 and data is read in R1 is shown below. ; R0=H'F100 004C; instruction cache data array access, entry=B'000 0100, ; Way=0, longword address=3 ; MOV.L @R0,R1 Rev. 3.00 Jun. 18, 2008 Page 197 of 1160 REJ09B0191-0300 Section 7 Cache 7.4.4 Notes 1. Programs that access memory-mapped cache of the operand cache should be placed in a cachedisabled space. Programs that access memory-mapped cache of the instruction cache should be placed in a cache-disabled space, and in each of the beginning and the end of that, two or more read accesses to on-chip peripheral modules or external address space (cache-disabled address) should be executed. 2. Rewriting the address array contents so that two or more ways are hit simultaneously is prohibited. Operation is not guaranteed if the address array contents are changed so that two or more ways are hit simultaneously. 3. Memory-mapped cache can be accessed only by the CPU and not by the DMAC. Registers can be accessed by the CPU and the DMAC. Rev. 3.00 Jun. 18, 2008 Page 198 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Section 8 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 8.1 Features 1. External address space A maximum of 64 Mbytes for each of areas CS0 to CS8. Can specify the normal space interface, SRAM interface with byte selection, burst ROM (clocked synchronous or asynchronous), MPX-I/O, burst MPX-I/O, SDRAM, and PCMCIA interface for each address space. Can select the data bus width (8, 16, or 32 bits) for each address space. Controls insertion of wait cycles for each address space. Controls insertion of wait cycles for each read access and write access. Can set independent idle cycles during the continuous access for five cases: read-write (in same space/different spaces), read-read (in same space/different spaces), the first cycle is a write access. 2. Normal space interface Supports the interface that can directly connect to the SRAM. 3. Burst ROM interface (clocked asynchronous) High-speed access to the ROM that has the page mode function. 4. MPX-I/O interface Can directly connect to a peripheral LSI that needs an address/data multiplexing. 5. SDRAM interface Can set the SDRAM in up to two areas. Multiplex output for row address/column address. Efficient access by single read/single write. High-speed access in bank-active mode. Supports an auto-refresh and self-refresh. Supports low-frequency and power-down modes. Issues MRS and EMRS commands. Rev. 3.00 Jun. 18, 2008 Page 199 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 6. PCMCIA direct interface Supports the IC memory card and I/O card interface defined in JEIDA specifications Ver. 4.2 (PCMCIA2.1 Rev. 2.1). Wait-cycle insertion controllable by program. 7. SRAM interface with byte selection Can connect directly to a SRAM with byte selection. 8. Burst MPX-I/O interface Can connect directly to a peripheral LSI that needs an address/data multiplexing. Supports burst transfer. 9. Burst ROM interface (clocked synchronous) Can connect directly to a ROM of the clocked synchronous type. 10. Bus arbitration Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 11. Refresh function Supports the auto-refresh and self-refresh functions. Specifies the refresh interval using the refresh counter and clock selection. Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 12. Usage as interval timer for refresh counter Generates an interrupt request at compare match. Rev. 3.00 Jun. 18, 2008 Page 200 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Figure 8.1 shows a block diagram of the BSC. BREQ BACK Bus mastership controller CMNCR CS0WCR WAIT Wait controller CS8WCR MD2, MD0 CS8BCR A25 to A0, D31 to D0 BS, RD/WR, RD, WE3 to WE0, RASU, RASL, CASU, CASL CKE, DQMxx, AH, FRAME, CE2A, CE2B Memory controller SDCR RTCSR RTCNT Comparator RTCOR BSC REFOUT Refresh controller [Legend] CMNCR: Common control register CSnWCR: CSn space wait control register (n = 0 to 8) CSnBCR: CSn space bus control register (n = 0 to 8) SDRAM control register SDCR: RTCSR: Refresh timer control/status register RTCNT: Refresh timer counter RTCOR: Refresh time constant register Figure 8.1 Block Diagram of BSC Rev. 3.00 Jun. 18, 2008 Page 201 of 1160 REJ09B0191-0300 Module bus CS0 to CS8 Area controller CS0BCR Internal bus ... ... ... ... ... Section 8 Bus State Controller (BSC) 8.2 Input/Output Pins Table 8.1 shows the pin configuration of the BSC. Table 8.1 Name A25 to A0 D31 to D0 BS CS0 to CS4, CS7, CS8 CS5/CE1A, CS6/CE1B CE2A, CE2B RD/WR Pin Configuration I/O Function Output Address bus I/O Data bus Output Bus cycle start Output Chip select Output Chip select Function as PCMCIA card select signals for D7 to D0 when PCMCIA is used. Output Function as PCMCIA card select signals for D15 to D8. Output Read/write Connects to WE pins when SDRAM or SRAM with byte selection is connected. RD Output Read pulse signal (read data output enable signal) Functions as a strobe signal for indicating memory read cycles when PCMCIA is used. WE3/DQMUU/ ICIOWR/AH Output Indicates that D31 to D24 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D31 to D24 when SDRAM is connected. Functions as a strobe signal for indicating I/O write cycles when PCMCIA is used. Functions as the address hold signal when the MPX-I/O is used. WE2/DQMUL/ ICIORD Output Indicates that D23 to D16 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D23 to D16 when SDRAM is connected. Functions as a strobe signal for indicating I/O read cycles when PCMCIA is used. Rev. 3.00 Jun. 18, 2008 Page 202 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Name WE1/DQMLU/WE I/O Function Output Indicates that D15 to D8 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D15 to D8 when SDRAM is connected. Functions as a strobe signal for indicating memory write cycles when PCMCIA is used. WE0/DQMLL Output Indicates that D7 to D0 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D7 to D0 when SDRAM is connected. RASU, RASL CASU, CASL CKE FRAME WAIT BREQ BACK REFOUT MD2, MD0 Output Connects to RAS pin when SDRAM is connected. Output Connects to CAS pin when SDRAM is connected. Output Connects to CKE pin when SDRAM is connected. Output Functions as FRAME signal when connected to burst MPX-I/O interface Input Input External wait input Bus request input Output Bus enable output Output Refresh request output in bus-released state Input Select bus width of area 0 and initial bus width of areas 1 to 8. Rev. 3.00 Jun. 18, 2008 Page 203 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.3 8.3.1 Area Overview Address Map In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled, cachedisabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved areas) according to the upper bits of the address. External address spaces CS0 to CS7 are cache-enabled when internal address A29 = 0 or cachedisabled when A29 = 1. The CS8 space is always cache-disabled. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 8.2 Address Map Space Memory to be Connected CS0 CS1 Normal space, burst ROM (asynchronous or synchronous) Normal space, SRAM with byte selection Normal space, SRAM with byte selection, SDRAM Normal space, SRAM with byte selection, SDRAM Normal space, SRAM with byte selection, burst ROM (asynchronous) Normal space, SRAM with byte selection, MPXI/O, PCMCIA Normal space, SRAM with byte selection, burst MPX-I/O, PCMCIA Normal space, SRAM with byte selection Normal space, burst ROM (asynchronous or synchronous) Normal space, SRAM with byte selection Normal space, SRAM with byte selection, SDRAM Normal space, SRAM with byte selection, SDRAM Normal space, SRAM with byte selection, burst ROM (asynchronous) Normal space, SRAM with byte selection, MPXI/O, PCMCIA Normal space, SRAM with byte selection, burst MPX-I/O, PCMCIA Normal space, SRAM with byte selection Cache-disabled Cache Cache-enabled Internal Address H'00000000 to H'03FFFFFF H'04000000 to H'07FFFFFF H'08000000 to H'0BFFFFFF CS2 H'0C000000 to H'0FFFFFFF CS3 H'10000000 to H'13FFFFFF H'14000000 to H'17FFFFFF CS4 CS5 H'18000000 to H'1BFFFFFF CS6 H'1C000000 to H'1FFFFFFF CS7 H'20000000 to H'23FFFFFF H'24000000 to H'27FFFFFF CS0 CS1 H'28000000 to H'2BFFFFFF CS2 H'2C000000 to H'2FFFFFFF CS3 H'30000000 to H'33FFFFFF H'34000000 to H'37FFFFFF CS4 CS5 H'38000000 to H'3BFFFFFF CS6 H'3C000000 to H'3FFFFFFF CS7 Rev. 3.00 Jun. 18, 2008 Page 204 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Internal Address H'40000000 to H'7FFFFFFF Space Memory to be Connected CS8 Normal space, SRAM with byte selection On-chip RAM, reserved area* On-chip peripheral modules, reserved area* Cache Cache-disabled H'80000000 to H'FFFBFFFF Other H'FFFC0000 to H'FFFFFFFF Other Note: * For the on-chip RAM space, access the addresses shown in section 21, On-Chip RAM. For the on-chip peripheral module space, access the addresses shown in section 24, List of Registers. Do not access addresses which are not described in these sections. Otherwise, the correct operation cannot be guaranteed. 8.3.2 Data Bus Width and Pin Function Setting in Each Area In this LSI, the data bus width of area 0 and the initial data bus width of areas 1 to 8 can be set to 8, 16, or 32 bits through external pins during a power-on reset. The bus width of area 0 cannot be modified after a power-on reset. The initial data bus width of areas 1 to 8 is set to the same size as that of area 0, but can be modified through register settings during program execution. Note that the selectable data bus widths may be limited depending on the connected memory type. After a power-on reset, the LSI starts execution of the program stored in the external memory allocated in area 0. Since ROM is assumed as the external memory in area 0, minimum pin functions such as the address bus, data bus, CS0, and RD are available. The sample access waveforms shown in this section include other pins such as BS, RD/WR, and WEn, which are available after they are selected through the pin function controller. Before pin function settings are completed by a program, only read access to area 0 is allowed; do not perform any other access. The A1 and A0 pin settings are also necessary to modify the bus width of an area other than area 0 into 8 or 16 bits after the LSI is started with a 32-bit data bus. For details on pin function settings, see section 19, Pin Function Controller (PFC). Table 8.3 MD2 1 Correspondence between External Pins (MD2 and MD0) and Data Bus Width MD0 1 0 Data Bus Width 32 bits 16 bits 8 bits Reserved (setting prohibited) 0 1 0 Rev. 3.00 Jun. 18, 2008 Page 205 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4 Register Descriptions The BSC has the following registers. Do not access spaces other than area 0 until settings of the connected memory interface are completed. Table 8.4 Register Configuration Abbreviation CMNCR CS0BCR CS1BCR CS2BCR CS3BCR CS4BCR CS5BCR CS6BCR CS7BCR CS8BCR CS0WCR CS1WCR CS2WCR CS3WCR CS4WCR CS5WCR CS6WCR CS7WCR CS8WCR SDCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00001010 H'36DB0600 H'36DB0600 H'36DB0600 H'36DB0600 H'36DB0600 H'36DB0600 H'36DB0600 H'36DB0600 H'36DB0600 H'00000500 H'00000500 H'00000500 H'00000500 H'00000500 H'00000500 H'00000500 H'00000500 H'00000500 H'00000000 H'00000000 H'00000000 H'00000000 Address H'FFFC0000 H'FFFC0004 H'FFFC0008 H'FFFC000C H'FFFC0010 H'FFFC0014 H'FFFC0018 H'FFFC001C H'FFFC0020 H'FFFC0024 H'FFFC0028 H'FFFC002C H'FFFC0030 H'FFFC0034 H'FFFC0038 H'FFFC003C H'FFFC0040 H'FFFC0044 H'FFFC0048 H'FFFC004C H'FFFC0050 H'FFFC0054 H'FFFC0058 Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Register Name Common control register CS0 space bus control register CS1 space bus control register CS2 space bus control register CS3 space bus control register CS4 space bus control register CS5 space bus control register CS6 space bus control register CS7 space bus control register CS8 space bus control register CS0 space wait control register CS1 space wait control register CS2 space wait control register CS3 space wait control register CS4 space wait control register CS5 space wait control register CS6 space wait control register CS7 space wait control register CS8 space wait control register SDRAM control register Refresh timer control/status register RTCSR Refresh timer counter Refresh time constant register RTCNT RTCOR Rev. 3.00 Jun. 18, 2008 Page 206 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Register Name AC characteristics switching register AC characteristics switching key register Abbreviation ACSWR ACKYER R/W 1 Initial Value Address H'FFFC180C H'FFFC1BFC Access Size 32 8 R/W* H'00000000 W* 2 Notes: 1. To write to this register, a special sequence using key registers for switching the AC characteristics is required. 2. Write-only register. The write value is arbitrary. Rev. 3.00 Jun. 18, 2008 Page 207 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. This register is initialized to H'00001010 by a power-on reset and retains the value by a manual reset and in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 BLOCK 10 9 8 7 DMAIW[2:0] 6 5 DMA IWA 4 - 3 - 2 - 1 HIZ MEM 0 HIZ CNT DPRTY[1:0] Initial value: R/W: 0 R 0 R 0 R 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 1 R Reserved This bit is always read as 1. The write value should always be 1. 11 BLOCK 0 R/W Bus Lock Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ. 10, 9 DPRTY[1:0] 00 R/W DMA Burst Transfer Priority Specify the priority for a refresh request/bus mastership request during DMA burst transfer. 00: Accepts a refresh request and bus mastership request during DMA burst transfer. 01: Accepts a refresh request but does not accept a bus mastership request during DMA burst transfer. 10: Accepts neither a refresh request nor a bus mastership request during DMA burst transfer. 11: Reserved (setting prohibited) Rev. 3.00 Jun. 18, 2008 Page 208 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 8 to 6 Bit Name DMAIW[2:0] Initial Value 000 R/W R/W Description Wait states between access cycles when DMA single address transfer is performed. Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 5 DMAIWA 0 R/W Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. However, when the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles after an access to an external device with DACK, even when the continuous access cycles to an external device with DACK are performed. 0: Idle cycles inserted when another device drives the data bus after an external device with DACK drove it. 1: Idle cycles always inserted after an access to an external device with DACK 4 1 R Reserved This bit is always read as 1. The write value should always be 1. Rev. 3.00 Jun. 18, 2008 Page 209 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 3, 2 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 HIZMEM 0 R/W High-Z Memory Control Specifies the pin state in software standby mode for A25 to A0, BS, CSn, CS2x, RD/WR, WEn/DQMxx/AH, RD, and FRAME. At bus-released state, these pin are high-impedance states regardless of the setting value of the HIZMEM bit. 0: High impedance in software standby mode. 1: Driven in software standby mode 0 HIZCNT 0 R/W High-Z Control Specifies the state in software standby mode and busreleased state for CKIO, CKE, RASU, RASL, CASU, and CASL. 0: High impedance in software standby mode and busreleased state for CKIO, CKE, RASU, RASL, CASU, and CASL. 1: Driven in software standby mode and bus-released state for CKIO, CKE, RASU, RASL, CASU, and CASL. Rev. 3.00 Jun. 18, 2008 Page 210 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 8) CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number of idle cycles between bus cycles, and the bus width. This register is initialized to H'36DB0x00 by a power-on reset and retains the value by a manual reset and in software standby mode. Do not access external memory other than area 0 until CSnBCR initial setting is completed. Idle cycles may be inserted even when they are not specified. For details, see section 8.5.12, Wait between Access Cycles. Bit: 31 - 30 29 IWW[2:0] 28 27 26 IWRWD[2:0] 25 24 23 IWRWS[2:0] 22 21 20 IWRRD[2:0] 19 18 17 IWRRS[2:0] 16 Initial value: R/W: Bit: 0 R 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 15 - 14 13 TYPE[2:0] 12 11 - 10 9 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - BSZ[1:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R 1* R/W 1* R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: * CSnBCR samples the external pins (MD2 and MD0) that specify the bus width at power-on reset. Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Idle Cycles between Write-Read Cycles and WriteWrite Cycles These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and write-write cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 30 to 28 IWW[2:0] 011 R/W Rev. 3.00 Jun. 18, 2008 Page 211 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 27 to 25 Bit Name Initial Value R/W R/W Description Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous access cycles switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted IWRWD[2:0] 011 24 to 22 IWRWS[2:0] 011 R/W Idle Cycles for Read-Write in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Rev. 3.00 Jun. 18, 2008 Page 212 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 21 to 19 Bit Name IWRRD[2:0] Initial Value 011 R/W R/W Description Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles switch between different space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 18 to 16 IWRRS[2:0] 011 R/W Idle Cycles for Read-Read in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 15 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 213 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 14 to 12 Bit Name TYPE[2:0] Initial Value 000 R/W R/W Description Specify the type of memory connected to a space. 000: Normal space 001: Burst ROM (clocked asynchronous) 010: MPX-I/O 011: SRAM with byte selection 100: SDRAM 101: PCMCIA 110: Burst MPX-I/O 111: Burst ROM (clocked synchronous) For details for memory type in each area, see table 8.2. Note: When connecting the burst ROM to the CS0 space, change the CS0WCR register to the settings by the burst ROM CS0WCR uses and then set TYPE[2:0] to the burst ROM setting. 11 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 214 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 10, 9 Bit Name BSZ[1:0] Initial Value 11* R/W R/W Description Data Bus Width Specification Specify the data bus widths of spaces. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size For MPX-I/O, selects bus width by address Notes: 1. If area 5 is specified as MPX-I/O, the bus width can be specified as 8 bits or 16 bits by the address according to the SZSEL bit in CS5WCR by specifying the BSZ[1:0] bits to 11. The fixed bus width can be specified as 8 bits or 16 bits 2. The initial data bus width for areas 0 to 8 is specified by external pins. The BSZ[1:0] bits settings in CS0BCR are ignored but the bus width settings in CS1BCR to CS8BCR can be modified. 3. If area 6 is specified as burst MPX-I/O space, the bus width can be specified as 32 bits only. 4. If area 5 or area 6 is specified as PCMCIA space, the bus width can be specified as either 8 bits or 16 bits. 5. If area 2 or area 3 is specified as SDRAM space, the bus width can be specified as either 16 bits or 32 bits. 6. If area 0 is specified as clocked synchronous burst ROM space, the bus width can be specified as either 16 bits or 32 bits. 8 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * CSnBCR samples the external pins (MD2 and MD0) that specify the bus width at power-on reset. Rev. 3.00 Jun. 18, 2008 Page 215 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 8) CSnWCR specifies various wait cycles for memory access. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. CSnWCR is initialized to H'00000500 by a power-on reset and retains the value by a manual reset and in software standby mode. (1) Normal Space, SRAM with Byte Selection, MPX-I/O * CS0WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 * All 0 R/W Reserved Clear these bits to 0 when the interface for normal space is used. 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 * All 0 R/W Reserved Clear these bits to 0 when the interface for normal space is used. 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 216 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 12, 11 Bit Name SW[1:0] Initial Value 00 R/W R/W Description Number of Delay Cycles from Address, CS0 Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CS0 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored Rev. 3.00 Jun. 18, 2008 Page 217 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 5 to 2 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS0 Negation Specify the number of delay cycles from RD and WEn negation to address and CS0 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Note: * To connect the burst ROM to the CS0 space and switch to burst ROM interface after activation, set the TYPE[2:0] bits in CS0BCR after setting the burst number by the bits 20 and 21 and the burst wait cycle number by the bits 16 and 17. Do not write 1 to the reserved bits other than above bits. Rev. 3.00 Jun. 18, 2008 Page 218 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * CS1WCR, CS7WCR, CS8WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 BAS 19 - 18 17 WW[2:0] 16 Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles Rev. 3.00 Jun. 18, 2008 Page 219 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored Rev. 3.00 Jun. 18, 2008 Page 220 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 5 to 2 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 3.00 Jun. 18, 2008 Page 221 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * CS2WCR, CS3WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 BAS 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 - 0 - WR[3:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 222 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 10 to 7 Bit Name WR[3:0] Initial Value 1010 R/W R/W Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 223 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * CS4WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 BAS 19 - 18 17 WW[2:0] 16 Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles Rev. 3.00 Jun. 18, 2008 Page 224 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 3.00 Jun. 18, 2008 Page 225 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 6 Bit Name WM Initial Value 0 R/W R/W Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 3.00 Jun. 18, 2008 Page 226 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * CS5WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 SZSEL 20 MPXW/ BAS 19 - 18 17 WW[2:0] 16 Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21 SZSEL 0 R/W MPX-I/O Interface Bus Width Specification Specifies an address to select the bus width when the BSZ[1:0] of CS5BCR are specified as 11. This bit is valid only when area 5 is specified as MPX-I/O. 0: Selects the bus width by address A14 1: Selects the bus width by address A21 The relationship between the SZSEL bit and bus width selected by A14 or A21 are summarized below. SZSEL 0 0 1 1 A14 0 1 Not affected Not affected A21 Not affected Not affected 0 1 Bus Width 8 bits 16 bits 8 bits 16 bits Rev. 3.00 Jun. 18, 2008 Page 227 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 20 Bit Name MPXW Initial Value 0 R/W R/W Description MPX-I/O Interface Address Wait This bit setting is valid only when area 5 is specified as MPX-I/O. Specifies the address cycle insertion wait for MPX-I/O interface. 0: Inserts no wait cycle 1: Inserts 1 wait cycle BAS 0 R/W SRAM with Byte Selection Byte Access Select This bit setting is valid only when area 5 is specified as SRAM with byte selection. Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 228 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 12, 11 Bit Name SW[1:0] Initial Value 00 R/W R/W Description Number of Delay Cycles from Address, CS5 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS5 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 229 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 1, 0 Bit Name HW[1:0] Initial Value 00 R/W R/W Description Delay Cycles from RD, WEn Negation to Address, CS5 Negation Specify the number of delay cycles from RD and WEn negation to address and CS5 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 3.00 Jun. 18, 2008 Page 230 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * CS6WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 BAS 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS6 Assertion to RD, WEn Assertion Specify the number of delay cycles from address, CS6 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 3.00 Jun. 18, 2008 Page 231 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 10 to 7 Bit Name WR[3:0] Initial Value 1010 R/W R/W Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WN 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification of this bit is valid even when the number of access wait cycles is 0. 0: The external wait input is valid 1: The external wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Number of Delay Cycles from RD, WEn Negation to Address, CS6 Negation Specify the number of delay cycles from RD, WEn negation to address, and CS6 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 3.00 Jun. 18, 2008 Page 232 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (2) Burst ROM (Clocked Asynchronous) * CS0WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 20 19 - 18 - 17 16 BST[1:0] BW[1:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 9 W[3:0] 8 7 6 WM 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 BST[1:0] 00 R/W Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11. Bus Width 8 bits BST[1:0] 00 01 16 bits 00 01 10 32 bits xx Burst count 16 burst x one time 4 burst x four times 8 burst x one time 2 burst x four times 4-4 or 2-4-2 burst 4 burst x one time 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 233 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 17, 16 Bit Name BW[1:0] Initial Value 00 R/W R/W Description Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 3.00 Jun. 18, 2008 Page 234 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 6 Bit Name WM Initial Value 0 R/W R/W Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 235 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * CS4WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 20 19 - 18 - 17 16 BST[1:0] BW[1:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 W[3:0] 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 BST[1:0] 00 R/W Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11. Bus Width 8 bits BST[1:0] 00 01 16 bits 00 01 10 32 bits xx Burst count 16 burst x one time 4 burst x four times 8 burst x one time 2 burst x four times 4-4 or 2-4-2 burst 4 burst x one time 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 3.00 Jun. 18, 2008 Page 236 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 3.00 Jun. 18, 2008 Page 237 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 6 Bit Name WM Initial Value 0 R/W R/W Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 3.00 Jun. 18, 2008 Page 238 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (3) SDRAM* * CS2WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 7 6 - 5 - 4 - 3 - 2 - 1 - 0 - A2CL[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 R 0 R 1 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 11 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 1 R Reserved This bit is always read as 1. The write value should always be 1. 9 0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A2CL[1:0] 10 R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection. Rev. 3.00 Jun. 18, 2008 Page 239 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * CS3WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 13 12 - 11 10 9 - 8 7 6 - 5 - 4 3 2 - 1 0 WTRP[1:0]* WTRCD[1:0]* A3CL[1:0] TRWL[1:0]* WTRC[1:0]* Initial value: R/W: 0 R 0 R/W 0 R/W 0 R 0 R/W 1 R/W 0 R 1 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. Bit 31 to 15 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 14, 13 WTRP[1:0]* 00 R/W Number of Auto-Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles as shown below. * * * * * From the start of auto-precharge and issuing of ACTV command for the same bank From issuing of the PRE/PALL command to issuing of the ACTV command for the same bank Till entering the power-down mode or deep powerdown mode From the issuing of PALL command to issuing REF command in auto refresh mode From the issuing of PALL command to issuing SELF command in self refresh mode The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 3.00 Jun. 18, 2008 Page 240 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 12 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 11, 10 WTRCD[1:0]* 01 R/W Number of Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9 0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A3CL[1:0] 10 R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 241 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 4, 3 Bit Name TRWL[1:0]* Initial Value 00 R/W R/W Description Number of Auto-Precharge Startup Wait Cycles Specify the number of minimum auto-precharge startup wait cycles as shown below. * Cycle number from the issuance of the WRITA command by this LSI until the completion of autoprecharge in the SDRAM. Equivalent to the cycle number from the issuance of the WRITA command until the issuance of the ACTV command. Confirm that how many cycles are required between the WRITE command receive in the SDRAM and the auto-precharge activation, referring to each SDRAM data sheet. And set the cycle number so as not to exceed the cycle number specified by this bit. Cycle number from the issuance of the WRITA command until the issuance of the PRE command. This is the case when accessing another low address in the same bank in bank active mode. * The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 2 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 242 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 1, 0 Bit Name Initial Value R/W R/W Description Number of Idle Cycles from REF Command/SelfRefresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles in the periods shown below. * * From the issuance of the REF command until the issuance of the ACTV/REF/MRS command From releasing self-refresh until the issuance of the ACTV/REF/MRS command. WTRC[1:0]* 00 The setting for areas 2 and 3 is common. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection. Rev. 3.00 Jun. 18, 2008 Page 243 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (4) PCMCIA * CS5WCR, CS6WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 20 19 - 18 - 17 - 16 - SA[1:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 15 - 14 13 12 11 10 9 8 7 6 WM 5 - 4 - 3 2 1 0 TED[3:0] PCW[3:0] TEH[3:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 SA[1:0] 00 R/W Space Attribute Specification Select memory card interface or I/O card interface when PCMCIA interface is selected. SA1: 0: Selects memory card interface for the space for A25 = 1. 1: Selects I/O card interface for the space for A25 = 1. SA0: 0: Selects memory card interface for the space for A25 = 0. 1: Selects I/O card interface for the space for A25 = 0. 19 to 15 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 244 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 14 to 11 Bit Name TED[3:0] Initial Value 0000 R/W R/W Description Number of Delay Cycles from Address Output to RD/WE Assertion Specify the number of delay cycles from address output to RD/WE assertion for the memory card or to ICIORD/ICIOWR assertion for the I/O card in PCMCIA interface. 0000: 0.5 cycles 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Rev. 3.00 Jun. 18, 2008 Page 245 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 10 to 7 Bit Name PCW[3:0] Initial Value 1010 R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid 1: External wait input is ignored 5, 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 246 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 3 to 0 Bit Name TEH[3:0] Initial Value 0000 R/W R/W Description Delay Cycles from RD/WE Negation to Address Specify the number of address hold cycles from RD/WE negation for the memory card or those from ICIORD/ICIOWR negation for the I/O card in PCMCIA interface. 0000: 0.5 cycles 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Rev. 3.00 Jun. 18, 2008 Page 247 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (5) Burst MPX-I/O * CS6WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 20 19 MPXMD 18 - 17 16 MPXAW[1:0] BW[1:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 9 W[3:0] 8 7 6 WM 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 22 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 MPXAW[1:0] 00 R/W Number of Address Cycle Waits Specify the number of waits to be inserted in the address cycle. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 3.00 Jun. 18, 2008 Page 248 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 19 Bit Name MPXMD Initial Value 0 R/W R/W Description Burst MPX-I/O Interface Mode Specification Specify the access mode in 16-byte access 0: One 4-burst access by 16-byte transfer 1: Two 2-burst access cycles by quadword (8-byte) transfer Transfer size when MPXMD = 0: D31 0 0 0 0 1 1 1 D30 0 0 1 1 0 0 1 D29 0 1 0 1 0 1 0 Transfer Size Byte (1 byte) Word (2 bytes) Longword (4 bytes) Reserved (quadword) (8 bytes) 16 bytes Reserved (32 bytes) Reserved (64 bytes) Transfer size when MPXMD = 1: D31 0 0 0 0 1 D30 0 0 1 1 0 D29 0 1 0 1 0 Transfer Size Byte (1 byte) Word (2 bytes) Longword (4 bytes) Quadword (8 bytes) Reserved (32 bytes) 18 0 R Reserved This bit is always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted at the second or subsequent access cycles in burst access 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 3.00 Jun. 18, 2008 Page 249 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 15 to 11 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 250 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (6) Burst ROM (Clocked Synchronous) * CS0WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 16 BW[1:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 9 W[3:0] 8 7 6 WM 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 18 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 251 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 10 to 7 Bit Name W[3:0] Initial Value 1010 R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 252 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. SDCR is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 19 18 - 17 16 A2ROW[1:0] A2COL[1:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 15 - 14 - 13 DEEP 12 SLOW 11 10 9 8 7 - 6 - 5 - 4 3 2 - 1 0 RFSH RMODEPDOWN BACTV A3ROW[1:0] A3COL[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W Bit 31 to 21 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20, 19 A2ROW[1:0] 00 R/W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 18 0 R Reserved This bit is always read as 0. The write value should always be 0. 17, 16 A2COL[1:0] 00 R/W Number of Bits of Column Address for Area 2 Specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) Rev. 3.00 Jun. 18, 2008 Page 253 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 DEEP 0 R/W Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the lowpower SDRAM enters the deep power-down mode. 0: Self-refresh mode 1: Deep power-down mode 12 SLOW 0 R/W Low-Frequency Mode Specifies the output timing of command, address, and write data for SDRAM and the latch timing of read data from SDRAM. Setting this bit makes the hold time for command, address, write and read data extended for half cycle (output or read at the falling edge of CKIO). This mode is suitable for SDRAM with low-frequency clock. 0: Command, address, and write data for SDRAM is output at the rising edge of CKIO. Read data from SDRAM is latched at the rising edge of CKIO. 1: Command, address, and write data for SDRAM is output at the falling edge of CKIO. Read data from SDRAM is latched at the falling edge of CKIO. Rev. 3.00 Jun. 18, 2008 Page 254 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 11 Bit Name RFSH Initial Value 0 R/W R/W Description Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh 10 RMODE 0 R/W Refresh Control Specifies whether to perform auto-refresh or selfrefresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed 9 PDOWN 0 R Power-Down Mode Specifies whether the SDRAM will enter the powerdown mode after the access to the SDRAM. With this bit being set to 1, after the SDRAM is accessed, the CKE signal is driven low and the SDRAM enters the power-down mode. 0: The SDRAM does not enter the power-down mode after being accessed. 1: The SDRAM enters the power-down mode after being accessed. Rev. 3.00 Jun. 18, 2008 Page 255 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 8 Bit Name BACTV Initial Value 0 R/W R/W Description Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: Bank active mode can be used only when either the upper or lower bits of the CS3 space are used. When both the CS2 and CS3 spaces are set to SDRAM, specify the autoprecharge mode. 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4, 3 A3ROW[1:0] 00 R/W Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 A3COL[1:0] 00 R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) Rev. 3.00 Jun. 18, 2008 Page 256 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. RTCSR is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is adjusted only by a power-on reset. Note that there is an error in the time until the compare match flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value other than B'000. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 CMF 6 CMIE 5 4 CKS[2:0] 3 2 1 RRC[2:0] 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 8 7 Bit Name CMF Initial Value All 0 0 R/W R R/W Description Reserved These bits are always read as 0. Compare Match Flag Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied. Rev. 3.00 Jun. 18, 2008 Page 257 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bit 6 Bit Name CMIE Initial Value 0 R/W R/W Description Compare Match Interrupt Enable Enables or disables CMF interrupt requests when the CMF bit in RTCSR is set to 1. 0: Disables CMF interrupt requests. 1: Enables CMF interrupt requests. 5 to 3 CKS[2:0] 000 R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: B/4 010: B/16 011: B/64 100: B/256 101: B/1024 110: B/2048 111: B/4096 2 to 0 RRC[2:0] 000 R/W Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: 1 time 001: 2 times 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) Rev. 3.00 Jun. 18, 2008 Page 258 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. This counter is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 8 7 to 0 Initial Bit Name Value All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. 8-Bit Counter Rev. 3.00 Jun. 18, 2008 Page 259 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.7 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. The REFOUT signal can be asserted when a refresh request is generated while the bus is released. For details, see section 8.5.6 (9), Relationship between Refresh Requests and Bus Cycles, and section 8.5.13, Bus Arbitration. When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects the interrupt request and does not clear the refresh request. Therefore, a combination of refresh request and interval timer interrupt can be specified so that the number of refresh requests are counted by using timer interrupts while refresh is performed periodically. When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. This register is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 8 7 to 0 Bit Name Initial Value All 0 All 0 R/W Description R Reserved These bits are always read as 0. R/W 8-Bit Counter Rev. 3.00 Jun. 18, 2008 Page 260 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.8 AC Characteristics Switching Register (ACSWR) To use the SDRAM in clock mode 2, set the AC characteristics switching register (ACSWR) and AC characteristics key switching register (ACKEYR). In clock mode 7, set nothing to keep the initial value. ACSWR is initialized to H'00000000 by a power-on reset, but not initialized and retains the value by a manual reset or in software standby mode. Only a special sequence can write to this register to prevent accidental erroneous write. The setting procedure is shown in section 8.4.10, Sequence to Write to ACSWR. Read is done by the normal longword. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 1 0 ACOSW[3:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 ACOSW[3:0] 0000 R/W AC Characteristics Switch Specifies AC characteristics switching 0000: Not extend the delay time 1001: Switches characteristics and extends the delay time Others: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 261 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.9 AC Characteristics Switching Key Register (ACKEYR) ACKEYR is a write only 8-bit register to access the AC characteristics switching register (ACSWR). The write value is ignored and the read value is undefined. Bit: 7 6 5 4 3 2 1 0 ACKEY[7:0] Initial value: R/W: W W W W W W W W Bit 7 to 0 Bit Name ACKEY[7:0] Initial Value R/W W Description AC Key Writing to this bit is required to write to the ACSWR register. The write value is arbitrary. Rev. 3.00 Jun. 18, 2008 Page 262 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.4.10 Sequence to Write to ACSWR Figure 8.2 shows the sequence to write to ACSWR. Write must be executed in the on-chip RAM. Main program routine Subroutine executed in on-chip RAM Write subroutine Byte write to ACKEYR (1) Transfer write subroutine to on-chip RAM Execute write subroutine Byte write to ACKEYR (2) Longword write to ACSWR (3) Read ACSWR to confirm Correcrly written (4) Incorrectly written Return Make sure to read and confirm as in step (4) after the write in step (3). If incorrectly written, execute from step (1) again. Figure 8.2 Recommended Sequence to Write to ACSWR Rev. 3.00 Jun. 18, 2008 Page 263 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5 8.5.1 Operation Endian/Access Size and Data Alignment This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte data. Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and SRAM with byte selection. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data bus widths (8 bits and 16 bits) are available for PCMCIA interface. For MPX-I/O, the data bus width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. The data bus width for burst MPX-I/O is fixed at 32 bits. Data alignment is performed in accordance with the data bus width of the device. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 8.5 to 8.7 show the relationship between device data width and access unit. Table 8.5 32-Bit External Device Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 D31 to D24 Data 7 to 0 Data 15 to 8 D23 to D16 Data 7 to 0 Data 7 to 0 Data 23 to 16 D15 to D8 Data 7 to 0 Data 15 to 8 Data 15 to 8 WE3, D7 to D0 DQMUU Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Strobe Signals WE2, DQMUL Assert Assert Assert WE1, DQMLU Assert Assert Assert WE0, DQMLL Assert Assert Assert Word access at 2 Longword access at 0 Data 31 to 24 Rev. 3.00 Jun. 18, 2008 Page 264 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.6 16-Bit External Device Access and Data Alignment Data Bus Strobe Signals D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 23 to 16 Data 7 to 0 WE3, DQMUU WE2, DQMUL WE1, DQMLU Assert Assert Assert Assert Assert Assert WE0, DQMLL Assert Assert Assert Assert Assert Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 D31 to D23 to D15 to D24 D16 D8 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 31 to 24 Data 15 to 8 Longword 1st access at 0 time at 0 2nd time at 2 Rev. 3.00 Jun. 18, 2008 Page 265 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.7 8-Bit External Device Access and Data Alignment Data Bus Strobe Signals WE3, DQMUU WE2, DQMUL WE1, DQMLU WE0, DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 1st time at 0 D31 to D23 to D15 to D24 D16 D8 D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 2nd time at 1 Word access at 2 1st time at 2 2nd time at 3 Longword access at 0 1st time at 0 2nd time at 1 3rd time at 2 4th time at 3 Rev. 3.00 Jun. 18, 2008 Page 266 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.2 (1) Normal Space Interface Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 8.5.8, SRAM Interface with Byte Selection. Figure 8.3 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. T1 T2 CKIO A25 to A0 CSn RD/WR Read RD D31 to D0 RD/WR Write WEn D31 to D0 BS DACKn * Note: * The waveform for DACKn is when active low is specified. Figure 8.3 Normal Space Basic Access Timing (Access Wait 0) There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always Rev. 3.00 Jun. 18, 2008 Page 267 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn signal for the byte to be written is asserted. It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision. Figures 8.4 and 8.5 show the basic timings of normal space access. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait (figure 8.4). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 8.5). T1 T2 Tnop T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 8.4 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) Rev. 3.00 Jun. 18, 2008 Page 268 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) T1 T2 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 8.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) Rev. 3.00 Jun. 18, 2008 Page 269 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) This LSI **** **** **** 128K x 8-bit SRAM **** **** **** **** **** **** **** **** A18 A2 CSn RD D31 **** A16 A0 CS OE I/O7 D24 WE3 D23 **** **** I/O0 WE **** D16 WE2 D15 **** **** A16 A0 CS OE I/O7 I/O0 WE **** D0 WE0 **** **** D8 WE1 D7 **** **** A16 A0 CS OE I/O7 I/O0 WE **** A16 A0 CS OE I/O7 I/O0 WE Figure 8.6 Example of 32-Bit Data-Width SRAM Connection Rev. 3.00 Jun. 18, 2008 Page 270 of 1160 REJ09B0191-0300 **** Section 8 Bus State Controller (BSC) This LSI **** **** **** 128K x 8-bit SRAM **** A17 A1 CSn RD D15 **** A16 A0 CS OE I/O7 D8 WE1 D7 **** **** I/O0 WE **** **** **** I/O0 WE Figure 8.7 Example of 16-Bit Data-Width SRAM Connection 128K x 8-bit SRAM A16 A0 CS OE I/O7 I/O0 WE ... ... This LSI A16 ... A0 CSn RD D7 D0 WE0 ... Figure 8.8 Example of 8-Bit Data-Width SRAM Connection Rev. 3.00 Jun. 18, 2008 Page 271 of 1160 REJ09B0191-0300 **** A0 CS OE I/O7 **** D0 WE0 A16 **** Section 8 Bus State Controller (BSC) 8.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 1, 4, 5, 7, and 8 to insert wait cycles independently in read access and in write access. Areas 0, 2, 3, and 6 have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 8.9. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.9 Wait Timing for Normal Space Access (Software Wait Only) Rev. 3.00 Jun. 18, 2008 Page 272 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 8.10. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle. Wait states inserted by WAIT signal Twx T2 T1 CKIO A25 to A0 CSn RD/WR RD Read Tw Tw D31 to D0 WEn Write D31 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.10 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT Signal) Rev. 3.00 Jun. 18, 2008 Page 273 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.4 CSn Assert Period Expansion The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 8.11 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.11 CSn Assert Period Expansion Rev. 3.00 Jun. 18, 2008 Page 274 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.5 MPX-I/O Interface Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits depending on the address to be accessed. Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous access cycles. Address output is increased to 3 cycles by setting the MPXW bit in CS5WCR to 1. The RD/WR signal is output at the same time as the CS5 signal; it is high in the read cycle and low in the write cycle. The data cycle is the same as that in a normal space access. Timing charts are shown in figures 8.12 to 8.14. Rev. 3.00 Jun. 18, 2008 Page 275 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Ta1 Ta2 Ta3 T1 T2 CKIO A25 to A0 CS5 RD/WR AH RD Read D15/D7 to D0 WEn Write D15/D7 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Address Data Address Data Figure 8.12 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait) Rev. 3.00 Jun. 18, 2008 Page 276 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Ta1 CKIO A25 to A0 CS5 RD/WR AH RD Read D15/D7 to D0 WEn Write D15/D7 to D0 BS DACKn* Tadw Ta2 Ta3 T1 T2 Address Data Address Data Note: * The waveform for DACKn is when active low is specified. Figure 8.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) Rev. 3.00 Jun. 18, 2008 Page 277 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Ta1 Tadw Ta2 Ta3 T1 Tw Twx T2 CKIO A25 to A0 CS5 RD/WR AH RD Read D15/D7 to D0 WEn Write Address Data D15/D7 to D0 WAIT Address Data BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.14 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) Rev. 3.00 Jun. 18, 2008 Page 278 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.6 (1) SDRAM Interface SDRAM Direct Connection The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RASU, RASL, CASU, CASL, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM can be set to 32 or 16 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RASU, RASL, CASU, CASL, RD/WR, and specific address signals. These commands supports: * * * * * * * * * * * NOP Auto-refresh (REF) Self-refresh (SELF) All banks pre-charge (PALL) Specified bank pre-charge (PRE) Bank active (ACTV) Read (READ) Read with pre-charge (READA) Write (WRIT) Write with pre-charge (WRITA) Write mode register (MRS, EMRS) The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx and the byte to be accessed, see section 8.5.1, Endian/Access Size and Data Alignment. Figures 8.15 to 8.17 show examples of the connection of the SDRAM with the LSI. Rev. 3.00 Jun. 18, 2008 Page 279 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) As shown in figure 8.17, two sets of SDRAMs of 32 Mbytes or smaller can be connected to the same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by RASU and CASU. When accessing the address with A25 = 0, RASL and CASL are asserted. When accessing the address with A25 = 1, RASU and CASU are asserted. 64M SDRAM (1M x 16-bit x 4-bank) A15 A13 A0 CKE CLK CS This LSI ... A2 CKE CKIO CSn RASU CASU RASL CASL RD/WR D31 Unused Unused RAS CAS WE I/O15 I/O0 DQMU DQML D16 DQMUU DQMUL D15 ... ... D0 DQMLU DQMLL A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML Figure 8.15 Example of 32-Bit Data Width SDRAM Connection (RASU and CASU are Not Used) Rev. 3.00 Jun. 18, 2008 Page 280 of 1160 REJ09B0191-0300 ... ... ... ... Section 8 Bus State Controller (BSC) This LSI A14 64M SDRAM (1M x 16-bit x 4-bank) A13 A0 CKE CLK CS A1 CKE CKIO CSn RASU CASU RASL CASL RD/WR D15 ... Unused Unused RAS CAS WE I/O15 I/O0 DQMU DQML D0 DQMLU DQMLL Figure 8.16 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Not Used) ... Rev. 3.00 Jun. 18, 2008 Page 281 of 1160 REJ09B0191-0300 ... ... Section 8 Bus State Controller (BSC) This LSI A14 ... 64M SDRAM (1M x 16-bit x 4-bank) A13 A0 CKE CLK CS ... A1 CKE CKIO CSn RASU CASU RASL CASL RD/WR D15 ... RAS CAS WE I/O15 I/O0 DQMU DQML ... D0 DQMLU DQMLL A13 A0 CKE CLK CS ... RAS CAS WE I/O15 I/O0 DQMU DQML ... Figure 8.17 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Used) Rev. 3.00 Jun. 18, 2008 Page 282 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (2) Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0], and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 8.8 to 8.13 show the relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ1 and BSZ0 = B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on. Rev. 3.00 Jun. 18, 2008 Page 283 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.8 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-1 Setting BSZ [1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 00 (11 bits) Row Address Output Cycle A25 A24 A23 A22* A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 2 A2/3 COL [1:0] 00 (8 bits) Column Address Output Cycle A17 A16 A15 A22*2 A21* L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 SDRAM Pin Function Unused A12 (BA1) A11 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Specifies address/precharge Address Unused Example of connected memory 64-Mbit product (512 Kwords x 32 bits x 4 banks, column 8-bit product): 1 16-Mbit product (512 Kwords x 16 bits x 2 banks, column 8-bit product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification. Rev. 3.00 Jun. 18, 2008 Page 284 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.8 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2 Setting BSZ [1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 01 (12 bits) Row Address Output Cycle A25 A24 A23*2 A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 A2/3 COL [1:0] 00 (8 bits) Column Address Output Cycle A17 A16 A23*2 A22* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 128-Mbit product (1 Mword x 32 bits x 4 banks, column 8-bit product): 1 64-Mbit product (1 Mword x 16 bits x 4 banks, column 8-bit product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification. Rev. 3.00 Jun. 18, 2008 Page 285 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 Setting BSZ [1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 01 (12 bits) Row Address Output Cycle A26 A25 A24*2 A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 A2/3 COL [1:0] 01 (9 bits) Column Address Output Cycle A17 A16 A24*2 A23* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 256-Mbit product (2 Mwords x 32 bits x 4 banks, column 9-bit product): 1 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9-bit product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification. 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted. Rev. 3.00 Jun. 18, 2008 Page 286 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 Setting BSZ [1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 01 (12 bits) Row Address Output Cycle A27 A26 A25*2*3 A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 2 A2/3 COL [1:0] 10 (10 bits) Column Address Output Cycle A17 A16 A25*2*3 A24* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10-bit product): 1 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10-bit product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification. 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted. Rev. 3.00 Jun. 18, 2008 Page 287 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.10 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3) Setting BSZ [1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 10 (13 bits) Row Address Output Cycle A26 A25*2*3 A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 A2/3 COL [1:0] 01 (9 bits) Column Address Output Cycle A17 A25*2*3 A24* A14 A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 512-Mbit product (4 Mwords x 32 bits x 4 banks, column 9-bit product): 1 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9-bit product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification. 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted. Rev. 3.00 Jun. 18, 2008 Page 288 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-1 Setting BSZ [1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 00 (11 bits) Row Address Output Cycle A25 A24 A23 A22 A21 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 A2/3 COL [1:0] 00 (8 bits) Column Address Output Cycle A17 A16 A15 A14 A21 A20*2 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 SDRAM Pin Function Unused A11 (BA) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Specifies address/precharge Address Unused Example of connected memory 16-Mbit product (512 Kwords x 16 bits x 2 banks, column 8-bit product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification. Rev. 3.00 Jun. 18, 2008 Page 289 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-2 Setting BSZ [1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 01 (12 bits) Row Address Output Cycle A25 A24 A23 A22* A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 2 A2/3 COL [1:0] 00 (8 bits) Column Address Output Cycle A17 A16 A15 A22*2 A21* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 64-Mbit product (1 Mword x 16 bits x 4 banks, column 8-bit product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification. Rev. 3.00 Jun. 18, 2008 Page 290 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-1 Setting BSZ [1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 01 (12 bits) Row Address Output Cycle A26 A25 A24 A23* A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 2 A2/3 COL [1:0] 01 (9 bits) Column Address Output Cycle A17 A16 A15 A23*2 A22* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9-bit product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification. Rev. 3.00 Jun. 18, 2008 Page 291 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-2 Setting BSZ [1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 01 (12 bits) Row Address Output Cycle A27 A26 A25 A24* A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 2 2 A2/3 COL [1:0] 10 (10 bits) Column Address Output Cycle A17 A16 A15 A24*2 A23* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10-bit product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification. Rev. 3.00 Jun. 18, 2008 Page 292 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-1 Setting BSZ [1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 10 (13 bits) Row Address Output Cycle A26 A25 A24*2 A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 A2/3 COL [1:0] 01 (9 bits) Column Address Output Cycle A17 A16 A24*2 A23* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9-bit product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification. 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted. Rev. 3.00 Jun. 18, 2008 Page 293 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-2 Setting BSZ [1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 10 (13 bits) Row Address Output Cycle A27 A26 A25*2*3 A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 2 A2/3 COL [1:0] 10 (10 bits) Column Address Output Cycle A17 A16 A25*2*3 A24* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 512-Mbit product (8 Mwords x 16 bits x 4 banks, column 10-bit product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification. 3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU is not asserted. Rev. 3.00 Jun. 18, 2008 Page 294 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (3) Burst Read A burst read occurs in the following cases with this LSI. * Access size in reading is larger than data bus width. * 16-byte transfer in cache miss. * 16-byte transfer in DMAC This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that is connected to a 32-bit data bus. This access is called the burst read with the burst number 4. Table 8.14 shows the relationship between the access size and the number of bursts. Table 8.14 Relationship between Access Size and Number of Bursts Bus Width 16 bits Access Size 8 bits 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 32 bits 16 bits Number of Bursts 1 1 2 8 1 1 1 4 Figures 8.18 and 8.19 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. Rev. 3.00 Jun. 18, 2008 Page 295 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM in variable frequencies. Figure 8.19 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and WTRCD0 bit in CS3WCR. The number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the SDRAM. A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for every burst read or every single read. Rev. 3.00 Jun. 18, 2008 Page 296 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.18 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge) Rev. 3.00 Jun. 18, 2008 Page 297 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Trw Tc1 Tw Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde (Tap) Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.19 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD[1:0] = 1 Cycle, Auto Pre-Charge) Rev. 3.00 Jun. 18, 2008 Page 298 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (4) Single Read A read access ends in one cycle when data exists in a cache-disabled space and the data bus width is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst length 1, only the required data is output. A read access that ends in one cycle is called single read. Figure 8.20 shows the single read basic timing. Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Td1 Tde (Tap) Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.20 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge) Rev. 3.00 Jun. 18, 2008 Page 299 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (5) Burst Write A burst write occurs in the following cases in this LSI. * Access size in writing is larger than data bus width. * Write-back of the cache * 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is connected to a 32-bit data bus. This access is called burst write with the burst number 4. The relationship between the access size and the number of bursts is shown in table 8.14. Figure 8.21 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the autoprecharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. Between the Trwl and the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. Rev. 3.00 Jun. 18, 2008 Page 300 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Tc2 Tc3 Tc4 Trwl Tap Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.21 Basic Timing for Burst Write (Auto Pre-Charge) Rev. 3.00 Jun. 18, 2008 Page 301 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (6) Single Write A write access ends in one cycle when data is written in a cache-disabled space and the data bus width is larger than or equal to access size. As a single write or burst write with burst length 1 is set in SDRAM, only the required data is output. The write access that ends in one cycle is called single write. Figure 8.22 shows the single write basic timing. Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Trwl Tap Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.22 Single Write Basic Timing (Auto-Precharge) Rev. 3.00 Jun. 18, 2008 Page 302 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (7) Bank Active The SDRAM bank function can be used to support high-speed access to the same row address. When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3. When area 3 is set to bank-active mode, area 2 should be set to normal space or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM or both the upper and lower bits of area 3 are connected to SDRAM, auto precharge mode must be set. When the bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As SDRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 8.23, a burst read cycle for the same row address in figure 8.24, and a burst read cycle for different row addresses in figure 8.25. Similarly, a burst write cycle without auto-precharge is shown in figure 8.26, a burst write cycle for the same row address in figure 8.27, and a burst write cycle for different row addresses in figure 8.28. In figure 8.24, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS Rev. 3.00 Jun. 18, 2008 Page 303 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMxx signal is asserted after the Tc cycle. When bank active mode is set, if only access cycles to the respective banks in the area 3 space are considered, as long as access cycles to the same row address continue, the operation starts with the cycle in figure 8.23 or 8.26, followed by repetition of the cycle in figure 8.24 or 8.27. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 8.24 or 8.27 is executed instead of that in figure 8.25 or 8.28. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Tr CKIO A25 to A0 A12/A11*1 CS3 RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.23 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1) Rev. 3.00 Jun. 18, 2008 Page 304 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tnop CKIO A25 to A0 A12/A11*1 CS3 RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.24 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1) Rev. 3.00 Jun. 18, 2008 Page 305 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tp CKIO A25 to A0 A12/A11*1 CS3 RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.25 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) Rev. 3.00 Jun. 18, 2008 Page 306 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tr CKIO A25 to A0 A12/A11*1 CS3 RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.26 Single Write Timing (Bank Active, Different Bank) Rev. 3.00 Jun. 18, 2008 Page 307 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tnop CKIO A25 to A0 A12/A11*1 CS3 RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.27 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank) Rev. 3.00 Jun. 18, 2008 Page 308 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tp CKIO A25 to A0 A12/A11*1 CS3 RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Tr Tc1 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.28 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) Rev. 3.00 Jun. 18, 2008 Page 309 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (8) Refreshing This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If SDRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. (a) Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS2 to CKS0 and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an autorefresh is performed for the number of times specified by the RRC2 to RRC0. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 8.29 shows the auto-refresh cycle timing. After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to pre-charged state from active state when some bank is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is longer than or equal to 1 cycle. Rev. 3.00 Jun. 18, 2008 Page 310 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tp CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Trr Trc Trc Trc Hi-z Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.29 Auto-Refresh Timing Rev. 3.00 Jun. 18, 2008 Page 311 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (b) Self-Refreshing Self-refresh mode in which the refresh timing and refresh addresses are generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WSR. SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR. Self-refresh timing is shown in figure 8.30. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode due to an interrupt. Note that the necessary signals such as CKE must be driven even in standby state by setting the HIZCNT bit in CMNCR to 1. When the multiplication rate for the PLL circuit is changed, the CKIO output will become unstable or will be fixed low. For details on the CKIO output, see section 3, Clock Pulse Generator (CPG). The contents of SDRAM can be retained by placing the SDRAM in the selfrefresh state before changing the multiplication rate. The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Rev. 3.00 Jun. 18, 2008 Page 312 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tp CKIO CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Trr Trc Trc Trc Hi-z Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.30 Self-Refresh Timing Rev. 3.00 Jun. 18, 2008 Page 313 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (9) Relationship between Refresh Requests and Bus Cycles If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. This LSI has the REFOUT pin to request the bus while waiting for refresh execution. For REFOUT pin function selection, see section 19, Pin Function Controller (PFC). This LSI continues to assert REFOUT (low level) until the bus is acquired. On receiving the asserted REFOUT signal, the external device must negate the BREQ signal and return the bus. If the external bus does not return the bus for a period longer than the specified refresh interval, refresh cannot be executed and the SDRAM contents may be lost. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus mastership occupation must be prevented from occurring. If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is completed. Rev. 3.00 Jun. 18, 2008 Page 314 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (10) Low-Frequency Mode When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency. Figure 8.31 shows the access timing in low-frequency mode. In this mode, commands, addresses, and write data are output in synchronization with the falling edge of CKIO, which is half a cycle delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a cycle faster than the normal timing. This timing allows the hold time of commands, addresses, write data, and read data to be extended. If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of commands, addresses, write data, and read data are not guaranteed. Take the operating frequency and timing design into consideration when making the SLOW bit setting. Tr CKIO Tc1 Td1 Tde Tap Tr Tc1 Tnop Trwl Tap (High) CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 8.31 Low-Frequency Mode Access Timing Rev. 3.00 Jun. 18, 2008 Page 315 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (11) Power-Down Mode If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the CKE in order to cancel the power-down mode. Figure 8.32 shows the access timing in power-down mode. Power-down CKIO CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Tnop Tr Tc1 Td1 Tde Tap Power-down Figure 8.32 Power-Down Mode Access Timing Rev. 3.00 Jun. 18, 2008 Page 316 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (12) Power-On Sequence In order to use SDRAM, mode setting must first be made for SDRAM after the pose interval specified for the SDRAM to be used after powering on. The pose interval should be obtained by a power-on reset generating circuit or software. To perform SDRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the SDRAM mode register by performing a write to address H'FFFC4000 + X for area 2 SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-size access to the addresses shown in table 8.15. In this time 0 is output at the external address pins of A12 or later. Table 8.15 Access Address in SDRAM Mode Register Write * Setting for Area 2 Burst read/single write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'FFFC4440 H'FFFC4460 H'FFFC4880 H'FFFC48C0 External Address Pin H'0000440 H'0000460 H'0000880 H'00008C0 Burst read/burst write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'FFFC4040 H'FFFC4060 H'FFFC4080 H'FFFC40C0 External Address Pin H'0000040 H'0000060 H'0000080 H'00000C0 Rev. 3.00 Jun. 18, 2008 Page 317 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * Setting for Area 3 Burst read/single write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'FFFC5440 H'FFFC5460 H'FFFC5880 H'FFFC58C0 External Address Pin H'0000440 H'0000460 H'0000880 H'00008C0 Burst read/burst write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'FFFC5040 H'FFFC5060 H'FFFC5080 H'FFFC50C0 External Address Pin H'0000040 H'0000060 H'0000080 H'00000C0 Mode register setting timing is shown in figure 8.33. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer than the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. Rev. 3.00 Jun. 18, 2008 Page 318 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tp PALL Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Hi-Z Figure 8.33 SDRAM Mode Write Timing (Based on JEDEC) Rev. 3.00 Jun. 18, 2008 Page 319 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (13) Low-Power SDRAM The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. The partial refresh is effective in systems in which there is data in a work area other than the specific area can be lost without severe repercussions. The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode registers as the normal SDRAM. This LSI supports issuing of the EMRS command. The EMRS command is issued according to the conditions specified in table below. For example, if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> REF x 8 -> MRS -> EMRS. In this case, the MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> MRS -> EMRS. Table 8.16 Output Addresses when EMRS Command Is Issued Command to be Issued CS2 MRS CS3 MRS CS2 MRS + EMRS (with refresh) CS3 MRS + EMRS (with refresh) CS2 MRS + EMRS (without refresh) CS3 MRS + EMRS (without refresh) H'FFFC5XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC4XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC5XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY Access Address H'FFFC4XX0 H'FFFC5XX0 H'FFFC4XX0 Write Access Size 16 bits 16 bits MRS EMRS Command Command Issue Address Issue Address H'0000XX0 H'0000XX0 H'0000XX0 H'YYYYYYY Access Data H'******** H'******** H'0YYYYYYY 32 bits Rev. 3.00 Jun. 18, 2008 Page 320 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tpw Tp PALL Trr REF Trc Trc Trr REF Trc Trc Tmw Tnop Temw Tnop MRS EMRS CKIO A25 to A0 BA1*1 BA0*2 A12/A11*3 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*4 Notes: 1. Address pin to be connected to pin BA1 of SDRAM. 2. Address pin to be connected to pin BA0 of SDRAM. 3. Address pin to be connected to pin A10 of SDRAM. 4. The waveform for DACKn is when active low is specified. Hi-Z Figure 8.34 EMRS Command Issue Timing Rev. 3.00 Jun. 18, 2008 Page 321 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) * Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed. Tp Tpw Tdpd Trc Trc Trc Trc Trc CKIO CKE A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Hi-Z Figure 8.35 Deep Power-Down Mode Transition Timing Rev. 3.00 Jun. 18, 2008 Page 322 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.7 Burst ROM (Clocked Asynchronous) Interface The burst ROM (clocked asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clocked asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent access cycles are performed only by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access cycles, addresses are changed at the falling edge of the CKIO. For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the W1 to W0 bits in CSnWCR is inserted. In the access to the burst ROM (clocked asynchronous), the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access or write access that does not perform the burst operation in the burst ROM (clocked asynchronous) interface, access timing is same as a normal space. In addition, there are some restrictions on 16-byte write access. For details, see section 8.6, Usage Notes. Table 8.17 lists a relationship between bus width, access size, and the number of bursts. Figure 8.36 shows a timing chart. Table 8.17 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width 8 bits Access Size 8 bits 16 bits 32 bits 16 bytes CSnWCR. BST[1:0] Bits Number of Bursts Access Count Not affected Not affected Not affected 00 01 16 bits 8 bits 16 bits 32 bits 16 bytes Not affected Not affected Not affected 00 01 10* 1 2 4 16 4 1 1 2 8 2 4 2, 4, 2 1 1 1 1 4 1 1 1 1 4 2 3 Rev. 3.00 Jun. 18, 2008 Page 323 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Bus Width 32 bits Access Size 8 bits 16 bits 32 bits 16 bytes CSnWCR. BST[1:0] Bits Number of Bursts Access Count Not affected Not affected Not affected Not affected 1 1 1 4 1 1 1 1 Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in CSnWCR are 10, the number of bursts and access count depend on the access start address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4 or H'xxxC, 2-4-2 burst access is performed. T1 CKIO A25 to A0 Tw Tw T2B Twb T2B Twb T2B Twb T2 CSn RD/WR RD D31 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.36 Burst ROM Access Timing (Clocked Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) Rev. 3.00 Jun. 18, 2008 Page 324 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.8 SRAM Interface with Byte Selection The SRAM interface with byte selection is for access to an SRAM which has a byte-selection pin (WEn). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM interface with byte selection is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic access timing is shown in figure 8.37. In write access, data is written to the memory according to the timing of the byteselection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 8.38 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 8.39 shows the access timing when a software wait is specified. Rev. 3.00 Jun. 18, 2008 Page 325 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) T1 T2 CKIO A25 to A0 CSn WEn RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.37 Basic Access Timing for SRAM with Byte Selection (BAS = 0) Rev. 3.00 Jun. 18, 2008 Page 326 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) T1 CKIO T2 A25 to A0 CSn WEn RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.38 Basic Access Timing for SRAM with Byte Selection (BAS = 1) Rev. 3.00 Jun. 18, 2008 Page 327 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Th CKIO T1 Tw T2 Tf A25 to A0 CSn WEn RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.39 Wait Timing for SRAM with Byte Selection (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) Rev. 3.00 Jun. 18, 2008 Page 328 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) This LSI 64K x 16-bit SRAM A17 ... A15 ... A2 CSn RD RD/WR D31 ... A0 CS OE WE I/O15 I/O0 UB LB ... D16 WE3 WE2 D15 ... A15 A0 CS OE WE I/O15 I/O0 UB LB ... ... This LSI A16 . . . A1 CSn RD RD/WR D15 . . . D0 WE1 WE0 64K x 16-bit SRAM D0 WE1 WE0 Figure 8.40 Example of Connection with 32-Bit Data-Width SRAM with Byte Selection A15 . . . A0 CS OE WE I/O 15 . . . I/O 0 UB LB Figure 8.41 Example of Connection with 16-Bit Data-Width SRAM with Byte Selection Rev. 3.00 Jun. 18, 2008 Page 329 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.9 PCMCIA Interface With this LSI, areas 5 and 6 can be used for the IC memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1 Rev. 2.1) by specifying bits TYPE[2:0] in CSnBCR (n = 5 and 6) to B'101. In addition, the bits SA[1:0] in CSnWCR (n = 5 and 6) assign the upper or lower 32 Mbytes of each area to IC memory card or I/O card interface. For example, if the bits SA1 and SA0 in CS5WCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes of area 5 are used for IC memory card interface and the lower 32 Mbytes are used for I/O card interface. When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using the bits BSZ[1:0] in CS5BCR or CS6BCR. Figure 8.42 shows an example of connection between this LSI and a PCMCIA card. To enable hot swapping (insertion and removal of the PCMCIA card with the system power turned on), tri-state buffers must be connected between the LSI and the PCMCIA card. In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined. Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI. Rev. 3.00 Jun. 18, 2008 Page 330 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) This LSI A25 to A0 D7 to D0 D15 to D8 RD/WR CS5B/CE1A CE2A G DIR G PC card (memory or I/O) A25 to A0 D7 to D0 D15 to D8 G DIR CE1 CE2 RD WE1/WE WE2/ICIORD WE3/ICIOWR REG (Output port) G OE WE/PGM IORD IOWR REG WAIT Card detector WAIT CD1, CD2 Figure 8.42 Example of PCMCIA Interface Connection Rev. 3.00 Jun. 18, 2008 Page 331 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (1) Basic Timing for Memory Card Interface Figure 8.43 shows the basic timing of the PCMCIA IC memory card interface. When areas 5 and 6 are specified as the PCMCIA interface, the bus is accessed with the IC memory card interface according to the SA[1:0] bit settings in CS5WCR and CS6WCR. If the external bus frequency (CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this LSI enables the setup times and hold times for areas 5 and 6 to be specified independently, using CS5WCR and CS6WCR. In the PCMCIA interface, as in the normal space interface, a software wait or hardware wait using the WAIT pin can be inserted. Figure 8.44 shows the PCMCIA memory bus wait timing. Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS Figure 8.43 Basic Access Timing for PCMCIA Memory Card Interface Rev. 3.00 Jun. 18, 2008 Page 332 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS WAIT Figure 8.44 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, PCW[3:0] = B'0000, TEH[3:0] = B'0001, Hardware Wait = 1) A port is used to generate the REG signal that switches between the common memory and attribute memory. As shown in the example in figure 8.46, when the total memory space necessary for the common memory and attribute memory is 32 Mbytes or less, pin A24 can be used as the REG signal to allocate a 16-Mbyte common memory space and a 16-Mbyte attribute memory space. Rev. 3.00 Jun. 18, 2008 Page 333 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) For 32-Mbyte capacity (I/O port is used for REG) Area 5: H'14000000 Attribute memory/common memory Area 6: H'16000000 I/O space Area 5: H'18000000 Attribute memory/common memory Area 6: H'1A000000 I/O space For 16-Mbyte capacity (A24 is used for REG) Area 5: H'14000000 Area 5: H'15000000 Area 5: H'16000000 H'17000000 Area 6: H'18000000 Area 6: H'19000000 Area 6: H'1A000000 H'1B000000 Attribute memory Common memory I/O space Attribute memory Common memory I/O space Figure 8.45 Example of PCMCIA Space Allocation (CS5WCR.SA[1:0] = B'10, CS6WCR.SA[1:0] = B'10) Rev. 3.00 Jun. 18, 2008 Page 334 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) (2) Basic Timing for I/O Card Interface Figures 8.46 and 8.47 show the basic timings for the PCMCIA I/O card interface. When accessing an I/O card with the PCMCIA interface, be sure to access the cache-disabled spaces. The I/O card and IC memory card interfaces are switched by an address to be accessed according to the SA[1:0] bit settings in CS5WCR and CS6WCR. Note that the bus width cannot be switched dynamically with the IOIS16 signal, which is output from an I/O card. The bus width must always be switched by modifying the CS5BCR or CS6BCR setting. In addition, there are some restrictions on the bus width of the I/O card interface. For details, see section 8.6, Usage Notes. Tpci1 Tpci1w Tpci1w Tpci1w Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS Figure 8.46 Basic Access Timing for PCMCIA I/O Card Interface Rev. 3.00 Jun. 18, 2008 Page 335 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CExx RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS WAIT Figure 8.47 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010, PCW[3:0] = B'0000, TEH[3:0] = B'0001, Hardware Wait = 1) Rev. 3.00 Jun. 18, 2008 Page 336 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.10 Burst MPX-I/O Interface Figure 8.48 shows an example of a connection between the LSI and the burst MPX device. Figures 8.49 to 8.52 show the burst MPX space access timings. Area 6 can be specified as the address/data multiplex I/O (MPX-I/O) interface using the TYPE2 to TYPE0 bits in CS6BCR. This MPX-I/O interface enables the LSI to be easily connected to an external memory controller chip that uses an address/data multiplexed 32-bit single bus. In this case, the address and the access size for the MPX-I/O interface are output to D25 to D0 and D31 to D29, respectively, in address cycles. For the access sizes of D31 to D29, see the description of CS6WCR in section 8.4.3 (5), Burst MPX-I/O. Address pins A25 to A0 are used to output normal addresses. In the burst MPX-I/O interface, the bus size is fixed at 32 bits. The BSZ1 and BSZ0 bits in CS6BCR must be specified as 32 bits. In the burst MPX-I/O interface, a software wait and hardware wait using the WAIT pin can be inserted. In read cycles, a wait cycle is inserted automatically following the address output even if the software wait insertion is specified as 0. 64K x 16-bit SRAM This LSI CS6 BS FRAME RD/WR D31 D0 WAIT CS BS FRAME WE I/O31 I/O0 WAIT Figure 8.48 Burst MPX Device Connection Example Rev. 3.00 Jun. 18, 2008 Page 337 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tm1 Tmd1w Tmd1 CKIO FRAME D31 to D0 A D A25 to A0 CS6 RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.49 Burst MPX Space Access Timing (Single Read, No Wait, or Software Wait 1) Rev. 3.00 Jun. 18, 2008 Page 338 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tm1 Tmd1w Tmd1w Tmd1 CKIO FRAME D31 to D0 A D A25 to A0 CS6 RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.50 Burst MPX Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1) Rev. 3.00 Jun. 18, 2008 Page 339 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CKIO FRAME D31 to D0 A D0 D1 D2 D3 A25 to A0 CS6 RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.51 Burst MPX Space Access Timing (Burst Read, No Wait, or Software Wait 1, CS6WCR.MPXMD = 0) Rev. 3.00 Jun. 18, 2008 Page 340 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Tm1 Tmd1 Tmd2 Tmd3 Tmd4 CKIO FRAME D31 to D0 A D0 D1 D2 D3 A25 to A0 CS6 RD/WR WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 8.52 Burst MPX Space Access Timing (Burst Write, No Wait, CS6WCR.MPXMD = 0) Rev. 3.00 Jun. 18, 2008 Page 341 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.11 Burst ROM (Clocked Synchronous) Interface The burst ROM (clocked synchronous) interface is supported to access a ROM with a synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only for area 0. In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR. While the burst ROM (clocked synchronous) is accessed, the BS signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width for the burst ROM. The burst ROM interface performs burst operations for all read access. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, it is recommended using a 16-byte read by cache fill in the cache-enabled spaces or 16-byte read by the DMA. The burst ROM interface performs write access in the same way as normal space access. T1 CKIO A25 to A0 CS0 RD/WR RD D15 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Tw Tw T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2 Figure 8.53 Burst ROM Access Timing (Clocked Synchronous) (Burst Length = 8, Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) Rev. 3.00 Jun. 18, 2008 Page 342 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.12 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting idle (wait) cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by the WM bit in CSnWCR, bits IWW2 to IWW0, IWRWD2 to IWRWD0, IWRWS2 to IWRWS0, IWRRD2 to IWRRD0, and IWRRS2 to IWRRS 0 in CSnBCR, and bits DMAIW2 to DMAIW0 and DMAIWA in CMNCR. The conditions for setting the idle cycles between access cycles are shown below. Continuous access cycles are write-read or write-write Continuous access cycles are read-write for different spaces Continuous access cycles are read-write for the same space Continuous access cycles are read-read for different spaces Continuous access cycles are read-read for the same space Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output from an external device caused by DMA single address transfer is followed by any type of access (DMAIWA = 1) For the specification of the number of idle cycles between access cycles described above, refer to the description of each register. Besides the idle cycles between access cycles specified by the registers, idle cycles must be inserted to interface with the internal bus or to obtain the minimum pulse width for a multiplexed pin (WEn). The following gives detailed information about the idle cycles and describes how to estimate the number of idle cycles. The number of idle cycles on the external bus from CSn negation to CSn or CSm assertion is described below. Here, CSn and CSm also include CE2A and CE2B for PCMCIA. There are eight conditions that determine the number of idle cycles on the external bus as shown in table 8.18. The effects of these conditions are shown in figure 8.54. 1. 2. 3. 4. 5. 6. Rev. 3.00 Jun. 18, 2008 Page 343 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.18 Conditions for Determining Number of Idle Cycles No. Condition [1] DMAIW[2:0] in CMNCR Description Range Note When 0 is specified for the number of idle cycles, the DACK signal may be asserted continuously. This causes a discrepancy between the number of cycles detected by the device with DACK and the DMAC transfer count, resulting in a malfunction. Do not set 0 for the number of idle cycles between memory types which are not allowed to be accessed successively. These bits specify the number of 0 to 12 idle cycles for DMA single address transfer. This condition is effective only for single address transfer and generates idle cycles after the access is completed. [2] IW***[2:0] in CSnBCR These bits specify the number of 0 to 12 idle cycles for access other than single address transfer. The number of idle cycles can be specified independently for each combination of the previous and next cycles. For example, in the case where reading CS1 space followed by reading other CS space, the bits IWRRD[2:0] in CS1BCR should be set to B'100 to specify six or more idle cycles. This condition is effective only for access cycles other than single address transfer and generates idle cycles after the access is completed. [3] SDRAM-related These bits specify precharge 0 to 3 bits in completion and startup wait cycles CSnWCR and idle cycles between commands for SDRAM access. This condition is effective only for SDRAM access and generates idle cycles after the access is completed WM in CSnWCR This bit enables or disables external 0 or 1 WAIT pin input for the memory types other than SDRAM. When this bit is cleared to 0 (external WAIT enabled), one idle cycle is inserted to check the external WAIT pin input after the access is completed. When this bit is set to 1 (disabled), no idle cycle is generated. Specify these bits in accordance with the specification of the target SDRAM. [4] Rev. 3.00 Jun. 18, 2008 Page 344 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) No. Condition [5] Read data transfer cycle Description Range Note One idle cycle is always generated after a read cycle with SDRAM or PCMCIA interface. One idle cycle is inserted after a 0 or 1 read access is completed. This idle cycle is not generated for the first or middle cycles in divided access cycles. This is neither generated when the HW[1:0] bits in CSnWCR are not B'00. [6] Internal bus External bus access requests from 0 or idle cycles, etc. the CPU or DMAC and their results larger are passed through the internal bus. The external bus enters idle state during internal bus idle cycles or while a bus other than the external bus is being accessed. This condition is not effective for divided access cycles, which are generated by the BSC when the access size is larger than the external data bus width. Write data wait During write access, a write cycle is 0 or 1 cycles executed on the external bus only after the write data becomes ready. This write data wait period generates idle cycles before the write cycle. Note that when the previous cycle is a write cycle and the internal bus idle cycles are shorter than the previous write cycle, write data can be prepared in parallel with the previous write cycle and therefore, no idle cycle is generated (write buffer effect). Idle cycles between different memory types The number of internal bus idle cycles may not become 0 depending on the I:B clock ratio. Tables 8.19 and 8.20 show the relationship between the clock ratio and the minimum number of internal bus idle cycles. [7] For write write or write read access cycles, successive access cycles without idle cycles are frequently available due to the write buffer effect described in the left column. If successive access cycles without idle cycles are not allowed, specify the minimum number of idle cycles between access cycles through CSnBCR. [8] To ensure the minimum pulse width 0 to 2.5 The number of idle cycles on the signal-multiplexed pins, idle depends on the target memory cycles may be inserted before types. See table 8.21. access after memory types are switched. For some memory types, idle cycles are inserted even when memory types are not switched. Rev. 3.00 Jun. 18, 2008 Page 345 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) In the above conditions, a total of four conditions, that is, condition [1] or [2] (either one is effective), condition [3] or [4] (either one is effective), a set of conditions [5] to [7] (these are generated successively, and therefore the sum of them should be taken as one set of idle cycles), and condition [8] are generated at the same time. The maximum number of idle cycles among these four conditions become the number of idle cycles on the external bus. To ensure the minimum idle cycles, be sure to make register settings for condition [1] or [2]. CKIO Previous access External bus idle cycles Next access CSn Idle cycle after access Idle cycle before access [1] DMAIW[2:0] setting in CMNCR [2] IWW[2:0] setting in CSnBCR IWRWD[2:0] setting in CSnBCR IWRWS[2:0] setting in CSnBCR IWRRD[2:0] setting in CSnBCR IWRRS[2:0] setting in CSnBCR [3] WTRP[1:0] setting in CSnWCR TRWL[1:0] setting in CSnWCR WTRC[1:0] setting in CSnWCR [4] WM setting in CSnWCR [5] Read data transfer [7] Write data wait Either one of them is effective Condition [1] or [2] Either one of them is effective Condition [3] or [4] [6] Internal bus idle cycles, etc. Set of conditions [5] to [7] [8] Idle cycles between Condition [8] different memory types Note: A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7], and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of cycles among these four conditions become the number of idle cycles. Figure 8.54 Idle Cycle Conditions Rev. 3.00 Jun. 18, 2008 Page 346 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.19 Minimum Number of Idle Cycles on Internal Bus (CPU Operation) Clock Ratio (I:B) CPU Operation Write write Write read Read write Read read 8:1 1 0 1 0 6:1 1 0 1 0 4:1 2 0 2 0 3:1 2 0 2 0 2:1 2 0 2 0 1:1 3 1 3 1 Table 8.20 Minimum Number of Idle Cycles on Internal Bus (DMAC Operation) Transfer Mode DMAC Operation Write write Write read Read write Read read Dual Address 0 0 or 2 0 0 Single Address 2 0 0 2 Notes: 1. The write write and read read columns in dual address transfer indicate the cycles in the divided access cycles. 2. For the write read cycles in dual address transfer, 0 means different channels are activated successively and 2 means when the same channel is activated successively. 3. The write read and read write columns in single address transfer indicate the case when different channels are activated successively. The "write" means transfer from a device with DACK to external memory and the "read" means transfer from external memory to a device with DACK. Rev. 3.00 Jun. 18, 2008 Page 347 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Table 8.21 Number of Idle Cycles Inserted between Access Cycles to Different Memory Types Next Cycle Byte SRAM Burst ROM Previous Cycle SRAM SRAM Burst ROM (asynchronous) MPX-I/O Byte SRAM (BAS = 0) Byte SRAM (BAS = 1) SDRAM SDRAM (low-frequency mode) PCMCIA Burst MPX Burst ROM (synchronous) 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1.5 1.5 1.5 0 0 0 0 0 0 0 0 0 1 1.5 1 1.5 2 2.5 1 1.5 0 0.5 0 1 1 1.5 1 1.5 1 1.5 1 1 2 1 0 0 1.5 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1.5 1.5 1 0 1 0 1 0 0 0 (Asynchronous) I/O 0 0 1 1 0) 0 0 Byte SRAM 1) 1 1 SDRAM (LowFrequency SDRAM Mode) 1 1 1.5 1.5 Burst Burst ROM PCMCIA MPX 0 0 0 0 (Synchronous) 0 0 MPX- (BAS = (BAS = Figure 8.55 shows sample estimation of idle cycles between access cycles. In the actual operation, the idle cycles may become shorter than the estimated value due to the write buffer effect or may become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU instruction execution or CPU register conflicts. Please consider these errors when estimating the idle cycles. Rev. 3.00 Jun. 18, 2008 Page 348 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Sample Estimation of Idle Cycles between Access Cycles This example estimates the idle cycles for data transfer from the CS1 space to CS2 space by CPU access. Transfer is repeated in the following order: CS1 read CS1 read CS2 write CS2 write CS1 read ... * Conditions The bits for setting the idle cycles between access cycles in CS1BCR and CS2BCR are all set to 0. In CS1WCR and CS2WCR, the WM bit is set to 1 (external WAIT pin disabled) and the HW[1:0] bits are set to 00 (CS negation is not extended). I:B is set to 4:1, and no other processing is done during transfer. For both the CS1 and CS2 spaces, normal SRAM devices are connected, the bus width is 32 bits, and access size is also 32 bits. The idle cycles generated under each condition are estimated for each pair of access cycles. In the following table, R indicates a read cycle and W indicates a write cycle. Condition [1] or [2] [3] or [4] [5] [6] [7] [5] + [6] + [7] [8] Estimated idle cycles Actual idle cycles RR 0 0 1 0 0 1 0 1 1 RW 0 0 1 2 1 4 0 4 4 WW 0 0 0 2 0 2 0 2 2 WR 0 0 0 0 0 0 0 0 1 Value for SRAM SRAM access Maximum value among conditions [1] or [2], [3] or [4], [5] + [6] + [7], and [8] The estimated value does not match the actual value in the W R cycles because the internal idle cycles due to condition [6] is estimated as 0 but actually an internal idle cycle is generated due to execution of a loop condition check instruction. CSnBCR is set to 0. The WM bit is set to 1. Generated after a read cycle. See the I:B = 4:1 columns in table 8.19. No idle cycle is generated for the second time due to the write buffer effect. Note Figure 8.55 Comparison between Estimated Idle Cycles and Actual Value Rev. 3.00 Jun. 18, 2008 Page 349 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.5.13 Bus Arbitration The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus mastership after receiving a bus request from another device. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn signal or other bus control signals. The states that do not allow bus mastership release are shown below. 1. 2. 3. 4. 16-byte transfer because of a cache miss During write-back operation for the cache Between the read and write cycles of a TAS instruction Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) 5. 16-byte transfer by the DMAC 6. Setting the BLOCK bit in CMNCR to 1 Moreover, by using DPRTY bit in CMNCR, whether the bus mastership request is received or not can be selected during DMAC burst transfer. The LSI has the bus mastership until a bus request is received from another device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the external device has released the bus, it negates the BACK signal and resumes the bus usage. With the SDRAM interface, all bank pre-charge commands (PALLs) are issued when active banks exist and the bus is released after completion of a PALL command. The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals (BS, CSn, RASU, RASL, CASU, CASL, CKE, DQMxx, WEn, RD, and RD/WR) are placed in the high-impedance state at subsequent rising edges of CKIO. Bus request signals are sampled at Rev. 3.00 Jun. 18, 2008 Page 350 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) the falling edge of CKIO. Note that CKE, RASU, RASL, CASU, and CASL can be continued to be driven at the previous value even in the bus-released state by setting the HIZCNT bit in CMNCR. The sequence for reclaiming the bus mastership from an external device is described below. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO where address and data signals are driven. Figure 8.56 shows the bus arbitration timing. When it is necessary to refresh SDRAM while releasing the bus mastership, the bus mastership should be returned using the REFOUT signal. For details on the selection of REFOUT, see section 19, Pin Function Controller (PFC). The REFOUT signal is kept asserting at low level until the bus mastership is acquired. The BREQ signal is negated by asserting the REFOUT signal and the bus mastership is returned from the external device. If the bus mastership is not returned for a refreshing period or longer, the contents of SDRAM cannot be guaranteed because a refreshing cannot be executed. While releasing the bus mastership, the SLEEP instruction (to enter the sleep mode or the software standby mode), as well as a manual reset, cannot be executed until the LSI obtains the bus mastership. The BREQ input signal is ignored in software standby mode and the BACK output signal is placed in the high impedance state. If the bus mastership request is required in this state, the bus mastership must be released by pulling down the BACK pin to enter software standby mode. The bus mastership release (BREQ signal for high level negation) after the bus mastership request (BREQ signal for low level assertion) must be performed after the bus usage permission (BACK signal for low level assertion). If the BREQ signal is negated before the BACK signal is asserted, only one cycle of the BACK signal is asserted depending on the timing of the BREQ signal to be negated and this may cause a bus contention between the external device and the LSI. Rev. 3.00 Jun. 18, 2008 Page 351 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) CKIO BREQ BACK A25 to A0 D31 to D0 CSn Other bus contorol sigals Figure 8.56 Bus Arbitration Timing (Clock Mode 7) 8.5.14 (1) Others Reset The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state after the internal reset is synchronized with the internal clock. All control registers are initialized. In software standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, only the current bus cycle being executed is completed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. (2) Access from the Side of the LSI Internal Bus Master There are three types of LSI internal buses: a CPU bus, internal bus, and peripheral bus. The CPU and cache memory are connected to the CPU bus. Internal bus masters other than the CPU and bus state controller are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memories other than the cache memory are connected bidirectionally to the CPU bus and internal bus. Access from the CPU bus to the internal bus is enabled but access from the internal bus to the cache bus is disabled. This gives rise to the following problems. On-chip bus masters such as DMAC other than the CPU can access internal memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software. In a cache-enabled space, if the CPU initiates read access, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the Rev. 3.00 Jun. 18, 2008 Page 352 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four contiguous longword access cycles to perform a cache fill operation on the external interface. For a cache-disabled space, the CPU performs access according to the actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of an on-chip peripheral module, the cycle is initiated through the internal bus and peripheral bus. The read data is sent to the CPU via the peripheral bus, internal bus, and CPU bus. In a write cycle for the cache-enabled space, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. Following these operations, a write-back cycle for the saved 16-byte data is executed. In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not modified but an actual write is performed via the internal bus. Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by a bus master other than the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. Rev. 3.00 Jun. 18, 2008 Page 353 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Changing the registers in the BSC while the write buffer is operating may disrupt correct write access. Therefore, do not change the registers in the BSC immediately after a write access. If this change becomes necessary, do it after executing a dummy read of the write data. (3) On-Chip Peripheral Module Access To access an on-chip module register, two or more peripheral module clock (P) cycles are required. Care must be taken in system design. When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without waiting for the completion of writing to registers. For example, a case is described here in which the system is transferring to the software standby mode for power savings. To make this transition, the SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy read of registers to which write instruction is given and then perform the succeeding instructions. Rev. 3.00 Jun. 18, 2008 Page 354 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) 8.6 8.6.1 Usage Notes Burst ROM Interface When the burst ROM interface (clocked asynchronous) is used and the following three conditions are met, read/write access from the external bus space immediately after write access may be invalid. 1. The 16-bit bus width is used for the burst ROM interface (clocked asynchronous). (The CSnBCR.TYPE[2:0] setting is B'001 and the CSnWCR.BSZ[1:0] setting is B'10) 2. The burst length is specified as 4. (The CSnWCR.BST[1:0] setting is B'10) 3. Write-back is performed with operand cache or 16-byte write access is performed with the DMAC for the burst ROM interface set as above. 8.6.2 PCMCIA I/O Card Interface When the following two conditions are met in the PCMCIA I/O card interface, read/write access may be performed with the 8-bit bus width even if the 16-bit bus width has been specified. 1. The 16-bit bus width is specified for the PCMCIA I/O card interface (The CSnBCR.TYPE[2:0] setting is B'101, the CSnBCR.BSZ[1:0] setting is B'10, and the CSnWCR.SA[1:0] setting is not B'00) 2. The number of delay cycles from address output to RD/WE assertion is specified as other than 0.5 cycle (The CSnWCR.TED[3:0] setting is not B'0000) 8.6.3 Burst MPX-I/O Interface When a contention occurs between SDRAM auto-refreshing and read/write access to the burst MPX-I/O interface, both the CS signal of the SDRAM space and the CS signal of the burst MPXI/O space are asserted and access to the burst MPX-I/O may not be performed correctly. Do not use the SDRAM interface and the burst MPX-I/O interface at the same time. Each can be used independently, and SDRAM can be used with interfaces other than the burst MPX-I/O. Rev. 3.00 Jun. 18, 2008 Page 355 of 1160 REJ09B0191-0300 Section 8 Bus State Controller (BSC) Rev. 3.00 Jun. 18, 2008 Page 356 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Section 9 Direct Memory Access Controller (DMAC) The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 9.1 Features * Number of channels: Eight channels (channels 0 to 7) selectable Four channels (channels 0 to 3) can receive external requests. * 4-Gbyte physical address space * Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes (longword x 4) * Maximum transfer count: 16,777,216 transfers (24 bits) * Address mode: Dual address mode and single address mode are supported. * Transfer requests External request On-chip peripheral module request Auto request The following modules can issue on-chip peripheral module requests. Eight SCIF sources, two IIC3 sources, two A/D converter sources, five MTU2 sources, and two CMT sources * Selectable bus modes Cycle steal mode (normal mode and intermittent mode) Burst mode * Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode. * Interrupt request: An interrupt request can be sent to the CPU on completion of half- or fulldata transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to the CPU when half of the initially specified DMA transfer is completed. * External request detection: There are following four types of DREQ input detection. Low level detection High level detection Rising edge detection Falling edge detection Rev. 3.00 Jun. 18, 2008 Page 357 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) * Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. * Support of reload functions in DMA transfer information registers: DMA transfer using the same information as the current transfer can be repeated automatically without specifying the information again. Modifying the reload registers during DMA transfer enables next DMA transfer to be done using different transfer information. The reload function can be enabled or disabled independently in each channel. Rev. 3.00 Jun. 18, 2008 Page 358 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Figure 9.1 shows the block diagram of the DMAC. RDMATCR_n On-chip memory On-chip peripheral module Iteration control Register control Peripheral bus Internal bus DMATCR_n RSAR_n SAR_n Start-up control RDAR_n DAR_n CHCR_n DMA transfer request signal DMA transfer acknowledge signal Interrupt controller HEIn DEIn Request priority control DMAOR DMARS0 to DMARS3 External ROM External RAM External device (memory mapped) Bus interface DMAC module External device (with acknowledge) Bus state controller DREQ0 to DREQ3 DACK0 to DACK3, TEND0, TEND1 [Legend] RDMATCR: DMA reload transfer count register DMATCR: DMA transfer count register DMA reload source address register RSAR: DMA source address register SAR: DMA reload destination address register RDAR: DMA destination address register DAR: DMA channel control register CHCR: DMA operation register DMAOR: DMARS0 to DMARS3: DMA extension resource selectors 0 to 3 DMA transfer half-end interrupt request to the CPU HEIn: DMA transfer end interrupt request to the CPU DEIn: n = 0 to 7 Figure 9.1 Block Diagram of DMAC Rev. 3.00 Jun. 18, 2008 Page 359 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.2 Input/Output Pins The external pins for DMAC are described below. Table 9.1 lists the configuration of the pins that are connected to external bus. DMAC has pins for four channels (channels 0 to 3) for external bus use. Table 9.1 Pin Configuration Abbreviation I/O I O Function DMA transfer request input from an external device to channel 0 DMA transfer request acknowledge output from channel 0 to an external device DMA transfer request input from an external device to channel 1 DMA transfer request acknowledge output from channel 1 to an external device DMA transfer request input from an external device to channel 2 DMA transfer request acknowledge output from channel 2 to an external device DMA transfer request input from an external device to channel 3 DMA transfer request acknowledge output from channel 3 to an external device DMA transfer end output for channel 0 DMA transfer end output for channel 1 Channel Name 0 DMA transfer request DREQ0 DMA transfer request DACK0 acknowledge 1 DMA transfer request DREQ1 DMA transfer request DACK1 acknowledge I O 2 DMA transfer request DREQ2 DMA transfer request DACK2 acknowledge I O 3 DMA transfer request DREQ3 DMA transfer request DACK3 acknowledge I O 0 1 DMA transfer end DMA transfer end TEND0 TEND1 O O Rev. 3.00 Jun. 18, 2008 Page 360 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3 Register Descriptions The DMAC has the registers listed in table 9.2. There are four control registers and three reload registers for each channel, and one common control register is used by all channels. In addition, there is one extension resource selector per two channels. Each channel number is expressed in the register names, as in SAR_0 for SAR in channel 0. Table 9.2 Channel 0 Register Configuration Register Name DMA source address register_0 DMA destination address register_0 DMA transfer count register_0 DMA channel control register_0 DMA reload source address register_0 Abbreviation R/W SAR_0 DAR_0 DMATCR_0 CHCR_0 RSAR_0 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1000 H'FFFE1004 H'FFFE1008 Access Size 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'FFFE100C 8, 16, 32 H'FFFE1100 H'FFFE1104 H'FFFE1108 H'FFFE1010 H'FFFE1014 H'FFFE1018 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 DMA reload destination RDAR_0 address register_0 DMA reload transfer count register_0 1 DMA source address register_1 DMA destination address register_1 DMA transfer count register_1 DMA channel control register_1 DMA reload source address register_1 RDMATCR_0 R/W SAR_1 DAR_1 DMATCR_1 CHCR_1 RSAR_1 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'FFFE101C 8, 16, 32 H'FFFE1110 H'FFFE1114 H'FFFE1118 16, 32 16, 32 16, 32 DMA reload destination RDAR_1 address register_1 DMA reload transfer count register_1 RDMATCR_1 R/W Rev. 3.00 Jun. 18, 2008 Page 361 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Channel 2 Register Name DMA source address register_2 DMA destination address register_2 DMA transfer count register_2 DMA channel control register_2 DMA reload source address register_2 Abbreviation R/W SAR_2 DAR_2 DMATCR_2 CHCR_2 RSAR_2 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1020 H'FFFE1024 H'FFFE1028 Access Size 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'FFFE102C 8, 16, 32 H'FFFE1120 H'FFFE1124 H'FFFE1128 H'FFFE1030 H'FFFE1034 H'FFFE1038 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 DMA reload destination RDAR_2 address register_2 DMA reload transfer count register_2 3 DMA source address register_3 DMA destination address register_3 DMA transfer count register_3 DMA channel control register_3 DMA reload source address register_3 RDMATCR_2 R/W SAR_3 DAR_3 DMATCR_3 CHCR_3 RSAR_3 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'FFFE103C 8, 16, 32 H'FFFE1130 H'FFFE1134 H'FFFE1138 16, 32 16, 32 16, 32 DMA reload destination RDAR_3 address register_3 DMA reload transfer count register_3 RDMATCR_3 R/W Rev. 3.00 Jun. 18, 2008 Page 362 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Channel 4 Register Name DMA source address register_4 DMA destination address register_4 DMA transfer count register_4 DMA channel control register_4 DMA reload source address register_4 Abbreviation R/W SAR_4 DAR_4 DMATCR_4 CHCR_4 RSAR_4 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1040 H'FFFE1044 H'FFFE1048 Access Size 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'FFFE104C 8, 16, 32 H'FFFE1140 H'FFFE1144 H'FFFE1148 H'FFFE1050 H'FFFE1054 H'FFFE1058 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 DMA reload destination RDAR_4 address register_4 DMA reload transfer count register_4 5 DMA source address register_5 DMA destination address register_5 DMA transfer count register_5 DMA channel control register_5 DMA reload source address register_5 RDMATCR_4 R/W SAR_5 DAR_5 DMATCR_5 CHCR_5 RSAR_5 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'FFFE105C 8, 16, 32 H'FFFE1150 H'FFFE1154 H'FFFE1158 16, 32 16, 32 16, 32 DMA reload destination RDAR_5 address register_5 DMA reload transfer count register_5 RDMATCR_5 R/W Rev. 3.00 Jun. 18, 2008 Page 363 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Channel 6 Register Name DMA source address register_6 DMA destination address register_6 DMA transfer count register_6 DMA channel control register_6 DMA reload source address register_6 Abbreviation R/W SAR_6 DAR_6 DMATCR_6 CHCR_6 RSAR_6 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1060 H'FFFE1064 H'FFFE1068 Access Size 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'FFFE106C 8, 16, 32 H'FFFE1160 H'FFFE1164 H'FFFE1168 H'FFFE1070 H'FFFE1074 H'FFFE1078 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 DMA reload destination RDAR_6 address register_6 DMA reload transfer count register_6 7 DMA source address register_7 DMA destination address register_7 DMA transfer count register_7 DMA channel control register_7 DMA reload source address register_7 RDMATCR_6 R/W SAR_7 DAR_7 DMATCR_7 CHCR_7 RSAR_7 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'FFFE107C 8, 16, 32 H'FFFE1170 H'FFFE1174 H'FFFE1178 16, 32 16, 32 16, 32 DMA reload destination RDAR_7 address register_7 DMA reload transfer count register_7 RDMATCR_7 R/W Rev. 3.00 Jun. 18, 2008 Page 364 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Channel Common 0 and 1 2 and 3 4 and 5 6 and 7 Register Name Abbreviation R/W Initial Value Address H'FFFE1200 H'FFFE1300 H'FFFE1304 H'FFFE1308 Access Size 8, 16 16 16 16 DMA operation register DMAOR DMA extension resource selector 0 DMA extension resource selector 1 DMA extension resource selector 2 DMA extension resource selector 3 DMARS0 DMARS1 DMARS2 DMARS3 R/W*2 H'0000 R/W R/W R/W R/W H'0000 H'0000 H'0000 H'0000 H'FFFE130C 16 Notes: 1. For the HE and TE bits in CHCRn, only 0 can be written to clear the flags after 1 is read. 2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is read. 9.3.1 DMA Source Address Registers (SAR) The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in single address mode, SAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. SAR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 365 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.2 DMA Destination Address Registers (DAR) The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. When the data of an external device with DACK is transferred in single address mode, DAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. DAR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 366 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.3 DMA Transfer Count Registers (DMATCR) The DMA transfer count registers (DMATCR) are 32-bit readable/writable registers that specify the number of DMA transfers. The transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. DMATCR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 367 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.4 DMA Channel Control Registers (CHCR) The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control the DMA transfer mode. The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions can be read and written to in channels 0 to 3, but they are reserved in channels 4 to 7. The TL bit which specifies the TEND external pin function can be read and written to in channels 0 and 1, but it is reserved in channels 2 to 7. CHCR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 31 TC 30 - 29 - 28 RLD 27 - 26 - 25 - 24 - 23 DO 22 TL 21 - 20 - 19 HE 18 HIE 17 AM 16 AL Initial value: R/W: Bit: 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 0 R/(W)* R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 DL 6 DS 5 TB 4 3 TS[1:0] 2 IE 1 TE 0 DE DM[1:0] SM[1:0] RS[3:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 0 R/W R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. Bit 31 Bit Name TC Initial Value 0 R/W R/W Descriptions Transfer Count Mode Specifies whether to transmit data once or for the count specified in DMATCR by one transfer request. Note that when this bit is set to 0, the TB bit must not be set to 1 (burst mode). When the SCIF or IIC3 is selected for the transfer request source, this bit (TC) must not be set to 1. 0: Transmits data once by one transfer request 1: Transmits data for the count specified in DMATCR by one transfer request 30, 29 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 368 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 28 Bit Name RLD Initial Value 0 R/W R/W Descriptions Reload Function Enable or Disable Enables or disables the reload function. 0: Disables the reload function 1: Enables the reload function 27 to 24 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 DO 0 R/W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in level detection by CHCR_0 to CHCR_3. This bit is reserved in CHCR_4 and CHCR_7; it is always read as 0 and the write value should always be 0. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1 22 TL 0 R/W Transfer End Level Specifies the TEND signal output is high active or low active. This bit is valid only in CHCR_0 and CHCR_1. This bit is reserved in CHCR_2 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: Low-active output from TEND 1: High-active output from TEND 21, 20 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 369 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 19 Bit Name HE Initial Value 0 R/W Descriptions R/(W)* Half-End Flag This bit is set to 1 when the transfer count reaches half of the DMATCR value that was specified before transfer starts. If DMA transfer ends because of an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR before the transfer count reaches half of the initial DMATCR value, the HE bit is not set to 1. If DMA transfer ends due to an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR after the HE bit is set to 1, the bit remains set to 1. To clear the HE bit, write 0 to it after HE = 1 is read. 0: DMATCR > (DMATCR set before transfer starts)/2 during DMA transfer or after DMA transfer is terminated [Clearing condition] * Writing 0 after reading HE = 1. 1: DMATCR (DMATCR set before transfer starts)/2 18 HIE 0 R/W Half-End Interrupt Enable Specifies whether to issue an interrupt request to the CPU when the transfer count reaches half of the DMATCR value that was specified before transfer starts. When the HIE bit is set to 1, the DMAC requests an interrupt to the CPU when the HE bit becomes 1. 0: Disables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2 1: Enables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2 Rev. 3.00 Jun. 18, 2008 Page 370 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 17 Bit Name AM Initial Value 0 R/W R/W Descriptions Acknowledge Mode Specifies whether DACK and TEND are output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK and TEND are always output regardless of the specification by this bit. This bit is valid only in CHCR_0 to CHCR_3. This bit is reserved in CHCR_4 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: DACK and TEND are outputs in read cycle (dual address mode) 1: DACK and TEND are outputs in write cycle (dual address mode) 16 AL 0 R/W Acknowledge Level Specifies the DACK (acknowledge) signal output is high active or low active. This bit is valid only in CHCR_0 to CHCR_3. This bit is reserved in CHCR_4 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: Low-active output from DACK 1: High-active output from DACK Rev. 3.00 Jun. 18, 2008 Page 371 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 15,14 Bit Name DM[1:0] Initial Value 00 R/W R/W Descriptions Destination Address Mode These bits select whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address (Setting prohibited in 16byte transfer) 01: Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Destination address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer, setting prohibited in 16-byte transfer) 11: Setting prohibited 13, 12 SM[1:0] 00 R/W Source Address Mode These bits select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address (Setting prohibited in 16byte-unit transfer) 01: Source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte-unit transfer) 10: Source address is decremented (-1 in byte-unit transfer, -2 in word-unit transfer, -4 in longwordunit transfer, setting prohibited in 16-byte-unit transfer) 11: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 372 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 11 to 8 Bit Name RS[3:0] Initial Value 0000 R/W R/W Descriptions Resource Select These bits specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state when DMA enable bit (DE) is set to 0. 0000: External request, dual address mode 0001: Setting prohibited 0010: External request/single address mode External address space External device with DACK 0011: External request/single address mode External device with DACK External address space 0100: Auto request 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1000: DMA extension resource selector 1001: Setting prohibited 1010: Setting prohibited 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Note: External request specification is valid only in CHCR_0 to CHCR_3. If a request source is selected in channels CHCR_4 to CHCR_7, no operation will be performed. Rev. 3.00 Jun. 18, 2008 Page 373 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 7 6 Bit Name DL DS Initial Value 0 0 R/W R/W R/W Descriptions DREQ Level DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0 to CHCR_3. These bits are reserved in CHCR_4 to CHCR_7; they are always read as 0 and the write value should always be 0. If the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, the specification by these bits is ignored. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge 5 TB 0 R/W Transfer Bus Mode Specifies the bus mode when DMA transfers data. Note that the burst mode must not be selected when TC = 0. 0: Cycle steal mode 1: Burst mode 4, 3 TS[1:0] 00 R/W Transfer Size These bits specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte unit 01: Word unit (two bytes) 10: Longword unit (four bytes) 11: 16-byte (four longword) unit 2 IE 0 R/W Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Disables an interrupt request 1: Enables an interrupt request Rev. 3.00 Jun. 18, 2008 Page 374 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 1 Bit Name TE Initial Value 0 R/W Descriptions R/(W)* Transfer End Flag This bit is set to 1 when DMATCR becomes 0 and DMA transfer ends. The TE bit is not set to 1 in the following cases. * * DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes 0. DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register (DMAOR). To clear the TE bit, write 0 after reading TE = 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been terminated [Clearing condition] * Writing 0 after reading TE = 1 1: DMA transfer ends by the specified count (DMATCR = 0) 0 DE 0 R/W DMA Enable Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this case, all of the bits TE, NMIF in DMAOR, and AE must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0 as in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Only 0 can be written to clear the flag after 1 is read. Rev. 3.00 Jun. 18, 2008 Page 375 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.5 DMA Reload Source Address Registers (RSAR) The DMA reload source address registers (RSAR) are 32-bit readable/writable registers. When the reload function is enabled, the RSAR value is written to the source address register (SAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RSAR during the current DMA transfer. When the reload function is disabled, RSAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. RSAR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 376 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.6 DMA Reload Destination Address Registers (RDAR) The DMA reload destination address registers (RDAR) are 32-bit readable/writable registers. When the reload function is enabled, the RDAR value is written to the destination address register (DAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDAR during the current DMA transfer. When the reload function is disabled, RDAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. RDAR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 377 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.7 DMA Reload Transfer Count Registers (RDMATCR) The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers. When the reload function is enabled, the RDMATCR value is written to the transfer count register (DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDMATCR during the current DMA transfer. When the reload function is disabled, RDMATCR is ignored. The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0. As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. RDMATCR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 378 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.8 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register also shows the DMA transfer status. DMAOR is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. Bit: 15 - 14 - 13 12 11 - 10 - 9 8 PR[1:0] 7 - 6 - 5 - 4 - 3 - 2 AE 1 NMIF 0 DME CMS[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)* R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 CMS[1:0] 00 R/W Cycle Steal Mode Select These bits select either normal mode or intermittent mode in cycle steal mode. It is necessary that the bus modes of all channels be set to cycle steal mode to make the intermittent mode valid. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer for every 16 cycles of B clock. 11: Intermittent mode 64 Executes one DMA transfer for every 64 cycles of B clock. 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 379 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 9, 8 Bit Name PR[1:0] Initial Value 00 R/W R/W Description Priority Mode These bits select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 01: Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7 10: Setting prohibited 11: Round-robin mode (only supported in CH0 to CH3) 7 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 AE 0 R/(W)* Address Error Flag Indicates whether an address error has occurred by the DMAC. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. 0: No DMAC address error 1: DMAC address error occurred [Clearing condition] * Writing 0 after reading AE = 1 1 NMIF 0 R/(W)* NMI Flag Indicates that an NMI interrupt occurred. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. Even if the NMI interrupt is input while the DMAC is not in operation, the NMIF bit is set to 1. 0: No NMI interrupt 1: NMI interrupt occurred [Clearing condition] * Writing 0 after reading NMIF = 1 Rev. 3.00 Jun. 18, 2008 Page 380 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Bit 0 Bit Name DME Initial Value 0 R/W R/W Description DMA Master Enable Enables or disables DMA transfer on all channels. If the DME bit and DE bit in CHCR are set to 1, DMA transfer is enabled. However, transfer is enabled only when the TE bit in CHCR of the transfer corresponding channel, the NMIF bit in DMAOR, and the AE bit are all cleared to 0. Clearing the DME bit to 0 can terminate the DMA transfer on all channels. 0: DMA transfer is disabled on all channels 1: DMA transfer is enabled on all channels Note: * Only 0 can be written to clear the flag after 1 is read. If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If fixed mode 2 is specified, the channel priority is specified as CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If the round-robin mode is specified, the transfer end channel is reset. Table 9.3 show the priority change in each mode (modes 0 to 2) specified by the priority mode bits. In each priority mode, the channel priority to accept the next transfer request may change in up to three ways according to the transfer end channel. For example, when the transfer end channel is channel 1, the priority of the channel to accept the next transfer request is specified as CH2 > CH3 > CH0 >CH1 > CH4 > CH5 > CH6 > CH7. When the transfer end channel is any one of the channels 4 to 7, round-robin will not be applied and the priority level is not changed at the end of transfer in the channels 4 to 7. The DMAC internal operation for an address error is as follows: * No address error: Read (source to DMAC) Write (DMAC to destination) * Address error in source address: Nop Nop * Address error in destination address: Read Nop Rev. 3.00 Jun. 18, 2008 Page 381 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Table 9.3 Combinations of Priority Mode Bits Transfer End Priority Mode Bits PR[1] 0 PR[0] 0 High 0 CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 Priority Level at the End of Transfer Low 7 CH7 Mode Mode 0 (fixed mode 1) Mode 1 (fixed mode 2) Mode 2 (round-robin mode) CH No. Any channel Any channel CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 0 1 CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CH1 CH2 CH3 CH0 CH0 CH0 CH0 CH0 CH2 CH3 CH0 CH1 CH1 CH1 CH1 CH1 CH3 CH0 CH1 CH2 CH2 CH2 CH2 CH2 CH0 CH1 CH2 CH3 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4 CH4 CH4 CH4 CH4 CH5 CH5 CH5 CH5 CH5 CH5 CH5 CH5 CH6 CH6 CH6 CH6 CH6 CH6 CH6 CH6 CH7 CH7 CH7 CH7 CH7 CH7 CH7 CH7 Rev. 3.00 Jun. 18, 2008 Page 382 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3) The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0 is for channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4 and 5, and DMARS3 is for channels 6 and 7. Table 9.4 shows the specifiable combinations. DMARS can specify transfer requests from eight SCIF sources, two IIC3 sources, two A/D converter sources, five MTU2 sources, and two CMT sources. DMARS is initialized to H'00000000 by a power-on reset and retains the value in manual reset, software standby mode, and module standby mode. * DMARS0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1 MID[5:0] CH1 RID[1:0] CH0 MID[5:0] CH0 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * DMARS1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3 MID[5:0] CH3 RID[1:0] CH2 MID[5:0] CH2 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * DMARS2 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH5 MID[5:0] CH5 RID[1:0] CH4 MID[5:0] CH4 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * DMARS3 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH7 MID[5:0] CH7 RID[1:0] CH6 MID[5:0] CH6 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Transfer requests from the various modules specify MID and RID as shown in table 9.4. Rev. 3.00 Jun. 18, 2008 Page 383 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Table 9.4 DMARS Settings Setting Value for One Channel ({MID, RID}) H'81 H'82 MID B'100000 RID B'01 B'10 B'100001 B'01 B'10 B'100010 B'01 B'10 B'100011 B'01 B'10 B'101000 B'01 B'10 B'101100 B'101101 B'111000 B'111001 B'111010 B'111011 B'111100 B'111110 B'111111 B'11 B'11 B'11 B'11 B'11 B'11 B'11 B'11 B'11 Function Transmit Receive Transmit Receive Transmit Receive Transmit Receive Transmit Receive Peripheral Module SCIF_0 SCIF_1 H'85 H'86 SCIF_2 H'89 H'8A SCIF_3 H'8D H'8E IIC3 H'A1 H'A2 A/D converter_0 A/D converter_1 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 CMT_0 CMT_1 H'B3 H'B7 H'E3 H'E7 H'EB H'EF H'F3 H'FB H'FF When MID or RID other than the values listed in table 9.4 is set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set, the transfer request source is not accepted. Rev. 3.00 Jun. 18, 2008 Page 384 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In bus mode, the burst mode or the cycle steal mode can be selected. 9.4.1 Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), and DMA extension resource selector (DMARS) are set for the target transfer conditions, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1. 4. When transfer has been completed for the specified count (when DMATCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. Figure 9.2 is a flowchart of this procedure. Rev. 3.00 Jun. 18, 2008 Page 385 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? Yes No Transfer request occurs?*1 Yes Transfer (one transfer unit); DMATCR - 1 DMATCR, SAR and DAR updated No *2 Bus mode, transfer request mode, DREQ detection system *3 DMATCR = 0? Yes No No DMATCR=1/2 ? TE = 1 Yes HE=1 DEI interrupt request (when IE = 1) When reload function is enabled, RSAR SAR, RDAR DAR, and RDMATCR DMATCR For a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer end Normal end HEI interrupt request (when HE = 1) When the TC bit in CHCR is 0, or for a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. No NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer terminated No Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the DE and DME bits are set to 1. 2. DREQ level detection in burst mode (external request) or cycle steal mode. 3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode. Figure 9.2 DMA Transfer Flowchart Rev. 3.00 Jun. 18, 2008 Page 386 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated in external devices and on-chip peripheral modules that are neither the transfer source nor destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_7 and DMARS0 to DMARS3. (1) Auto-Request Mode When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR_0 to CHCR_7 and the DME bit in DMAOR are set to 1, the transfer begins so long as the TE bits in CHCR_0 to CHCR_7, and the AE and NMIF bits in DMAOR are 0. (2) External Request Mode In this mode a transfer is performed at the request signals (DREQ0 to DREQ3) of an external device. Choose one of the modes shown in table 9.5 according to the application system. When the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), DMA transfer is performed upon a request at the DREQ input. Table 9.5 Selecting External Request Modes with the RS Bits Transfer Source Any Transfer Destination Any External device with DACK External memory, memory-mapped external device RS[3] RS[2] RS[1] RS[0] Address Mode 0 0 0 0 0 1 0 0 Dual address mode Single address mode External memory, memory-mapped external device External device with DACK 1 Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in CHCR_0 to CHCR_3 as shown in table 9.6. The source of the transfer request does not have to be the data transfer source or destination. Rev. 3.00 Jun. 18, 2008 Page 387 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Table 9.6 Selecting External Request Detection with DL and DS Bits CHCR DL bit 0 DS bit 0 1 Detection of External Request Low level detection Falling edge detection High level detection Rising edge detection 1 0 1 When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again enters the request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. Overrun 0: Transfer is terminated after the same number of transfer has been performed as requests. Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 9.7 CHCR DO bit 0 1 External Request Overrun 0 Overrun 1 Selecting External Request Detection with DO Bit Rev. 3.00 Jun. 18, 2008 Page 388 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) (3) On-Chip Peripheral Module Request In this mode, the transfer is performed in response to the DMA transfer request signal from an onchip peripheral module. Signals that request DMA transfer from on-chip peripheral modules include transmit FIFO data empty and receive FIFO data full from the SCIF, transmit data empty and receive data full from the IIC3, A/D conversion end transfer requests from the A/D converter, input capture/compare match from the MTU2, and compare match from the CMT. When a transfer request signal is sent in on-chip peripheral module request mode while DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, and NMIF = 0), DMA transfer is performed. When the transmit FIFO data empty from the SCIF is selected, specify the transfer destination as the corresponding SCIF transmit FIFO data register. Likewise, when the receive FIFO data full from the SCIF is selected, specify the transfer source as the corresponding SCIF receive FIFO data register. When the transmit data empty from IIC3 is selected as the transfer request, the transfer destination must be ICDRT; when the receive data full from IIC3 is selected as the transfer request, the transfer source must be ICDRR. When a transfer request is set to the end of A/D conversion by the A/D converter, the transfer source must be the A/D data register (ADDR). Any address can be specified for data transfer source and destination when a transfer request is set to an input capture/compare match from the MTU2 or compare match from the CMT. Rev. 3.00 Jun. 18, 2008 Page 389 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Table 9.8 CHCR Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits DMARS DMA Transfer Request RID Source DMA Transfer Request Signal Transfer Source Transfer Bus Destination Mode SCFTDR_0 Cycle steal SCFTDR_1 RS[3:0] MID 1000 100000 01 10 100001 01 10 100010 01 10 100011 01 10 101000 01 10 101100 11 101101 11 111000 11 111001 11 111010 11 111011 11 111100 11 111110 11 111111 11 SCIF_0 transmit TXI0 (transmit FIFO data empty) Any SCIF_0 receive RXI0 (receive FIFO data full) SCFRDR_0 Any SCIF_1 transmit TXI1 (transmit FIFO data empty) Any SCIF_1 receive RXI1 (receive FIFO data full) SCFRDR_1 Any SCFTDR_2 SCIF_2 transmit TXI2 (transmit FIFO data empty) Any SCIF_2 receive RXI2 (receive FIFO data full) SCFRDR_2 Any SCFTDR_3 SCIF_3 transmit TXI3 (transmit FIFO data empty) Any SCIF_3 receive IIC3 transmit IIC3 receive RXI3 (receive FIFO data full) TXI (transmit data empty) RXI (receive data full) SCFRDR_3 Any Any ICDRR ADDR0 ADDR1 Any Any Any Any Any Any Any ICDRT Any Any Any Any Any Any Any Any Any Any Cycle steal or burst Cycle steal Cycle steal Cycle steal or burst A/D converter_0 ADI0 (A/D conversion end) A/D converter_1 ADI1 (A/D conversion end) MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 CMT_0 CMT_1 TGI0A (input capture/compare match) TGI1A (input capture/compare match) TGI2A (input capture/compare match) TGI3A (input capture/compare match) TGI4A (input capture/compare match) CMI0 (compare match) CMI1 (compare match) Rev. 3.00 Jun. 18, 2008 Page 390 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.4.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Three modes (fixed mode 1, fixed mode 2, and round-robin mode) are selected using the PR1 and PR0 bits in DMAOR. (1) Fixed Mode In fixed modes, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7 These are selected by the PR1 and PR0 bits in the DMA operation register (DMAOR). (2) Round-Robin Mode Each time one unit of word, byte, longword, or 16 bytes is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished is rotated to the lowest of the priority order among the four round-robin channels (channels 0 to 4). The priority of the channels other than the round-robin channels (channels 0 to 4) does not change even in round-robin mode. The round-robin mode operation is shown in figure 9.3. The priority in round-robin mode is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 immediately after a reset. When the round-robin mode has been specified, do not concurrently specify cycle steal mode and burst mode as the bus modes of any two or more channels. Rev. 3.00 Jun. 18, 2008 Page 391 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Channel 0 is given the lowest priority among the round-robin channels. Priority order after transfer CH1 > CH2 > CH3 > CH0 > CH4 > CH5 > CH6 > CH7 (2) When channel 1 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Channel 1 is given the lowest priority among the round-robin channels. The priority of channel 0, which was higher than channel 1, is also shifted. Priority order after transfer CH2 > CH3 > CH0 > CH1 > CH4 > CH5 > CH6 > CH7 (3) When channel 2 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Priority order after transfer CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7 Channel 2 is given the lowest priority among the round-robin channels. The priority of channels 0 and 1, which were higher than channel 2, is also shifted. If there is a transfer request only to channel 5 immediately after that, the priority does not change because channel 5 is not a round-robin channel. Post-transfer priority order when there is an immediate transfer request to channel 5 only CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7 (4) When channel 7 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Priority order does not change. Priority order after transfer CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Figure 9.3 Round-Robin Mode Rev. 3.00 Jun. 18, 2008 Page 392 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Figure 9.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 is given the lowest priority among the round-robin channels. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 is given the lowest priority among the round-robin channels. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 are lowered in priority so that channel 3 is given the lowest priority among the round-robin channels. Transfer request Waiting channel(s) DMAC operation Channel priority 0>1>2>3>4>5>6>7 (1) Channels 0 and 3 (2) Channel 0 transfer start (3) Channel 1 3 Priority order changes 1, 3 (4) Channel 0 transfer ends 1>2>3>0>4>5>6>7 (5) Channel 1 transfer starts Priority order changes 3 (6) Channel 1 transfer ends 2>3>0>1>4>5>6>7 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 0>1>2>3>4>5>6>7 Figure 9.4 Changes in Channel Priority in Round-Robin Mode Rev. 3.00 Jun. 18, 2008 Page 393 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to the transfer source and destination. A data transfer timing depends on the bus mode, which is the cycle steal mode or burst mode. The DMAC supports the transfers shown in table 9.9. Table 9.9 Supported DMA Transfers Transfer Destination Transfer Source External device with DACK External memory Memory-mapped external device On-chip peripheral module On-chip memory External Device with DACK Not available Dual, single Dual, single Not available Not available External Memory Dual, single Dual Dual Dual Dual Memory-Mapped External Device Dual, single Dual Dual Dual Dual On-Chip On-Chip Peripheral Module Memory Not available Dual Dual Dual Dual Not available Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is available only for on-chip peripheral modules that support longword access. Rev. 3.00 Jun. 18, 2008 Page 394 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) (1) (a) Address Modes Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selected) by an address. The transfer source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 9.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a data write cycle. DMAC SAR Memory Address bus DAR Data bus Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is tempolarily stored in the DMAC. First bus cycle DMAC SAR Memory Address bus DAR Data bus Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle Figure 9.5 Data Flow of Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. Figure 9.6 shows an example of DMA transfer timing in dual address mode. Rev. 3.00 Jun. 18, 2008 Page 395 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) CKIO A25 to A0 Transfer source address Transfer destination address CSn D31 to D0 RD WEn DACKn (Active-low) Data read cycle (1st cycle) Data write cycle (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 9.6 Example of DMA Transfer Timing in Dual Mode (Transfer Source: Normal Memory, Transfer Destination: Normal Memory) Rev. 3.00 Jun. 18, 2008 Page 396 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) (b) Single Address Mode In single address mode, both the transfer source and destination are external devices, either of them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 9.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus This LSI DMAC External memory External data bus External device with DACK DACK DREQ Data flow (from memory to device) Data flow (from device to memory) Figure 9.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Figure 9.8 shows an example of DMA transfer timing in single address mode. Rev. 3.00 Jun. 18, 2008 Page 397 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) CK A25 to A0 CSn WEn D31 to D0 DACKn Address output to external memory space Select signal to external memory space Write strobe signal to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK External memory space (normal memory) CK A25 to A0 CSn RD D31 to D0 DACKn Address output to external memory space Select signal to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space (normal memory) External device with DACK Figure 9.8 Example of DMA Transfer Timing in Single Address Mode (2) Bus Modes There are two bus modes; cycle steal and burst. Select the mode by the TB bits in the channel control registers (CHCR). (a) Cycle Steal Mode * Normal mode In normal mode of cycle steal, the bus mastership is given to another bus master after a onetransfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer request occurs, the bus mastership is obtained from another bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is repeated until the transfer end conditions are satisfied. The cycle-steal normal mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. Figure 9.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer conditions shown in the figure are; Dual address mode DREQ low level detection Rev. 3.00 Jun. 18, 2008 Page 398 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU Read/Write Figure 9.9 DMA Transfer Example in Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection) * Intermittent Mode 16 and Intermittent Mode 64 In intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next transfer request occurs after that, DMAC obtains the bus mastership from other bus master after waiting for 16 or 64 cycles of B clock. DMAC then transfers data of one unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of cycle steal. When DMAC obtains again the bus mastership, DMA transfer may be postponed in case of entry updating due to cache miss. The cycle-steal intermittent mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in all channels. Figure 9.10 shows an example of DMA transfer timing in cycle-steal intermittent mode. Transfer conditions shown in the figure are; Dual address mode DREQ low level detection DREQ More than 16 or 64 B clock cycles (depends on the CPU's condition of using bus) Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU CPU DMAC DMAC Read/Write CPU Figure 9.10 Example of DMA Transfer in Cycle-Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) Rev. 3.00 Jun. 18, 2008 Page 399 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) (b) Burst Mode In burst mode, once the DMAC obtains the bus mastership, it does not release the bus mastership and continues to perform transfer until the transfer end condition is satisfied. In external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus mastership is passed to another bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. Figure 9.11 shows DMA transfer timing in burst mode. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC Read Write Read Write CPU CPU Figure 9.11 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection) (3) Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 9.10 shows the relationship between request modes and bus modes by DMA transfer category. Rev. 3.00 Jun. 18, 2008 Page 400 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Table 9.10 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Dual External device with DACK and external memory External device with DACK and memory-mapped external device External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memorymapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module Request Mode External External All* All* All* All* All* 4 4 Bus Mode B/C B/C B/C B/C B/C B/C* B/C* B/C* B/C B/C B/C* B/C B/C B/C 5 5 5 Transfer Size (Bits) 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128* 8/16/32/128* 8/16/32/128* 8/16/32/128 8/16/32/128 8/16/32/128* 8/16/32/128 8/16/32/128 8/16/32/128 2 2 2 Usable Channels 0 to 3 0 to 3 0 to 7* 0 to 7* 0 to 7* 3 3 4 3 1 1 0 to 7* 0 to 7* 0 to 7* 0 to 7* 0 to 7* 3 3 On-chip peripheral module and on-chip peripheral All* module On-chip memory and on-chip memory On-chip memory and memory-mapped external device On-chip memory and on-chip peripheral module On-chip memory and external memory Single External device with DACK and external memory External device with DACK and memory-mapped external device All* All* All* All* 1 5 2 3 4 4 3 3 1 4 0 to 7* 0 to 7* 0 to 3 0 to 3 3 3 External External [Legend] B: Burst C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. However, in the case of internal module request, along with the exception of MTU2 and CMT as the transfer request source, the requesting module must be designated as the transfer source or the transfer destination. 2. Access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 3. If the transfer request is an external request, channels 0 to 3 are only available. 4. External requests, auto requests, and on-chip peripheral module requests are all available. In the case of on-chip peripheral module requests, however, the CMT and MTU2 are only available. 5. In the case of internal module request, only cycle steal except for the MTU2 and CMT as the transfer request source. Rev. 3.00 Jun. 18, 2008 Page 401 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) (4) Bus Mode and Channel Priority In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer on channel 1 will only resume on completion of the transfer on channel 0. When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1, channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of this is shown in figure 9.12. When multiple channels are in burst mode, data transfer on the channel that has the highest priority is given precedence. When DMA transfer is being performed on multiple channels, the bus mastership is not released to another bus-master device until all of the competing burst-mode transfers have been completed. CPU DMA CH1 DMA CH1 DMA CH0 CH0 DMA CH1 CH1 DMA CH0 CH0 DMA CH1 DMA CH1 CPU CPU DMAC CH1 Burst mode DMAC CH0 and CH1 Cycle steal mode DMAC CH1 Burst mode CPU Priority: CH0 > CH1 CH0: Cycle steal mode CH1: Burst mode Figure 9.12 Bus State when Multiple Channels are Operating In round-robin mode, the priority changes as shown in figure 9.3. Note that channels in cycle steal and burst modes must not be mixed. Rev. 3.00 Jun. 18, 2008 Page 402 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.4.5 (1) Number of Bus Cycles and DREQ Pin Sampling Timing Number of Bus Cycles When the DMAC is the bus master, the number of bus cycles is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 8, Bus State Controller (BSC). (2) DREQ Pin Sampling Timing Figures 9.13 to 9.16 show the DREQ input sampling timings in each bus mode. CKIO Bus cycle DREQ (Rising) DACK (Active-high) Acceptance start CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Figure 9.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC 2nd acceptance CPU Acceptance start Figure 9.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection Rev. 3.00 Jun. 18, 2008 Page 403 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising) DACK (Active-high) CPU Burst acceptance Non sensitive period CPU DMAC DMAC Figure 9.15 Example of DREQ Input Detection in Burst Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) Acceptance start CPU 1st acceptance CPU DMAC 2nd acceptance Non sensitive period CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Acceptance start Acceptance start CPU 1st acceptance CPU DMAC 2nd acceptance DMAC 3rd acceptance Non sensitive period Figure 9.16 Example of DREQ Input Detection in Burst Mode Level Detection Rev. 3.00 Jun. 18, 2008 Page 404 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Figure 9.17 shows the TEND output timing. CKIO End of DMA transfer Bus cycle DREQ DACK TEND DMAC CPU DMAC CPU CPU Figure 9.17 Example of DMA Transfer End Signal Timing (Cycle Steal Mode Level Detection) The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for an 8-bit or 16-bit external device, or when word access is performed for an 8-bit external device. When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS signal for data alignment as shown in figure 9.18. Also, the DREQ sampling may not be detected correctly with divided DACK, and one extra overrun may occur at maximum. Use a setting that does not divide DACK or specify a transfer size smaller than the external device bus width if DACK is divided. Rev. 3.00 Jun. 18, 2008 Page 405 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) T1 CKIO Address CS RD Data WEn DACKn (Active low) TEND (Active low) WAIT T2 Taw T1 T2 Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit is divided into multiple bus cycles and the CS is negated between the bus cycles, TEND is also divided. Figure 9.18 BSC Normal Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) Rev. 3.00 Jun. 18, 2008 Page 406 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) 9.5 9.5.1 Usage Notes Setting of the Half-End Flag and Generation of the Half-End Interrupt When executing DMA transfer by reload function of DMAC, setting different value to DMA reload transfer count register (RDMATCR_n) from the DMA transfer count register (DMATCR_n) value set when transfer is started lead to an error in the operation of the half end flag of DMA channel control register (CHCR_n). Even though the value of DMATCR_n is rewritten by reload operation, half end flag is set based on the value set when transfer is started. Because of this, there may be errors where (a) the set timing of the half end flag is not correct, or (b) the half end flag can not be set, may be generated. When executing DMA transfer by reload function under the condition that different values are set to RDMATCR_n from DMATCR_n, do not use half end flag or half end interrupt. 9.5.2 Timing of DACK and TEND Outputs When the external memory is the MPX-I/O or burst MPX-I/O, the DACK output is asserted with the timing of the data cycle. For details, see the respective figures in section 8.5.5, MPX-I/O Interface, or section 8.5.10, Burst MPX-I/O Interface. When the memory is other than the MPX-I/O or burst MPX-I/O, the DACK output is asserted with the same timing as the corresponding CS signal. The TEND output does not depend on the type of memory and is always asserted with the same timing as the corresponding CS signal. 9.5.3 DREQ Sampling There are cases that when DACK is split for an external access, DREQ can be sampled twice in that access. When DACK is split for an external access as following. (1) * * * * In case that bus width and access size are one of the following four cases 16 byte access 32 bit access for 8 bit space 16 bit access for 8 bit space 32 bit access for 16 bit space Rev. 3.00 Jun. 18, 2008 Page 407 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) (2) and, in case that the setting is one of the following three cases * Write-Write cycles (IWW[2:0]) >=001 * Read-Read cycles in the same spaces (IWRRS[2:0]) >=001 * External Wait Mask Specification (WM) =0 In addition to above condition, DREQ sampling and access type is one of the following two cases, DREQ can be sampled twice. * For DREQ level detection: only write access * For DREQ edge detection: both write access and read access Figures 9.19 to 9.22 show DREQ sampling timing for above access. For the external access as shown above conditions, please use one of the following three ways. * For DREQ edge detection: please input one DREQ edge at maximum in that external access. * For DREQ level detection in overrun 0: please negate DREQ after the detection of the first DACK negation and before the second DACK negation. * For DREQ level detection in overrun 1: please negate DREQ after the detection of the first DACK assertion and before the second DACK assertion. Rev. 3.00 Jun. 18, 2008 Page 408 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) CKIO Bus cycle CPU 1st acceptance 2nd acceptance DMAC Write or Read DREQ (Rising) Non sensitive period DACK (Active-high) Non sensitive period 3rd acceptance possible Figure 9.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection when DACK is Split to 4 Due to Idia Cycles CKIO Bus cycle CPU 1st acceptance DMAC Write or Read 2nd acceptance 3rd acceptance is after the next DACK assertion DREQ (Rising) Non sensitive period DACK (Active-high) Non sensitive period Figure 9.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection when DACK is Split to 2 Due to Idia Cycles Rev. 3.00 Jun. 18, 2008 Page 409 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) CKIO Bus cycle CPU 1st acceptance DMAC Write 2nd acceptance Non sensitive period 3rd acceptance possible DREQ (Overrun 0 at high level) DACK (Active-high) Non sensitive period CKIO Bus cycle CPU 1st acceptance 2nd acceptance Non sensitive period DMAC Write 3rd acceptance possible DREQ (Overrun 1 at high level) DACK (Active-high) Non sensitive period Figure 9.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection when DACK is Split to 4 Due to Idia Cycles Rev. 3.00 Jun. 18, 2008 Page 410 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) CKIO Bus cycle CPU 1st acceptance DMAC Write 2nd acceptance 3rd acceptance possible DREQ (Overrun 0 at high level) DACK (Active-high) Non sensitive period Non sensitive period CKIO Bus cycle CPU 1st acceptance DMAC Write 2nd acceptance 3rd acceptance possible DREQ (Overrun 1 at high level) DACK (Active-high) Non sensitive period Non sensitive period Figure 9.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection when DACK is Split to 2 Due to Idia Cycles Rev. 3.00 Jun. 18, 2008 Page 411 of 1160 REJ09B0191-0300 Section 9 Direct Memory Access Controller (DMAC) Rev. 3.00 Jun. 18, 2008 Page 412 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels. 10.1 Features * Maximum 16 pulse input/output lines and three pulse input lines * Selection of eight counter input clocks for each channel (four clocks for channel 5) * The following operations can be set for channels 0 to 4: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 12-phase PWM output is possible in combination with synchronous operation However, waveform output by compare match for channel 5 is not possible. * Buffer operation settable for channels 0, 3, and 4 * Phase counting mode settable independently for each of channels 1 and 2 * Cascade connection operation * Fast access via internal 16-bit bus * 28 interrupt sources * Automatic transfer of register data * A/D converter start trigger can be generated * Module standby mode can be settable * A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible. * AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible. * Dead time compensation counter available in channel 5 * In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped. Rev. 3.00 Jun. 18, 2008 Page 413 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.1 MTU2 Functions Item Count clock Channel 0 P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRE_0 TGRC_0 TGRD_0 TGRF_0 TIOC0A TIOC0B TIOC0C TIOC0D TGR compare match or input capture Channel 1 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB TGRA_1 TGRB_1 -- Channel 2 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 -- Channel 3 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOC3A TIOC3B TIOC3C TIOC3D TGR compare match or input capture -- Channel 4 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4A TIOC4B TIOC4C TIOC4D TGR compare match or input capture -- Channel 5 P/1 P/4 P/16 P/64 General registers TGRU_5 TGRV_5 TGRW_5 -- General registers/ buffer registers I/O pins TIOC1A TIOC1B TIOC2A TIOC2B Input pins TIC5U TIC5V TIC5W TGR compare match or input capture -- -- -- -- -- -- -- -- -- Counter clear function TGR compare match or input capture -- -- -- TGR compare match or input capture -- -- -- Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset PWM mode AC synchronous motor drive mode -- -- Rev. 3.00 Jun. 18, 2008 Page 414 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Item Phase counting mode Buffer operation Dead time compensation counter function DMAC activation Channel 0 -- -- Channel 1 -- -- Channel 2 -- -- Channel 3 -- -- Channel 4 -- -- Channel 5 -- -- TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture and TCNT overflow or underflow TGRA_4 compare match or input capture TCNT_4 underflow (trough) in complement ary PWM mode -- A/D converter start TGRA_0 trigger compare match or input capture TGRE_0 compare match TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture -- Rev. 3.00 Jun. 18, 2008 Page 415 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Item Interrupt sources Channel 0 7 sources * Channel 1 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Channel 2 4 sources * Channel 3 5 sources Channel 4 5 sources Channel 5 3 sources Compare match or input capture 5U Compare match or input capture 5V Compare match or input capture 5W Compare * match or input capture 0A Compare * match or input capture 2A Compare * match or input capture 3A Compare * match or input capture 3B Compare * match or input capture 4A Compare * match or input capture 4B Compare * match or input capture 4C Compare match or input capture 4D * Compare * match or input capture 0B * Compare * match or input capture 2B * Compare * match or input capture 0C * * Overflow Underflow * Compare * match or input capture 3C Underflow * * Compare match or input capture 0D * Compare * match or input capture 3D * * * Compare match 0E Compare match 0F Overflow * Overflow * Overflow or underflow Rev. 3.00 Jun. 18, 2008 Page 416 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Item Channel 0 Channel 1 -- Channel 2 -- Channel 3 -- Channel 4 * A/D converter start request at a match between TADCOR A_4 and TCNT_4 * A/D converter start request at a match between TADCOR B_4 and TCNT_4 Channel 5 -- A/D converter start -- request delaying function Interrupt skipping function -- -- -- * Skips TGRA_3 compare match interrupts * Skips TCIV_4 interrupts -- [Legend] : Possible --: Not possible Rev. 3.00 Jun. 18, 2008 Page 417 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.1 shows a block diagram of the MTU2. TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Control logic for channels 3 and 4 Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 TIORH TIORL TMDR Channel 4 TSR TIER TCR TGRC TDDR TIORH TOCR TGCR TIER TCR TCNTS TCDR Channel 2 TGRA TGRB TCNT Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 External clock: TCLKA TCLKB TCLKC TCLKD Module data bus Input pins Channel 5: TIC5U TIC5V TIC5W Channel 5 TOER TCBR TCNTW TGRD TGRA TGRB TCNT Channel 5: TGIU_5 TGIV_5 TGIW_5 TCNTU TCNTV TGRW TGRU TGRV TIOR TIER TCR TSR Control logic Common TSYR Peripheral bus BUS I/F TMDR TSR TSTR A/D converter conversion start signal TIORL TMDR Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B TIORH [Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter TCDR: TCBR: TDDR: TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: TGRU: TGRV: TGRW: Timer cycle data register Timer cycle buffer register Timer dead time data register Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer general register U Timer general register V Timer general register W Figure 10.1 Block Diagram of MTU2 Rev. 3.00 Jun. 18, 2008 Page 418 of 1160 REJ09B0191-0300 TIER Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2 TIOR Control logic for channels 0 to 2 TMDR Channel 1 TSR TIER TCR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TCNT TGRD TGRA TGRB TGRE TCR TGRF TCNT Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.2 Input/Output Pins Table 10.2 Pin Configuration Channel Pin Name I/O Common TCLKA TCLKB TCLKC TCLKD 0 TIOC0A TIOC0B TIOC0C TIOC0D 1 TIOC1A TIOC1B 2 TIOC2A TIOC2B 3 TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D 5 TIC5U TIC5V TIC5W Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRC_4 input capture input/output compare output/PWM output pin TGRD_4 input capture input/output compare output/PWM output pin TGRU_5 input capture input/external pulse input pin TGRV_5 input capture input/external pulse input pin TGRW_5 input capture input/external pulse input pin Note: For the pin configuration in complementary PWM mode, see table 10.54 in section 10.4.8, Complementary PWM Mode. Rev. 3.00 Jun. 18, 2008 Page 419 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3 Register Descriptions The MTU2 has the following registers. For details on register addresses and register states during each process, refer to section 24, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 10.3 Register Descriptions Channel Register Name 0 Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer general register E_0 Timer general register F_0 Timer interrupt enable register2_0 Timer status register2_0 Timer buffer operation transfer mode register_0 1 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Abbreviation TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'00 H'00 H'00 H'00 H'00 H'C0 H'0000 Address H'FFFE4300 H'FFFE4301 H'FFFE4302 H'FFFE4303 H'FFFE4304 H'FFFE4305 H'FFFE4306 Access Size 8 8 8 8 8 8 16 16 16 H'FFFF H'FFFE4308 H'FFFF H'FFFE430A H'FFFF H'FFFE430C 16 H'FFFF H'FFFE430E H'FFFF H'FFFE4320 H'FFFF H'FFFE4322 H'00 H'C0 H'00 H'00 H'00 H'00 H'00 H'C0 H'FFFE4324 H'FFFE4325 H'FFFE4326 H'FFFE4380 H'FFFE4381 H'FFFE4382 H'FFFE4384 H'FFFE4385 16 16 16 8 8 8 8 8 8 8 8 Rev. 3.00 Jun. 18, 2008 Page 420 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Channel Register Name 1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer input capture control register 2 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 3 Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Timer buffer operation transfer mode register_3 4 Timer control register_4 Timer mode register_4 Timer I/O control register H_4 Timer I/O control register L_4 Abbreviation TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TBTM_3 TCR_4 TMDR_4 TIORH_4 TIORL_4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'0000 Address H'FFFE4386 Access Size 16 16 16 8 8 8 8 8 8 16 16 16 8 8 8 8 8 H'FFFF H'FFFE4388 H'FFFF H'FFFE438A H'00 H'00 H'00 H'00 H'00 H'C0 H'0000 H'FFFE4390 H'FFFE4000 H'FFFE4001 H'FFFE4002 H'FFFE4004 H'FFFE4005 H'FFFE4006 H'FFFF H'FFFE4008 H'FFFF H'FFFE400A H'00 H'00 H'00 H'00 H'00 H'C0 H'0000 H'FFFE4200 H'FFFE4202 H'FFFE4204 H'FFFE4205 H'FFFE4208 H'FFFE422C 8 H'FFFE4210 16 16 16 16 16 8 8 8 8 8 H'FFFF H'FFFE4218 H'FFFF H'FFFE421A H'FFFF H'FFFE4224 H'FFFF H'FFFE4226 H'00 H'00 H'00 H'00 H'00 H'FFFE4238 H'FFFE4201 H'FFFE4203 H'FFFE4206 H'FFFE4207 Rev. 3.00 Jun. 18, 2008 Page 421 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Channel Register Name 4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 Timer general register C_4 Timer general register D_4 Timer buffer operation transfer mode register_4 Timer A/D converter start request control register Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4 Timer A/D converter start request cycle set buffer register A_4 Timer A/D converter start request cycle set buffer register B_4 5 Timer control register U_5 Timer control register V_5 Timer control register W_5 Timer I/O control register U_5 Timer I/O control register V_5 Timer I/O control register W_5 Timer interrupt enable register_5 Timer status register_5 Timer start register_5 Timer counter U_5 Timer counter V_5 Abbreviation TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TBTM_4 TADCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'00 H'C0 H'0000 Address H'FFFE4209 Access Size 8 H'FFFE422D 8 H'FFFE4212 16 H'FFFF H'FFFE421C 16 H'FFFF H'FFFE421E H'FFFF H'FFFE4228 H'FFFF H'FFFE422A H'00 H'0000 H'FFFE4239 H'FFFE4240 16 16 16 8 16 16 16 16 TADCORA_4 R/W TADCORB_4 R/W TADCOBRA_4 H'FFFF H'FFFE4244 H'FFFF H'FFFE4246 H'FFFF H'FFFE4248 R/W TADCOBRB_4 R/W H'FFFF H'FFFE424A 16 TCRU_5 TCRV_5 TCRW_5 TIORU_5 TIORV_5 TIORW_5 TIER_5 TSR_5 TSTR_5 TCNTU_5 TCNTV_5 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'0000 H'FFFE4084 H'FFFE4094 H'FFFE40A4 H'FFFE4086 H'FFFE4096 H'FFFE40A6 H'FFFE40B2 H'FFFE40B0 H'FFFE40B4 H'FFFE4080 H'FFFE4090 8 8 8 8 8 8 8 8 8 16 16 Rev. 3.00 Jun. 18, 2008 Page 422 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Channel Register Name 5 Timer counter W_5 Timer general register U_5 Timer general register V_5 Timer general register W_5 Timer compare match clear register Common Timer start register Timer synchronous register Timer counter synchronous start register Timer read/write enable register Common Timer output master enable to 3 and register 4 Timer output control register 1 Timer output control register 2 Timer gate control register Timer cycle control register Timer dead time data register Timer subcounter Timer cycle buffer register Timer interrupt skipping set register Abbreviation TCNTW_5 TGRU_5 TGRV_5 TGRW_5 TCNTCMPCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W Initial value H'0000 Address H'FFFE40A0 Access Size 16 16 16 16 8 8 8 8 8 8 8 8 H'FFFF H'FFFE4082 H'FFFF H'FFFE4092 H'FFFF H'FFFE40A2 H'00 H'00 H'00 H'00 H'01 H'C0 H'00 H'00 H80 H'FFFE40B6 H'FFFE4280 H'FFFE4281 H'FFFE4282 H'FFFE4284 H'FFFE420A H'FFFE420E H'FFFE420F TSTR TSYR TCSYSTR TRWER TOER TOCR1 TOCR2 TGCR TCDR TDDR TCNTS TCBR TITCR H'FFFE420D 8 16 16 16 16 8 8 8 8 8 8 8 H'FFFF H'FFFE4214 H'FFFF H'FFFE4216 H'0000 H'FFFE4220 H'FFFF H'FFFE4222 H'00 H'00 H'00 H'01 H'00 H'00 H'00 H'FFFE4230 H'FFFE4231 H'FFFE4232 H'FFFE4234 H'FFFE4250 H'FFFE4260 H'FFFE4236 Timer interrupt skipping counter TITCNT Timer buffer transfer set register Timer dead time enable register Timer synchronous clear register TBTER TDER TSYCR Timer waveform control register TWCR Timer output level buffer register TOLBR Rev. 3.00 Jun. 18, 2008 Page 423 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted only when TCNT operation is stopped. Bit: 7 6 CCLR[2:0] 5 4 3 2 1 TPSC[2:0] 0 CKEG[1:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 5 Bit Name CCLR[2:0] Initial Value 000 R/W R/W Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 10.4 and 10.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. When P/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.6 to 10.9 for details. [Legend] x: Don't care Rev. 3.00 Jun. 18, 2008 Page 424 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Channel 0, 3, 4 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 1 0 0 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 10.5 CCLR0 to CCLR2 (Channels 1 and 2) Channel 1, 2 Bit 7 Bit 6 Reserved*2 CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 425 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.6 TPSC0 to TPSC2 (Channel 0) Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 10.7 TPSC0 to TPSC2 (Channel 1) Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT_2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 3.00 Jun. 18, 2008 Page 426 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.8 TPSC0 to TPSC2 (Channel 2) Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 10.9 TPSC0 to TPSC2 (Channels 3 and 4) Channel 3, 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 Internal clock: counts on P/256 Internal clock: counts on P/1024 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Rev. 3.00 Jun. 18, 2008 Page 427 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.10 TPSC1 and TPSC0 (Channel 5) Channel 5 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value should always be 0. 10.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: 7 - 6 BFE 5 BFB 4 BFA 3 2 1 0 MD[3:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 BFE 0 R/W Buffer Operation E Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. TGRF compare match is generated when TGRF is used as the buffer register. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation Rev. 3.00 Jun. 18, 2008 Page 428 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name BFB Initial Value 0 R/W R/W Description Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated in a mode other than complementary PWM. TGRD compare match is generated in complementary PWM mode. When compare match occurs during the Tb period in complementary PWM mode, TGRD is set. Therefore, set the TGIED bit in the timer interrupt enable register 3/4 (TIER_3/4) to 0. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated in a mode other than complementary PWM. TGRC compare match is generated when in complementary PWM mode. When compare match for channel 4 occurs during the Tb period in complementary PWM mode, TGFC is set. Therefore, set the TGIEC bit in the timer interrupt enable register 4 (TIER_4) to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 10.11 for details. Rev. 3.00 Jun. 18, 2008 Page 429 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 0 X 0 1 1 0 1 Description Normal operation Setting prohibited PWM mode 1 PWM mode 2*1 Phase counting mode 1*2 Phase counting mode 2*2 Phase counting mode 3*2 Phase counting mode 4*2 Reset synchronous PWM mode*3 Setting prohibited Setting prohibited Setting prohibited Complementary PWM mode 1 (transmit at crest)*3 Complementary PWM mode 2 (transmit at trough)*3 Complementary PWM mode 2 (transmit at crest and trough)*3 [Legend] X: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2. Rev. 3.00 Jun. 18, 2008 Page 430 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5. TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: 7 6 5 4 3 2 1 0 IOB[3:0] IOA[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 4 Bit Name IOB[3:0] Initial Value 0000 R/W R/W Description I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 10.12 Table 10.14 Table 10.15 Table 10.16 Table 10.18 3 to 0 IOA[3:0] 0000 R/W I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 10.20 Table 10.22 Table 10.23 Table 10.24 Table 10.26 Rev. 3.00 Jun. 18, 2008 Page 431 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TIORL_0, TIORL_3, TIORL_4 Bit: 7 6 5 4 3 2 1 0 IOD[3:0] IOC[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 4 Bit Name IOD[3:0] Initial Value 0000 R/W R/W Description I/O Control D0 to D3 Specify the function of TGRD. See the following tables. TIORL_0: Table 10.13 TIORL_3: Table 10.17 TIORL_4: Table 10.19 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 10.21 TIORL_3: Table 10.25 TIORL_4: Table 10.27 * TIORU_5, TIORV_5, TIORW_5 Bit: 7 - 6 - 5 - 4 3 2 IOC[4:0] 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IOC[4:0] 00000 R/W I/O Control C0 to C4 Specify the function of TGRU_5, TGRV_5, and TGRW_5. For details, see table 10.28. Rev. 3.00 Jun. 18, 2008 Page 432 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.12 TIORH_0 (Channel 0) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_0 Function Output compare register TIOC0B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 433 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.13 TIORL_0 (Channel 0) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRD_0 Function Output compare register*2 TIOC0D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Jun. 18, 2008 Page 434 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.14 TIOR_1 (Channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_1 Function Output compare register TIOC1B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 435 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.15 TIOR_2 (Channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_2 Function Output compare register TIOC2B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 436 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.16 TIORH_3 (Channel 3) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_3 Function Output compare register TIOC3B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 437 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.17 TIORL_3 (Channel 3) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRD_3 Function Output compare 2 register* TIOC3D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Jun. 18, 2008 Page 438 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.18 TIORH_4 (Channel 4) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_4 Function Output compare register TIOC4B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 439 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.19 TIORL_4 (Channel 4) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRD_4 Function Output compare 2 register* TIOC4D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Jun. 18, 2008 Page 440 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.20 TIORH_0 (Channel 0) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_0 Function Output compare register TIOC0A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 441 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.21 TIORL_0 (Channel 0) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRC_0 Function Output compare 2 register* TIOC0C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge 2 register* Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Jun. 18, 2008 Page 442 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.22 TIOR_1 (Channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_1 Function Output compare register TIOC1A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 443 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.23 TIOR_2 (Channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_2 Function Output compare register TIOC2A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 444 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.24 TIORH_3 (Channel 3) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_3 Function Output compare register TIOC3A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 445 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.25 TIORL_3 (Channel 3) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRC_3 Function Output compare 2 register* TIOC3C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Jun. 18, 2008 Page 446 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.26 TIORH_4 (Channel 4) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_4 Function Output compare register TIOC4A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 3.00 Jun. 18, 2008 Page 447 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.27 TIORL_4 (Channel 4) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRC_4 Function Output compare 2 register* TIOC4C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Jun. 18, 2008 Page 448 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) Description TGRU_5, TGRV_5, and TGRW_5 TIC5U, TIC5V, and TIC5W Pin Function Function Compare Compare match match register Setting prohibited Setting prohibited Setting prohibited Setting prohibited Input capture register Setting prohibited Input capture at rising edge Input capture at falling edge Input capture at both edges Setting prohibited Setting prohibited Measurement of low pulse width of external input signal Capture at trough 1 0 Measurement of low pulse width of external input signal Capture at crest 1 Measurement of low pulse width of external input signal Capture at crest and trough 1 0 0 1 Setting prohibited Measurement of high pulse width of external input signal Capture at trough 1 0 Measurement of high pulse width of external input signal Capture at crest 1 Measurement of high pulse width of external input signal Capture at crest and trough Bit 4 IOC4 0 Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 1 1 1 0 X 0 X X 0 X X X 0 1 1 0 1 1 1 0 X 0 X 0 1 [Legend] X: Don't care Rev. 3.00 Jun. 18, 2008 Page 449 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5. Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 CMP CMP CMP CLR5U CLR5V CLR5W Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 CMPCLR5U 0 R/W TCNT Compare Clear 5U Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture. 0: Disables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1: Enables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1 CMPCLR5V 0 R/W TCNT Compare Clear 5V Enables or disables requests to clear TCNTV_5 at TGRV_5 compare match or input capture. 0: Disables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture 1: Enables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture Rev. 3.00 Jun. 18, 2008 Page 450 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name Initial Value R/W R/W Description TCNT Compare Clear 5W Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture CMPCLR5W 0 10.3.5 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and one each for channels 1 to 5. * TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 Bit: 7 6 5 4 3 2 1 0 TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name TTGE Initial Value 0 R/W R/W Description A/D Converter Start Request Enable Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled Rev. 3.00 Jun. 18, 2008 Page 451 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 6 Bit Name TTGE2 Initial Value 0 R/W R/W Description A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 3.00 Jun. 18, 2008 Page 452 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 Bit Name TGIEC Initial Value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 3.00 Jun. 18, 2008 Page 453 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TIER2_0 Bit: 7 TTGE2 6 - 5 - 4 - 3 - 2 - 1 0 TGIEF TGIEE Initial value: 0 R/W: R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 7 Bit Name TTGE2 Initial Value 0 R/W R/W Description A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGIEF 0 R/W TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled 0 TGIEE 0 R/W TGR Interrupt Enable E Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled Rev. 3.00 Jun. 18, 2008 Page 454 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TIER_5 Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 TGIE5U TGIE5V TGIE5W Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 TGIE5U 0 R/W TGR Interrupt Enable 5U Enables or disables interrupt requests (TGIU_5) by the CMFU5 bit when the CMFU5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIU_5) disabled 1: Interrupt requests (TGIU_5) enabled 1 TGIE5V 0 R/W TGR Interrupt Enable 5V Enables or disables interrupt requests (TGIV_5) by the CMFV5 bit when the CMFV5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIV_5) disabled 1: Interrupt requests (TGIV_5) enabled 0 TGIE5W 0 R/W TGR Interrupt Enable 5W Enables or disables interrupt requests (TGIW_5) by the CMFW5 bit when the CMFW5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIW_5) disabled 1: Interrupt requests (TGIW_5) enabled Rev. 3.00 Jun. 18, 2008 Page 455 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.6 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5. * TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: 7 TCFD 6 - 5 TCFU 4 TCFV 3 TGFD 2 TGFC 1 TGFB 0 TGFA Initial value: R/W: 1 R 1 R 0 0 0 0 0 0 R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 7 Bit Name TCFD Initial Value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6 -- 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCFU 0 R/(W)*1 Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition] * * When 0 is written to TCFU after reading TCFU = 1* When the TCNT value underflows (changes from H'0000 to H'FFFF) 2 [Setting condition] Rev. 3.00 Jun. 18, 2008 Page 456 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 4 Bit Name TCFV Initial Value 0 R/W 1 Description R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Clearing condition] * When 0 is written to TCFV after reading 2 TCFV = 1* When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. [Setting condition] * 3 TGFD 0 R/(W)*1 Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition] * When 0 is written to TGFD after reading 2 TGFD = 1* When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Setting conditions] * * Rev. 3.00 Jun. 18, 2008 Page 457 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 Bit Name TGFC Initial Value 0 R/W 1 Description R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition] * When 0 is written to TGFC after reading 2 TGFC = 1* When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Setting conditions] * * 1 TGFB 0 R/(W)*1 Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Clearing condition] * When 0 is written to TGFB after reading 2 TGFB = 1* When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Setting conditions] * * Rev. 3.00 Jun. 18, 2008 Page 458 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name TGFA Initial Value 0 R/W 1 Description R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Clearing conditions] * * When DMAC is activated by TGIA interrupt When 0 is written to TGFA after reading 2 TGFA = 1* When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Setting conditions] * * Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is held. Rev. 3.00 Jun. 18, 2008 Page 459 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TSR2_0 Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 TGFF 0 TGFE Initial value: R/W: 1 R 1 R 0 R 0 R 0 R 0 R 0 0 R/(W)*1 R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 7, 6 Bit Name -- Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 5 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGFF 0 R/(W)*1 Compare Match Flag F Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Clearing condition] * When 0 is written to TGFF after reading 2 TGFF = 1* When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register [Setting condition] * 0 TGFE 0 R/(W)*1 Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Clearing condition] * When 0 is written to TGFE after reading 2 TGFE = 1* When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register [Setting condition] * Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is held. Rev. 3.00 Jun. 18, 2008 Page 460 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * TSR_5 Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 CMFU5 CMFV5 CMFW5 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)*1 R/(W)*1R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 7 to 3 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 CMFU5 0 R/(W)*1 Compare Match/Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match. Only 0 can be written, for flag clearing. [Clearing condition] * * * When 0 is written to CMFU5 after reading CMFU5 = 1 When TCNTU_5 = TGRU_5 and TGRU_5 is functioning as output compare register When TCNTU_5 value is transferred to TGRU_5 by input capture signal and TGRU_5 is functioning as input capture register When TCNTU_5 value is transferred to TGRU_5 and TGRU_5 is functioning as a register for measuring the 2 pulse width of the external input signal.* [Setting conditions] * Rev. 3.00 Jun. 18, 2008 Page 461 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 1 Bit Name CMFV5 Initial Value 0 R/W 1 Description R/(W)* Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. Only 0 can be written, for flag clearing. [Clearing condition] * * * When 0 is written to CMFV5 after reading CMFV5 = 1 When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register When TCNTV_5 value is transferred to TGRV_5 by input capture signal and TGRV_5 is functioning as input capture register When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the 2 pulse width of the external input signal.* [Setting conditions] * Rev. 3.00 Jun. 18, 2008 Page 462 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name CMFW5 Initial Value 0 R/W 1 Description R/(W)* Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. [Clearing condition] * When 0 is written to CMFW5 after reading CMFW5 = 1 When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register When TCNTW_5 value is transferred to TGRW_5 by input capture signal and TGRW_5 is functioning as input capture register When TCNTW_5 value is transferred to TGRW_5 and TGRW_5 is functioning as a register for measuring 2 the pulse width of the external input signal. * [Setting conditions] * * * Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Timing for transfer is set by the IOC bit in the timer I/O control register U_5/V_5/W_5 (TIORU_5/V_5/W_5). Rev. 3.00 Jun. 18, 2008 Page 463 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM) The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4. Bit: 7 - 6 - 5 - 4 - 3 - 2 TTSE 1 TTSB 0 TTSA Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 TTSE 0 R/W Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared 1 TTSB 0 R/W Timing Select B Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel 0 TTSA 0 R/W Timing Select A Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel Rev. 3.00 Jun. 18, 2008 Page 464 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.8 Timer Input Capture Control Register (TICCR) TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1. Bit: 7 - 6 - 5 - 4 - 3 I2BE 2 I2AE 1 I1BE 0 I1AE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 4 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 I2BE 0 R/W Input Capture Enable Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions 2 I2AE 0 R/W Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions 1 I1BE 0 R/W Input Capture Enable Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions Rev. 3.00 Jun. 18, 2008 Page 465 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name I1AE Initial Value 0 R/W R/W Description Input Capture Enable Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions 10.3.9 Timer Synchronous Clear Register (TSYCR) TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCR in channel 3 but the MTU2 has no TSYCR. Bit: 7 CE0A 6 CE0B 5 CE0C 4 CE0D 3 CE1A 2 CE1B 1 CE2A 0 CE2B Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name CE0A Initial Value 0 R/W R/W Description Clear Enable 0A Enables or disables counter clearing when the TGFA flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_0 1: Enables counter clearing by the TGFA flag in TSR_0 6 CE0B 0 R/W Clear Enable 0B Enables or disables counter clearing when the TGFB flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_0 1: Enables counter clearing by the TGFB flag in TSR_0 Rev. 3.00 Jun. 18, 2008 Page 466 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name CE0C Initial Value 0 R/W R/W Description Clear Enable 0C Enables or disables counter clearing when the TGFC flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFC flag in TSR_0 1: Enables counter clearing by the TGFC flag in TSR_0 4 CE0D 0 R/W Clear Enable 0D Enables or disables counter clearing when the TGFD flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFD flag in TSR_0 1: Enables counter clearing by the TGFD flag in TSR_0 3 CE1A 0 R/W Clear Enable 1A Enables or disables counter clearing when the TGFA flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_1 1: Enables counter clearing by the TGFA flag in TSR_1 2 CE1B 0 R/W Clear Enable 1B Enables or disables counter clearing when the TGFB flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_1 1: Enables counter clearing by the TGFB flag in TSR_1 1 CE2A 0 R/W Clear Enable 2A Enables or disables counter clearing when the TGFA flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_2 1: Enables counter clearing by the TGFA flag in TSR_2 0 CE2B 0 R/W Clear Enable 2B Enables or disables counter clearing when the TGFB flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_2 1: Enables counter clearing by the TGFB flag in TSR_2 Rev. 3.00 Jun. 18, 2008 Page 467 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.10 Timer A/D Converter Start Request Control Register (TADCR) TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4. Bit: 15 14 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 BF[1:0] UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0* R/W 0 R/W 0* R/W 0* R/W 0* R/W 0* R/W 0* R/W Note: * Do not set to 1 when complementary PWM mode is not selected. Bit 15, 14 Bit Name BF[1:0] Initial Value 00 R/W R/W Description TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 10.29. 13 to 8 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 UT4AE 0 R/W Up-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation 6 DT4AE 0* R/W Down-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation Rev. 3.00 Jun. 18, 2008 Page 468 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name UT4BE Initial Value 0 R/W R/W Description Up-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation 4 DT4BE 0* R/W Down-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation 3 ITA3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping 2 ITA4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping 1 ITB3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping Rev. 3.00 Jun. 18, 2008 Page 469 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name ITB4VE Initial Value 0* R/W R/W Description TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 10.29 Setting of Transfer Timing by Bits BF1 and BF0 Bit 7 BF1 0 0 1 1 Bit 6 BF0 0 1 0 1 Description Does not transfer data from the cycle set buffer register to the cycle set register. Transfers data from the cycle set buffer register to the cycle set register at the crest of the TCNT_4 count.*1 Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.*2 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the TCNT_4 count.*2 Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected. Rev. 3.00 Jun. 18, 2008 Page 470 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. 10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. Rev. 3.00 Jun. 18, 2008 Page 471 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.13 Timer Counter (TCNT) The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R/W Note: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. 10.3.14 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse width measurement registers. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF. Rev. 3.00 Jun. 18, 2008 Page 472 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.15 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. * TSTR Bit: 7 CST4 6 CST3 5 - 4 - 3 - 2 CST2 1 CST1 0 CST0 Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 6 Bit Name CST4 CST3 Initial Value 0 0 R/W R/W R/W Description Counter Start 4 and 3 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 473 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 1 0 Bit Name CST2 CST1 CST0 Initial Value 0 0 0 R/W R/W R/W R/W Description Counter Start 2 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation * TSTR_5 Bit : 7 - 6 - 5 - 4 - 3 - 2 1 0 CSTU5 CSTV5 CSTW5 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 CSTU5 0 R/W Counter Start U5 Selects operation or stoppage for TCNTU_5. 0: TCNTU_5 count operation is stopped 1: TCNTU_5 performs count operation 1 CSTV5 0 R/W Counter Start V5 Selects operation or stoppage for TCNTV_5. 0: TCNTV_5 count operation is stopped 1: TCNTV_5 performs count operation 0 CSTW5 0 R/W Counter Start W5 Selects operation or stoppage for TCNTW_5. 0: TCNTW_5 count operation is stopped 1: TCNTW_5 performs count operation Rev. 3.00 Jun. 18, 2008 Page 474 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.16 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: 7 6 5 - 4 - 3 - 2 1 0 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 6 Bit Name SYNC4 SYNC3 Initial Value 0 0 R/W R/W R/W Description Timer Synchronous operation 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 475 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 1 0 Bit Name SYNC2 SYNC1 SYNC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Timer Synchronous operation 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Rev. 3.00 Jun. 18, 2008 Page 476 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and MTU2S counters. Note that the MTU2S does not have TCSYSTR. Bit: 7 SCH0 6 SCH1 5 SCH2 4 SCH3 3 SCH4 2 - 1 0 SCH3S SCH4S Initial value: 0 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 1 can be written to set the register. 0 R 0 0 R/(W)* R/(W)* Bit 7 Bit Name SCH0 Initial Value 0 R/W Description R/(W)* Synchronous Start Controls synchronous start of TCNT_0 in the MTU2. 0: Does not specify synchronous start for TCNT_0 in the MTU2 1: Specifies synchronous start for TCNT_0 in the MTU2 [Clearing condition] * When 1 is set to the CST0 bit of TSTR in MTU2 while SCH0 = 1 6 SCH1 0 R/(W)* Synchronous Start Controls synchronous start of TCNT_1 in the MTU2. 0: Does not specify synchronous start for TCNT_1 in the MTU2 1: Specifies synchronous start for TCNT_1 in the MTU2 [Clearing condition] * When 1 is set to the CST1 bit of TSTR in MTU2 while SCH1 = 1 Rev. 3.00 Jun. 18, 2008 Page 477 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name SCH2 Initial Value 0 R/W Description R/(W)* Synchronous Start Controls synchronous start of TCNT_2 in the MTU2. 0: Does not specify synchronous start for TCNT_2 in the MTU2 1: Specifies synchronous start for TCNT_2 in the MTU2 [Clearing condition] * When 1 is set to the CST2 bit of TSTR in MTU2 while SCH2 = 1 4 SCH3 0 R/(W)* Synchronous Start Controls synchronous start of TCNT_3 in the MTU2. 0: Does not specify synchronous start for TCNT_3 in the MTU2 1: Specifies synchronous start for TCNT_3 in the MTU2 [Clearing condition] * When 1 is set to the CST3 bit of TSTR in MTU2 while SCH3 = 1 3 SCH4 0 R/(W)* Synchronous Start Controls synchronous start of TCNT_4 in the MTU2. 0: Does not specify synchronous start for TCNT_4 in the MTU2 1: Specifies synchronous start for TCNT_4 in the MTU2 [Clearing condition] * When 1 is set to the CST4 bit of TSTR in MTU2 while SCH4 = 1 2 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 478 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 1 Bit Name SCH3S Initial Value 0 R/W Description R/(W)* Synchronous Start Controls synchronous start of TCNT_3S in the MTU2S. 0: Does not specify synchronous start for TCNT_3S in the MTU2S 1: Specifies synchronous start for TCNT_3S in the MTU2S [Clearing condition] * When 1 is set to the CST3 bit of TSTRS in MTU2S while SCH3S = 1 0 SCH4S 0 R/(W)* Synchronous Start Controls synchronous start of TCNT_4S in the MTU2S. 0: Does not specify synchronous start for TCNT_4S in the MTU2S 1: Specifies synchronous start for TCNT_4S in the MTU2S [Clearing condition] * When 1 is set to the CST4 bit of TSTRS in MTU2S while SCH4S = 1 Note: Only 1 can be written to set the register. Rev. 3.00 Jun. 18, 2008 Page 479 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.18 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and 4. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 RWE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W Bit 7 to 1 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RWE 1 R/W Read/Write Enable Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition] * When 0 is written to the RWE bit after reading RWE = 1 * Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4. Rev. 3.00 Jun. 18, 2008 Page 480 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.19 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit: 7 - 6 - 5 OE4D 4 OE4C 3 OE3D 2 OE4B 1 OE4A 0 OE3B Initial value: R/W: 1 R 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7, 6 Bit Name -- Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 5 OE4D 0 R/W Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 4 OE4C 0 R/W Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 3 OE3D 0 R/W Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 2 OE4B 0 R/W Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 1 OE4A 0 R/W Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Rev. 3.00 Jun. 18, 2008 Page 481 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name OE3B Initial Value 0 R/W R/W Description Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Note: * The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 10.3.20, Timer Output Control Register 1 (TOCR1), and section 10.3.21, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable MTU2 output in other than complementary PWM or resetsynchronized PWM mode. When these bits are set to 0, low level is output. 10.3.20 Timer Output Control Register 1 (TOCR1) TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: 7 - 6 PSYE 5 - 4 - 3 TOCL 2 TOCS 1 OLSN 0 OLSP Initial value: R/W: 0 R 0 R/W 0 R 0 R 0 0 R/(W)* R/W 0 R/W 0 R/W Note: * This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit. Bit 7 Bit Name -- Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 482 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 3 Bit Name TOCL Initial value 0 R/W 1 Description R/(W)* TOC Register Write Protection*2 This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled 2 TOCS 0 R/W TOC Select This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected 1 OLSN 0 R/W Output Level Select N*3 This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 10.30. 0 OLSP 0 R/W Output Level Select P*3 This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 10.31. Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 2. Clearing the TOCS0 bit to 0 makes this bit setting valid. Table 10.30 Output Level Select Function Bit 1 Function Compare Match Output OLSN 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start. Rev. 3.00 Jun. 18, 2008 Page 483 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.31 Output Level Select Function Bit 0 Function Compare Match Output OLSP 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level Figure 10.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3, and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Initial output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Time Positive phase output Reverse phase output Figure 10.2 Complementary PWM Mode Output Level Example Rev. 3.00 Jun. 18, 2008 Page 484 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.21 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: 7 6 BF[1:0] 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7, 6 Bit Name BF[1:0] Initial value 00 R/W R/W Description TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 10.32. 5 OLS3N 0 R/W Output Level Select 3N* This bit selects the output level on TIOC4D in resetsynchronized PWM mode/complementary PWM mode. See table 10.33. 4 OLS3P 0 R/W Output Level Select 3P* This bit selects the output level on TIOC4B in resetsynchronized PWM mode/complementary PWM mode. See table 10.34. 3 OLS2N 0 R/W Output Level Select 2N* This bit selects the output level on TIOC4C in resetsynchronized PWM mode/complementary PWM mode. See table 10.35. 2 OLS2P 0 R/W Output Level Select 2P* This bit selects the output level on TIOC4A in resetsynchronized PWM mode/complementary PWM mode. See table 10.36. 1 OLS1N 0 R/W Output Level Select 1N* This bit selects the output level on TIOC3D in resetsynchronized PWM mode/complementary PWM mode. See table 10.37. Rev. 3.00 Jun. 18, 2008 Page 485 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name OLS1P Initial value 0 R/W R/W Description Output Level Select 1P* This bit selects the output level on TIOC3B in resetsynchronized PWM mode/complementary PWM mode. See table 10.38. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. Table 10.32 Setting of Bits BF1 and BF0 Bit 7 BF1 0 0 Bit 6 BF0 0 1 Complementary PWM Mode Description Reset-Synchronized PWM Mode Does not transfer data from the Does not transfer data from the buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2. Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared Setting prohibited 1 0 1 1 Setting prohibited Table 10.33 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Rev. 3.00 Jun. 18, 2008 Page 486 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.34 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level Table 10.35 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Table 10.36 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level Table 10.37 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Rev. 3.00 Jun. 18, 2008 Page 487 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.38 TIOC4B Output Level Select Function Bit 0 Function Compare Match Output OLS1P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level 10.3.22 Timer Output Level Buffer Register (TOLBR) TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: 7 - 6 - 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7, 6 Bit Name -- Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Specifies the buffer value to be transferred to the OLS3N bit in TOCR2. Specifies the buffer value to be transferred to the OLS3P bit in TOCR2. Specifies the buffer value to be transferred to the OLS2N bit in TOCR2. Specifies the buffer value to be transferred to the OLS2P bit in TOCR2. Specifies the buffer value to be transferred to the OLS1N bit in TOCR2. Specifies the buffer value to be transferred to the OLS1P bit in TOCR2. Rev. 3.00 Jun. 18, 2008 Page 488 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS [1] [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. Set TOCR2 [2] [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Set TOLBR [3] Figure 10.3 PWM Output Level Setting Procedure in Buffer Operation 10.3.23 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Bit: 7 - 6 BDC 5 N 4 P 3 FB 2 WF 1 VF 0 UF Initial value: R/W: 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name -- Initial value 1 R/W R Description Reserved This bit is always read as 1. The write value should always be 1. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective Rev. 3.00 Jun. 18, 2008 Page 489 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name N Initial value 0 R/W R/W Description Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU2/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (setting values of UF, VF, and WF in TGCR). 2 1 0 WF VF UF 0 0 0 R/W R/W R/W Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 10.39. Rev. 3.00 Jun. 18, 2008 Page 490 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.39 Output level Select Function Function Bit 2 WF 0 Bit 1 VF 0 Bit 0 UF 0 1 1 0 1 1 0 0 1 1 0 1 TIOC3B U Phase OFF ON OFF OFF OFF ON OFF OFF TIOC4A V Phase OFF OFF ON ON OFF OFF OFF OFF TIOC4B TIOC3D TIOC4C V Phase OFF OFF OFF OFF ON ON OFF OFF TIOC4D W Phase OFF ON OFF ON OFF OFF OFF OFF W Phase U Phase OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON OFF 10.3.24 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R Note: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. Rev. 3.00 Jun. 18, 2008 Page 491 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.25 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 10.3.26 Timer Cycle Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. Rev. 3.00 Jun. 18, 2008 Page 492 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.27 Timer Cycle Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. 10.3.28 Timer Interrupt Skipping Set Register (TITCR) TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. The MTU2 has one TITCR. Bit: 7 T3AEN 6 5 3ACOR[2:0] 4 3 T4VEN 2 1 4VCOR[2:0] 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name T3AEN Initial value 0 R/W R/W Description T3AEN Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 10.40. T4VEN Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled 3 T4VEN 0 R/W Rev. 3.00 Jun. 18, 2008 Page 493 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 to 0 Bit Name Initial value R/W R/W Description These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 10.41. 4VCOR[2:0] 000 Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TICNT). Table 10.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 3ACOR2 0 0 0 0 1 1 1 1 Bit 5 3ACOR1 0 0 1 1 0 0 1 1 Bit 4 3ACOR0 0 1 0 1 0 1 0 1 Description Does not skip TGIA_3 interrupts. Sets the TGIA_3 interrupt skipping count to 1. Sets the TGIA_3 interrupt skipping count to 2. Sets the TGIA_3 interrupt skipping count to 3. Sets the TGIA_3 interrupt skipping count to 4. Sets the TGIA_3 interrupt skipping count to 5. Sets the TGIA_3 interrupt skipping count to 6. Sets the TGIA_3 interrupt skipping count to 7. Table 10.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 4VCOR2 0 0 0 0 1 1 1 1 Bit 1 4VCOR1 0 0 1 1 0 0 1 1 Bit 0 4VCOR0 0 1 0 1 0 1 0 1 Description Does not skip TCIV_4 interrupts. Sets the TCIV_4 interrupt skipping count to 1. Sets the TCIV_4 interrupt skipping count to 2. Sets the TCIV_4 interrupt skipping count to 3. Sets the TCIV_4 interrupt skipping count to 4. Sets the TCIV_4 interrupt skipping count to 5. Sets the TCIV_4 interrupt skipping count to 6. Sets the TCIV_4 interrupt skipping count to 7. Rev. 3.00 Jun. 18, 2008 Page 494 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.29 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains its value even after stopping the count operation of TCNT_3 and TCNT_4. Bit: 7 - 6 5 3ACNT[2:0] 4 3 - 2 1 4VCNT[2:0] 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 7 6 to 4 Bit Name -- 3ACNT[2:0] Initial Value 0 000 R/W R R Description Reserved This bit is always read as 0. TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions] * * * When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR When the T3AEN bit in TITCR is cleared to 0 When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 3 2 to 0 -- 4VCNT[2:0] 0 000 R R Reserved This bit is always read as 0. TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions] * * * When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR When the T4VEN bit in TITCR is cleared to 0 When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0 Note: To clear the TITCNT, clear the bits T3AEN and T4VEN in TITCR to 0. Rev. 3.00 Jun. 18, 2008 Page 495 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.30 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. The MTU2 has one TBTER. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 0 BTE[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 7 to 2 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 10.42. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR Rev. 3.00 Jun. 18, 2008 Page 496 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.42 Setting of Bits BTE1 and BTE0 Bit 1 BTE1 0 0 1 1 Bit 0 BTE0 0 1 0 1 Description Enables transfer from the buffer registers to the temporary registers*1 and does not link the transfer with interrupt skipping operation. Disables transfer from the buffer registers to the temporary registers. Links transfer from the buffer registers to the temporary registers with interrupt skipping operation.*2 Setting prohibited Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 10.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed. Rev. 3.00 Jun. 18, 2008 Page 497 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.31 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 TDER Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W) Bit 7 to 1 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TDER 1 R/(W) Dead Time Enable Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition] * When 0 is written to TDER after reading TDER = 1 Note: * TDDR must be set to 1 or a larger value. Rev. 3.00 Jun. 18, 2008 Page 498 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.3.32 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: 7 CCE 6 - 5 - 4 - 3 - 2 - 1 SCC 0 WRE Initial value: 0* R/W: R/(W) 0 R 0 R 0 R 0 R 0 R 0 0 R/(W) R/(W) Note: * Do not set to 1 when complementary PWM mode is not selected. Bit 7 Bit Name CCE Initial Value 0* R/W R/(W) Description Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition] * When 1 is written to CCE after reading CCE = 0 6 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 499 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 1 Bit Name SCC Initial Value 0 R/W R/(W) Description Synchronous Clearing Control Specifies whether to clear TCNT_3 and TCNT_4 in the MTU2S when synchronous counter clearing between the MTU2 and MTU2S occurs in complementary PWM mode. When using this control, place the MTU2S in complementary PWM mode. When modifying the SCC bit while the counters are operating, do not modify the CCE or WRE bits. Counter clearing synchronized with the MTU2 is disabled by the SCC bit setting only when synchronous clearing occurs outside the Tb interval at the trough. When synchronous clearing occurs in the Tb interval at the trough including the period immediately after TCNT_3 and TCNT_4 start operation, TCNT_3 and TCNT_4 in the MTU2S are cleared. For the Tb interval at the trough in complementary PWM mode, see figure 10.40. In the MTU2, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: Enables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2-MTU2S synchronous clearing operation 1: Disables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2-MTU2S synchronous clearing operation [Setting condition] * When 1 is written to SCC after reading SCC = 0 Rev. 3.00 Jun. 18, 2008 Page 500 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name WRE Initial Value 0 R/W R/(W) Description Waveform Retain Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The output waveform is retained only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 10.40. 0: Outputs the initial value specified in TOCR 1: Retains the waveform output immediately before synchronous clearing [Setting condition] * When 1 is written to WRE after reading WRE = 0 Note: * Do not set to 1 when complementary PWM mode is not selected. 10.3.33 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. Rev. 3.00 Jun. 18, 2008 Page 501 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4 10.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC). (1) Counter Operation When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. (a) Example of Count Operation Setting Procedure Figure 10.4 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation Operation selection Select counter clock [1] Periodic counter Select counter clearing source Select output compare register Set period [2] [3] [4] Start count operation [5] Figure 10.4 Example of Counter Operation Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 502 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (b) Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU2's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU2 requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.5 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.5 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the MTU2 requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev. 3.00 Jun. 18, 2008 Page 503 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.6 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DMAC activation TGF Figure 10.6 Periodic Counter Operation (2) Waveform Output by Compare Match The MTU2 can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match Figure 10.7 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 10.7 Example of Setting Procedure for Waveform Output by Compare Match Rev. 3.00 Jun. 18, 2008 Page 504 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (b) Examples of Waveform Output Operation: Figure 10.8 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 TIOCA TIOCB No change No change Time No change No change 1 output 0 output Figure 10.8 Example of 0 Output/1 Output Operation Figure 10.9 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB TIOCA Time Toggle output Toggle output Figure 10.9 Example of Toggle Output Operation Rev. 3.00 Jun. 18, 2008 Page 505 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, P/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P/1 is selected. (a) Example of Input Capture Operation Setting Procedure Figure 10.10 shows an example of the input capture operation setting procedure. [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Input selection Select input capture input [1] Start count [2] Figure 10.10 Example of Input Capture Operation Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 506 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (b) Example of Input Capture Operation Figure 10.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.11 Example of Input Capture Operation Rev. 3.00 Jun. 18, 2008 Page 507 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 10.12 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source [3] Set synchronous counter clearing [4] No Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10.12 Example of Synchronous Operation Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 508 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) Example of Synchronous Operation Figure 10.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 10.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOC0A TIOC1A TIOC2A Time Figure 10.13 Example of Synchronous Operation Rev. 3.00 Jun. 18, 2008 Page 509 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 10.43 shows the register combinations used in buffer operation. Table 10.43 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 TGRE_0 3 TGRA_3 TGRB_3 4 TGRA_4 TGRB_4 Buffer Register TGRC_0 TGRD_0 TGRF_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.14. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.14 Compare Match Buffer Operation Rev. 3.00 Jun. 18, 2008 Page 510 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.15. Input capture signal Buffer register Timer general register TCNT Figure 10.15 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 10.16 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Buffer operation Select TGR function Start count [3] Figure 10.16 Example of Buffer Operation Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 511 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) (a) Examples of Buffer Operation When TGR is an output compare register Figure 10.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. In this example, the TTSA bit in TBTM is cleared to 0. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 10.4.5, PWM Modes. TCNT value TGRB_0 H'0200 H'0520 H'0450 TGRA_0 H'0000 TGRC_0 H'0200 Transfer Time H'0450 H'0520 TGRA_0 H'0200 H'0450 TIOCA Figure 10.17 Example of Buffer Operation (1) (b) When TGR is an input capture register Figure 10.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 3.00 Jun. 18, 2008 Page 512 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10.18 Example of Buffer Operation (2) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer timing is one of the following cases. * When TCNT overflows (H'FFFF to H'0000) * When H'0000 is written to TCNT during counting * When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note: TBTM must be modified only while TCNT stops. Figure 10.19 shows an operation example in which PWM mode 1 is designated for channel 0 and buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. The TTSA bit in TBTM_0 is set to 1. Rev. 3.00 Jun. 18, 2008 Page 513 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value TGRB_0 H'0450 TGRA_0 H'0520 H'0200 H'0000 Time TGRC_0 H'0200 H'0450 Transfer H'0520 TGRA_0 H'0200 H'0450 H'0520 TIOCA Figure 10.19 Example of Buffer Operation when TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.44 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 10.44 Cascaded Combinations Combination Channels 1 and 2 Upper 16 Bits TCNT_1 Lower 16 Bits TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). For input capture in cascade connection, refer to section 10.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection. Rev. 3.00 Jun. 18, 2008 Page 514 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.45 shows the TICCR setting and input capture input pins. Table 10.45 TICCR Setting and Input Capture Input Pins Target Input Capture Input capture from TCNT_1 to TGRA_1 Input capture from TCNT_1 to TGRB_1 Input capture from TCNT_2 to TGRA_2 Input capture from TCNT_2 to TGRB_2 TICCR Setting I2AE bit = 0 (initial value) I2AE bit = 1 I2BE bit = 0 (initial value) I2BE bit = 1 I1AE bit = 0 (initial value) I1AE bit = 1 I1BE bit = 0 (initial value) I1BE bit = 1 Input Capture Input Pins TIOC1A TIOC1A, TIOC2A TIOC1B TIOC1B, TIOC2B TIOC2A TIOC2A, TIOC1A TIOC2B TIOC2B, TIOC1B (1) Example of Cascaded Operation Setting Procedure Figure 10.20 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [1] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Cascaded operation Set cascading Start count [2] Figure 10.20 Cascaded Operation Setting Procedure (2) Cascaded Operation Example (a) Figure 10.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. Rev. 3.00 Jun. 18, 2008 Page 515 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 10.21 Cascaded Operation Example (a) (3) Cascaded Operation Example (b) Figure 10.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used. TCNT_2 value H'FFFF H'C256 H'6128 H'0000 H'0512 H'0513 H'0514 Time TCNT_1 TIOC1A TIOC2A TGRA_1 H'0512 H'0513 TGRA_2 H'C256 As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing. Figure 10.22 Cascaded Operation Example (b) Rev. 3.00 Jun. 18, 2008 Page 516 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (4) Cascaded Operation Example (c) Figure 10.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'FFFF H'C256 H'9192 H'6128 H'2064 H'0000 Time TCNT_1 H'0512 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 H'0512 H'0513 H'0514 TGRA_2 H'6128 H'2064 H'C256 H'9192 Figure 10.23 Cascaded Operation Example (c) (5) Cascaded Operation Example (d) Figure 10.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1. Rev. 3.00 Jun. 18, 2008 Page 517 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value TGRA_0 Compare match between TCNT_0 and TGRA_0 H'0000 TCNT_2 value H'FFFF H'D000 Time H'0000 Time TCNT_1 H'0512 H'0513 TIOC1A TIOC2A TGRA_1 H'0513 TGRA_2 H'D000 Figure 10.24 Cascaded Operation Example (d) Rev. 3.00 Jun. 18, 2008 Page 518 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.46. Rev. 3.00 Jun. 18, 2008 Page 519 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.46 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4C TIOC4A TIOC3C TIOC3A TIOC2A TIOC1A TIOC0C PWM Mode 1 TIOC0A PWM Mode 2 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev. 3.00 Jun. 18, 2008 Page 520 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (1) Example of PWM Mode Setting Procedure Figure 10.25 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [3] [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level Set TGR [4] Start count [6] Figure 10.25 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation Figure 10.26 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels. Rev. 3.00 Jun. 18, 2008 Page 521 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 10.26 Example of PWM Mode Operation (1) Figure 10.27 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 10.27 Example of PWM Mode Operation (2) Rev. 3.00 Jun. 18, 2008 Page 522 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 10.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 10.28 Example of PWM Mode Operation (3) Rev. 3.00 Jun. 18, 2008 Page 523 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 10.47 shows the correspondence between external clock pins and channels. Table 10.47 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD (1) Example of Phase Counting Mode Setting Procedure Figure 10.29 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [1] [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode Start count [2] Figure 10.29 Example of Phase Counting Mode Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 524 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 10.30 shows an example of phase counting mode 1 operation, and table 10.48 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.30 Example of Phase Counting Mode 1 Operation Table 10.48 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 3.00 Jun. 18, 2008 Page 525 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (b) Phase counting mode 2 Figure 10.31 shows an example of phase counting mode 2 operation, and table 10.49 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.31 Example of Phase Counting Mode 2 Operation Table 10.49 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 3.00 Jun. 18, 2008 Page 526 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (c) Phase counting mode 3 Figure 10.32 shows an example of phase counting mode 3 operation, and table 10.50 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.32 Example of Phase Counting Mode 3 Operation Table 10.50 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 3.00 Jun. 18, 2008 Page 527 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (d) Phase counting mode 4 Figure 10.33 shows an example of phase counting mode 4 operation, and table 10.51 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.33 Example of Phase Counting Mode 4 Operation Table 10.51 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 3.00 Jun. 18, 2008 Page 528 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (3) Phase Counting Mode Application Example Figure 10.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Rev. 3.00 Jun. 18, 2008 Page 529 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 + + - TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 10.34 Phase Counting Mode Application Example Rev. 3.00 Jun. 18, 2008 Page 530 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 10.52 shows the PWM output pins used. Table 10.53 shows the settings of the registers. Table 10.52 Output Pins for Reset-Synchronized PWM Mode Channel 3 Output Pin TIOC3B TIOC3D 4 TIOC4A TIOC4C TIOC4B TIOC4D Description PWM output pin 1 PWM output pin 1' (negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (negative-phase waveform of PWM output 3) Table 10.53 Register Settings for Reset-Synchronized PWM Mode Register TCNT_3 TCNT_4 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Description of Setting Initial setting of H'0000 Initial setting of H'0000 Set count cycle for TCNT_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins Rev. 3.00 Jun. 18, 2008 Page 531 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (1) Procedure for Selecting the Reset-Synchronized PWM Mode Figure 10.35 shows an example of procedure for selecting the reset synchronized PWM mode. [1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. [1] [2] Set bits TPSC2-TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2-CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. [5] [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 10.3. [7] Set bits MD3-MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. Reset-synchronized PWM mode Stop counting Select counter clock and counter clear source [2] Brushless DC motor control setting [3] Set TCNT [4] Set TGR PWM cycle output enabling, PWM output level setting [6] Set reset-synchronized PWM mode [7] Enable waveform output [8] PFC setting [9] Start count operation Reset-synchronized PWM mode [10] Figure 10.35 Procedure for Selecting Reset-Synchronized PWM Mode Rev. 3.00 Jun. 18, 2008 Page 532 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) Reset-Synchronized PWM Mode Operation Figure 10.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 comparematch occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT_3 and TCNT_4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 10.36 Reset-Synchronized PWM Mode Operation Example (When TOCR's OLSN = 1 and OLSP = 1) Rev. 3.00 Jun. 18, 2008 Page 533 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without nonoverlapping interval are also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 10.54 shows the PWM output pins used. Table 10.55 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 10.54 Output Pins for Complementary PWM Mode Channel 3 Output Pin TIOC3A TIOC3B TIOC3C TIOC3D Description Toggle output synchronized with PWM period (or I/O port) PWM output pin 1 I/O port* PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) PWM output pin 2 PWM output pin 3 PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) 4 TIOC4A TIOC4B TIOC4C TIOC4D Note: * Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. Rev. 3.00 Jun. 18, 2008 Page 534 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.55 Register Settings for Complementary PWM Mode Channel 3 Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1) Temporary register 2 (TEMP2) Temporary register 3 (TEMP3) Note: * Description Start of up-count from value set in dead time register Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) PWM output 1 compare register TGRA_3 buffer register PWM output 1/TGRB_3 buffer register Up-count start, initialized to H'0000 PWM output 2 compare register PWM output 3 compare register PWM output 2/TGRA_4 buffer register PWM output 3/TGRB_4 buffer register Set TCNT_4 and TCNT_3 offset value (dead time value) Set TCNT_4 upper limit value (1/2 carrier cycle) TCDR buffer register Subcounter for dead time generation PWM output 1/TGRB_3 temporary register PWM output 2/TGRA_4 temporary register PWM output 3/TGRB_4 temporary register Read/Write from CPU Maskable by TRWER setting* Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Always readable/writable Maskable by TRWER setting* Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Always readable/writable Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Read-only Not readable/writable Not readable/writable Not readable/writable Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register). Rev. 3.00 Jun. 18, 2008 Page 535 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TGRA_3 comparematch interrupt TCNT_4 underflow interrupt TGRC_3 TCBR TDDR TGRA_3 TCDR Comparator Output controller Match signal PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2 POE3 Comparator Match signal TGRB_3 TGRA_4 TGRD_3 TGRC_4 TGRD_4 TGRB_4 Temp 2 Temp 3 Temp 1 External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Figure 10.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode Rev. 3.00 Jun. 18, 2008 Page 536 of 1160 REJ09B0191-0300 Output protection circuit TCNT_3 TCNTS TCNT_4 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (1) Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in figure 10.38. [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. [1] [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2-CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. Inter-channel synchronization setting [5] [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 10.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. Start count operation [13] [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC motor control setting [2] [3] TCNT setting [4] TGR setting [6] Enable/disable dead time generation Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting [7] [8] [9] [10] Enable waveform output [11] StartPFC setting count operation [12] Figure 10.38 Example of Complementary PWM Mode Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 537 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 10.39 illustrates counter operation in complementary PWM mode, and figure 10.40 shows an example of complementary PWM mode operation. (a) Counter Operation In complementary PWM mode, three counters--TCNT_3, TCNT_4, and TCNTS--perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. Rev. 3.00 Jun. 18, 2008 Page 538 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 TCNT_3 TCNT_4 TCNTS TCNTS Time Figure 10.39 Complementary PWM Mode Counter Operation (b) Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 10.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 10.40 shows an example in which the mode is selected in which the change is made in the trough. In the tb interval (tb1 in figure 10.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared Rev. 3.00 Jun. 18, 2008 Page 539 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters--TCNT_3, TCNT_4, and TCNTS-- and two registers--compare register and temporary register--are compared, and PWM output controlled accordingly. Rev. 3.00 Jun. 18, 2008 Page 540 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 TGRA_3 Ta Tb1 Ta Tb2 Ta TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 H'6400 H'0080 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 10.40 Example of Complementary PWM Mode Operation Rev. 3.00 Jun. 18, 2008 Page 541 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (c) Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 10.56 Registers and Counters Requiring Initialization Register/Counter TGRC_3 Set Value 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR TCBR TGRD_3, TGRC_4, TGRD_4 TCNT_4 Dead time Td (1 when dead time generation is disabled by TDER) 1/2 PWM carrier cycle Initial PWM duty value for each phase H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1. Rev. 3.00 Jun. 18, 2008 Page 542 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (d) PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. (e) Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. (f) Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 10.41 shows an example of operation without dead time. Rev. 3.00 Jun. 18, 2008 Page 543 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary register to compare register Transfer from temporary register to compare register Ta TGRA_3=TCDR+1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4 Tb1 Ta Tb2 Ta TDDR=1 H'0000 Buffer register TGRC_4 Data1 Data2 Temporary register TEMP2 Data1 Data2 Compare register TGRA_4 Data1 Data2 Output waveform Output waveform Output waveform is active-low. Figure 10.41 Example of Operation without Dead Time Rev. 3.00 Jun. 18, 2008 Page 544 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (g) PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers--TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value Without dead time: TGRA_3 set value = TCDR set value + 1 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 10.42 illustrates the operation when the PWM cycle is updated at the crest. See description (h), Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 10.42 Example of PWM Cycle Updating Rev. 3.00 Jun. 18, 2008 Page 545 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (h) Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 10.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. Rev. 3.00 Jun. 18, 2008 Page 546 of 1160 REJ09B0191-0300 Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register : Compare register : Buffer register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H'0000 Time BR data2 data1 data2 data3 data1 data2 data3 data4 data4 data3 data5 data5 data4 data6 data6 data6 Temp_R data1 Figure 10.43 Example of Data Update in Complementary PWM Mode Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Jun. 18, 2008 Page 547 of 1160 GR REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (i) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 10.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 10.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TGRA_4 TDDR Time Initial output Positive phase output Negative phase output Dead time Active level Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 10.44 Example of Initial Output in Complementary PWM Mode (1) Rev. 3.00 Jun. 18, 2008 Page 548 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TDDR TGRA_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 10.45 Example of Initial Output in Complementary PWM Mode (2) Rev. 3.00 Jun. 18, 2008 Page 549 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (j) Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 10.46 to 10.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a b c d (or c d a' b'), as shown in figure 10.46. If compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 10.47, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 10.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. Rev. 3.00 Jun. 18, 2008 Page 550 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period TGR3A_3 T2 period T1 period c TCDR d a b a' b' TDDR H'0000 Positive phase Negative phase Figure 10.46 Example of Complementary PWM Mode Waveform Output (1) T1 period TGRA_3 c TCDR a b d T2 period T1 period a b TDDR H'0000 Positive phase Negative phase Figure 10.47 Example of Complementary PWM Mode Waveform Output (2) Rev. 3.00 Jun. 18, 2008 Page 551 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period TGRA_3 T2 period T1 period TCDR a b TDDR c a' H'0000 Positive phase b' d Negative phase Figure 10.48 Example of Complementary PWM Mode Waveform Output (3) T1 period TGRA_3 c d T2 period T1 period TCDR a b a' TDDR b' H'0000 Positive phase Negative phase Figure 10.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) Rev. 3.00 Jun. 18, 2008 Page 552 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period TGRA_3 T2 period T1 period TCDR a b a b TDDR H'0000 Positive phase c d Negative phase Figure 10.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period TGRA_3 T2 period c d T1 period TCDR a b TDDR H'0000 Positive phase Negative phase Figure 10.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) Rev. 3.00 Jun. 18, 2008 Page 553 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 Positive phase Negative phase c b' d a' Figure 10.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 T2 period T1 period c ad b TCDR TDDR H'0000 Positive phase Negative phase Figure 10.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Rev. 3.00 Jun. 18, 2008 Page 554 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (k) Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 10.49 to 10.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. (l) Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 10.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 10.54 Example of Toggle Output Waveform Synchronized with PWM Output Rev. 3.00 Jun. 18, 2008 Page 555 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (m) Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 10.55 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNTS TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 10.55 Counter Clearing Synchronized with Another Channel Rev. 3.00 Jun. 18, 2008 Page 556 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 10.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 10.56) immediately after the counters start operation, initial value output is not suppressed. This function can be used in both the MTU2 and MTU2S. In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter clearing in complementary PWM mode; in the MTU2S, compare match or input capture flag setting in channels 0 to 2 in the MTU2 can cause counter clearing. Counter start Tb interval Tb interval Tb interval TGRA_3 TCDR TCNT_3 TGRB_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Figure 10.56 Timing for Synchronous Counter Clearing Rev. 3.00 Jun. 18, 2008 Page 557 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 10.57. Output waveform control at synchronous counter clearing Stop count operation [1] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. Set TWCR and complementary PWM mode [2] [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Start count operation [3] Output waveform control at synchronous counter clearing Figure 10.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode * Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 10.58 to 10.61 show examples of output waveform control in which the MTU2 operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 10.58 to 10.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 10.56, respectively. In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in complementary PWM mode and synchronous counter clearing is generated while the SCC bit is cleared to 0 and the WRE bit is set to 1 in TWCR. Rev. 3.00 Jun. 18, 2008 Page 558 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 10.56; Bit WRE of TWCR in MTU2 is 1) Rev. 3.00 Jun. 18, 2008 Page 559 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 10.56; Bit WRE of TWCR in MTU2 is 1) Rev. 3.00 Jun. 18, 2008 Page 560 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 10.56; Bit WRE of TWCR is 1) Rev. 3.00 Jun. 18, 2008 Page 561 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit WRE = 1 TGRA_3 TCDR Synchronous clearing TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Initial value output is suppressed. Negative phase Output waveform is active-low. Figure 10.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 10.56; Bit WRE of TWCR is 1) Rev. 3.00 Jun. 18, 2008 Page 562 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (o) Suppressing MTU2-MTU2S Synchronous Counter Clearing In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused by the MTU2. Synchronous counter clearing is suppressed only within the interval shown in figure 10.62. When using this function, the MTU2S should be set to complementary PWM mode. For details of synchronous clearing caused by the MTU2, refer to section 10.4.10 (2), MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (MTU2-MTU2S Synchronous Counter Clearing). Tb interval immediately after counter operation starts Tb interval at the crest Tb interval at the trough Tb interval at the crest Tb interval at the trough TGRA_3 TCDR TGRB_3 TDDR H'0000 MTU2-MTU2S synchronous counter clearing is suppressed. MTU2-MTU2S synchronous counter clearing is suppressed. Figure 10.62 MTU2-MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC Bit in TWCR Rev. 3.00 Jun. 18, 2008 Page 563 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing An example of the procedure for suppressing MTU2-MTU2S synchronous counter clearing is shown in figure 10.63. [1] Clear bits CST of the timer start register (TSTR) in the MTU2S to 0, and halt count operation. Clear bits CST of TSTR in the MTU2 to 0, and halt count operation. [2] Set the complementary PWM mode in the MTU2S and compare match/input capture operation in the MTU2. When bit WRE in TWCR should be set, make appropriate setting here. [3] Set bits CST3 and CST4 of TSTR in the MTU2S to 1 to start count operation. For MTU2-MTU2S synchronous counter clearing, set bits CST of TSTR in the MTU2 to 1 to start count operation in any one of TCNT_0 to TCNT_2. [4] Read TWCR and then set bit SCC in TWCR to 1 to suppress MTU2-MTU2S synchronous counter clearing*. Here, do not modify the CCE and WRE bit values in TWCR of the MTU2S. MTU2-MTU2S synchronous counter clearing is suppressed in the intervals shown in figure 10.62. Note: * The SCC bit value can be modified during counter operation. However, if a synchronous clearing occurs when bit SCC is modified from 0 to 1, the synchronous clearing may not be suppressed. If a synchronous clearing occurs when bit SCC is modified from 1 to 0, the synchronous clearing may be suppressed. MTU2-MTU2S synchronous counter clearing suppress Stop count operation (MTU2 and MTU2S) [1] Set the following * Complementary PWM mode (MTU2S) * Compare match/input capture operation (MTU2) * Bit WRE in TWCR (MTU2S) [2] Start count operation (MTU2 and MTU2S) [3] Set bit SCC in TWCR (MTU2S) [4] Output waveform control at synchronous counter clearing and synchronous counter clearing suppress Figure 10.63 Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing * Examples of Suppression of MTU2-MTU2S Synchronous Counter Clearing Figures 10.64 to 10.67 show examples of operation in which the MTU2S operates in complementary PWM mode and MTU2-MTU2S synchronous counter clearing is suppressed by setting the SCC bit in TWCR in the MTU2S to 1. In the examples shown in figures 10.64 to 10.67, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 10.56, respectively. In these examples, the WRE bit in TWCR of the MTU2S is set to 1. Rev. 3.00 Jun. 18, 2008 Page 564 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2S) Counters are not cleared TCNT_4 (MTU2S) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.64 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S) Rev. 3.00 Jun. 18, 2008 Page 565 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2S) Counters are not cleared TCNT_4 (MTU2S) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 10.65 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S) Rev. 3.00 Jun. 18, 2008 Page 566 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2S) TCNT_4 (MTU2S) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Counters are not cleared Figure 10.66 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S) Rev. 3.00 Jun. 18, 2008 Page 567 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Bit WRE = 1 Bit SCC = 1 TGRA_3 TCDR MTU2-MTU2S synchronous clearing TGRB_3 TCNT_3 (MTU2S) TCNT_4 (MTU2S) TDDR H'0000 Counters are cleared Positive phase Negative phase Output waveform is active-low. Initial value output is suppressed. Figure 10.67 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S) Rev. 3.00 Jun. 18, 2008 Page 568 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (p) Counter Clearing by TGRA_3 Compare Match In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match. Figure 10.68 illustrates an operation example. Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest) 2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to SYNC4 bits in the timer synchronous register (TSYR) to 1 or the CE0A, CE0B, CE0C, CE0D, CE1A, CE1B, CE1C, and CE1D bits in the timer synchronous clear register (TSYCR) to 1). 3. Do not set the PWM duty value to H'0000. 4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1. Counter cleared by TGRA_3 compare match TGRA_3 TCDR TGRB_3 TDDR H'0000 Output waveform Output waveform Output waveform is active-high. Figure 10.68 Example of Counter Clearing Operation by TGRA_3 Compare Match Rev. 3.00 Jun. 18, 2008 Page 569 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (q) Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 10.69 to 10.72 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 10.69 Example of Output Phase Switching by External Input (1) Rev. 3.00 Jun. 18, 2008 Page 570 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 10.70 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 10.71 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) Rev. 3.00 Jun. 18, 2008 Page 571 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 10.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) (r) A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1. Rev. 3.00 Jun. 18, 2008 Page 572 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (3) Interrupt Skipping in Complementary PWM Mode Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR). Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the timer buffer transfer register (TBTER). For the linkage with buffer registers, refer to description (c), Buffer Transfer Control Linked with Interrupt Skipping, below. A/D converter start requests generated by the A/D converter start request delaying function can also be skipped in coordination with interrupt skipping by making settings in the timer A/D converter request control register (TADCR). For the linkage with the A/D converter start request delaying function, refer to section 10.4.9, A/D Converter Start Request Delaying Function. The setting of the timer interrupt skipping setting register (TITCR) must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. (a) Example of Interrupt Skipping Operation Setting Procedure Figure 10.73 shows an example of the interrupt skipping operation setting procedure. Figure 10.74 shows the periods during which interrupt skipping count can be changed. [1] Set bits T3AEN and T4VEN in the timer interrupt skipping set register (TITCR) to 0 to clear the skipping counter. [2] Specify the interrupt skipping count within the range from 0 to 7 times in bits 3ACOR2 to 3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and enable interrupt skipping through bits T3AEN and T4VEN. Note: The setting of TITCR must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. Interrupt skipping Clear interrupt skipping counter [1] Set skipping count and enable interrupt skipping [2] Figure 10.73 Example of Interrupt Skipping Operation Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 573 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Figure 10.74 Periods during Which Interrupt Skipping Count Can be Changed (b) Example of Interrupt Skipping Operation Figure 10.75 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register (TITCR). Interrupt skipping period TGIA_3 interrupt flag set signal Interrupt skipping period Skipping counter 00 01 02 03 00 01 02 03 TGFA_3 flag Figure 10.75 Example of Interrupt Skipping Operation Rev. 3.00 Jun. 18, 2008 Page 574 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (c) Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER). Figure 10.76 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the temporary register. Figure 10.77 shows an example of operation when buffer transfer is linked with interrupt skipping (BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer register outside the buffer transfer-enabled period. Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register (TITCR). Figure 10.78 shows the relationship between the T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period. Note: This function must always be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never performed. Rev. 3.00 Jun. 18, 2008 Page 575 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 data1 Bit BTE0 in TBTER Bit BTE1 in TBTER Buffer register Data1 (1) Data2 (3) Data* (2) Data2 Temporary register General register Data* Buffer transfer is suppressed Data2 [Legend] (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. Note: * When buffer transfer at the crest is selected. Figure 10.76 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and BTE0 = 1) Rev. 3.00 Jun. 18, 2008 Page 576 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 Buffer transfer-enabled period Buffer register Data* Data1 Data2 Temporary register Data* Data2 General register Note: * Buffer transfer at the crest is selected. The skipping count is set to three. T3AEN is set to 1. Data* Data2 Figure 10.77 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) Skipping counter 3ACNT 0 1 2 3 0 1 2 3 0 Skipping counter 4VCNT 0 1 2 3 0 1 2 3 Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) Note: * The skipping count is set to three. Figure 10.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period Rev. 3.00 Jun. 18, 2008 Page 577 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (4) Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection functions. (a) Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following: * TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored. (b) Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 12, Port Output Enable 2 (POE2), for details. Rev. 3.00 Jun. 18, 2008 Page 578 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR. * Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 10.79 shows an example of procedure for specifying the A/D converter start request delaying function. [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register. * Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE. * Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. A/D converter start request delaying function Set A/D converter start request cycle [1] * Set the timing of transfer from cycle set buffer register * Set linkage with interrupt skipping * Enable A/D converter start request delaying function [2] A/D converter start request delaying function Figure 10.79 Example of Procedure for Specifying A/D Converter Start Request Delaying Function Rev. 3.00 Jun. 18, 2008 Page 579 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) * Basic Operation Example of A/D Converter Start Request Delaying Function Figure 10.80 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting. Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register TADCORA_4 TCNT_4 TADCOBRA_4 A/D converter start request (TRG4AN) (Complementary PWM mode) Figure 10.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation * Buffer Transfer The data in the timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A/D converter start request control register (TADCR_4). * A/D Converter Start Request Delaying Function Linked with Interrupt Skipping A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR). Figure 10.81 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D converter start requests are linked with interrupt skipping. Figure 10.82 shows another example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter start requests are linked with interrupt skipping. Rev. 3.00 Jun. 18, 2008 Page 580 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter 00 00 01 01 02 02 00 00 01 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * When the interrupt skipping count is set to two. (UT4AE/DT4AE = 1) Figure 10.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping Rev. 3.00 Jun. 18, 2008 Page 581 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter 00 00 01 01 02 02 00 00 01 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping UT4AE = 1 DT4AE = 0 Note: * When the interrupt skipping count is set to two. Figure 10.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping Rev. 3.00 Jun. 18, 2008 Page 582 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.10 MTU2-MTU2S Synchronous Operation (1) MTU2-MTU2S Synchronous Counter Start The counters in the MTU2 and MTU2S which operate at different clock systems can be started synchronously by making the TCSYSTR settings in the MTU2. (a) Example of MTU2-MTU2S Synchronous Counter Start Setting Procedure Figure 10.83 shows an example of synchronous counter start setting procedure. [1] Use TSTR registers in the MTU2 and MTU2S and halt the counters used for synchronous start operation. [2] Specify necessary operation with appropriate registers such as TCR and TMDR. Stop count operation [1] [3] In TCSYSTR in the MTU2, set the bits corresponding to the counters to be started synchronously to 1. The TSTRs are automatically set appropriately and the counters start synchronously. Notes: 1. Even if a bit in TCSYSTR corresponding to an operating counter is cleared to 0, the counter will not stop. To stop the counter, clear the corresponding bit in TSTR to 0 directly. 2. To start channels 3 and 4 in reset-synchronized PWM mode or complementary PWM mode, make appropriate settings in TCYSTR according to the TSTR setting for the respective mode. For details, refer to section 10.4.7, Reset-Synchronized PWM Mode, and section 10.4.8, Complementary PWM Mode. MTU2-MTU2S synchronous counter start Set the necessary operation [2] Set TCSYSTR [3] Figure 10.83 Example of Synchronous Counter Start Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 583 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (b) Examples of Synchronous Counter Start Operation Figures 10.84 (1) to (4) show examples of synchronous counter start operation when the clock frequency ratios between the MTU2 and MTU2S are 1:1, 1:2, 1:3, and 1:4, respectively. In these examples, the count clock is set to P/1. MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 H'0001 H'0002 MTU2S/TCNT_4 H'0000 H'0001 H'0002 Figure 10.84 (1) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:1) Rev. 3.00 Jun. 18, 2008 Page 584 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 H'0001 H'0002 H'0002 H'0004 H'0003 MTU2S/TCNT_4 H'0000 H'0001 Figure 10.84 (2) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:2) MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 H'0001 H'0002 H'0004 H'0002 MTU2S/TCNT_4 H'0000 H'0001 H'0003 Figure 10.84 (3) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:3) Rev. 3.00 Jun. 18, 2008 Page 585 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made TCSYSTR H'00 H'51 H'00 MTU2/TSTR H'00 H'42 MTU2S/TSTR H'00 H'80 MTU2/TCNT_1 H'0000 H'0001 H'0002 H'0004 H'0002 MTU2S/TCNT_4 H'0000 H'0001 H'0003 Figure 10.84 (4) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:4) Rev. 3.00 Jun. 18, 2008 Page 586 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (MTU2-MTU2S Synchronous Counter Clearing) The MTU2S counters can be cleared by sources for setting the flags in TSR_0 to TSR_2 in the MTU2 through the TSYCR_3 settings in the MTU2S. (a) Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting Source Figure 10.85 shows an example of procedure for specifying MTU2S counter clearing by MTU2 flag setting source. MTU2S counter clearing by MTU2S flag setting source [1] Use TSTR registers in the MTU2 and MTU2S and halt the counters used for this function. [2] Use TSYCR_3 in the MTU2S to specify the flag setting source to be used for the TCNT_3 and TCNT_4 clearing source. [3] Start TCNT_3 or TCNT_4 in the MTU2S. Stop count operation [1] Set TSYCR_3 [2] [4] Start TCNT_0, TCNT_1, or TCNT_2 in the MTU2. Note: The TSYCR_3 setting is ignored while the counter is stopped. The setting becomes valid after TCNT_3 or TCNT4 is started. Start channel 3 or 4 in MTU2S [3] Start one of channels 0 to 2 in MTU2 [4] Figure 10.85 Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting Source Rev. 3.00 Jun. 18, 2008 Page 587 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (b) Examples of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source Figures 10.86 (1) and 10.86 (2) show examples of MTS2S counter clearing caused by MTU2 flag setting source. TSYCR_3 H'00 H'80 TCNT_0 value in MTU2 TGRA_0 TCNT_0 in MTU2 Compare match between TCNT_0 and TGRA_0 H'0000 TCNT_4 value in MTU2S Time TCNT_4 in MTU2S H'0000 Time Figure 10.86 (1) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (1) TSYCR_3 H'00 H'F0 TCNT_0 value in MTU2 TGRD_0 TGRB_0 TGRC_0 TGRA_0 H'0000 TCNT_4 value in MTU2S Compare match between TCNT_0 and TGR TCNT_0 in MTU2 Time TCNT_4 in MTU2S H'0000 Time Figure 10.86 (2) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (2) Rev. 3.00 Jun. 18, 2008 Page 588 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.11 External Pulse Width Measurement The pulse widths of up to three external input lines can be measured in channel 5. (1) Example of External Pulse Width Measurement Setting Procedure External pulse width measurement [1] Use bits TPSC1 and TPSC0 in TCR to select the counter clock. [2] In TIOR, select the high level or low level for the pulse width measuring condition. [3] Set bits CST in TSTR to 1 to start count operation. Select counter clock [1] Select pulse width measuring conditions [2] Start count operation [3] Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or CMPCLR5W in TCNTCMPCLR to 1. 2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in TIER_5 to 1. 3. The value in TCNT is not captured in TGR. Figure 10.87 Example of External Pulse Width Measurement Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 589 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) Example of External Pulse Width Measurement P TIC5U TCNT5_U 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 Figure 10.88 Example of External Pulse Width Measurement (Measuring High Pulse Width) 10.4.12 Dead Time Compensation By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation. Tdead Upper arm signal Lower arm signal Inverter output detection signal Tdelay Dead time delay signal Figure 10.89 Delay in Dead Time in Complementary PWM Operation Rev. 3.00 Jun. 18, 2008 Page 590 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (1) Example of Dead Time Compensation Setting Procedure Figure 10.90 shows an example of dead time compensation setting procedure by using three counters in channel 5. [1] Place channels 3 and 4 in complementary PWM mode. For details, refer to section 10.4.8, Complementary PWM Mode. Complementary PWM mode [1] [2] Specify the external pulse width measurement function for the target TIOR in channel 5. For details, refer to section 10.4.11, External Pulse Width Measurement. [2] [3] Set bits CST3 and CST4 in TSTR and bits CST5U, CST5V, and CST5W in TSTR2 to 1 to start count operation. Start count operation in channels 3 to 5 [3] [4] When the capture condition specified in TIOR is satisfied, the TCNT_5 value is captured in TGR_5. [5] For U-phase dead time compensation, when an interrupt is generated at the crest (TGIA_3) or trough (TCIV_4) in complementary PWM mode, read the TGRU_5 value, calculate the difference in time in TGRB_3, and write the corrected value to TGRD_3 in the interrupt processing. For the V phase and W phase, read the TGRV_5 and TGRW_5 values and write the corrected values to TGRC_4 and TGRD_4, respectively, in the same way as for U-phase compensation. The TCNT_5 value should be cleared through the TCNTCMPCLR setting or by software. Notes: The PFC settings must be completed in advance. * As an interrupt flag is set under the capture condition specified in TIOR, do not enable interrupt requests in TIER_5. External pulse width measurement TCNT_5 input capture occurs [4] * Interrupt processing [5] Figure 10.90 Example of Dead Time Compensation Setting Procedure Rev. 3.00 Jun. 18, 2008 Page 591 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) MTU ch3/4 ch5 Complementary PWM output DC + Level conversion Dead time delay input W Inverter output monitor signals V U V U W U V W Motor Figure 10.91 Example of Motor Control Circuit Configuration Rev. 3.00 Jun. 18, 2008 Page 592 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 10.92 shows an example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). TGRA_4 Tdead Upper arm signal Lower arm signal Inverter output monitor signal Tdelay Dead time delay signal Up-count/down-count signal (udflg) TCNT[15:0] TGR[15:0] 3DE7 3E5B 3DE7 3E5B 3ED3 3ED3 3F37 3F37 3FAF 3FAF Figure 10.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation Rev. 3.00 Jun. 18, 2008 Page 593 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.5 10.5.1 Interrupt Sources Interrupt Sources and Priorities There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 5, Interrupt Controller (INTC). Table 10.57 lists the MTU2 interrupt sources. Rev. 3.00 Jun. 18, 2008 Page 594 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Table 10.57 MTU2 Interrupts Channel 0 Name Interrupt Source Interrupt DMAC Flag Activation TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFE_0 TGFF_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TGFC_4 TGFD_4 TCFV_4 TGFU_5 TGFV_5 Possible Not possible Not possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Not possible Not possible Not possible Low Priority High TGIA_0 TGRA_0 input capture/compare match TGIB_0 TGRB_0 input capture/compare match TGIC_0 TGRC_0 input capture/compare match TGID_0 TGRD_0 input capture/compare match TCIV_0 TCNT_0 overflow TGIE_0 TGRE_0 compare match TGIF_0 1 TGRF_0 compare match TGIA_1 TGRA_1 input capture/compare match TGIB_1 TGRB_1 input capture/compare match TCIV_1 TCIU_1 TCNT_1 overflow TCNT_1 underflow 2 TGIA_2 TGRA_2 input capture/compare match TGIB_2 TGRB_2 input capture/compare match TCIV_2 TCIU_2 TCNT_2 overflow TCNT_2 underflow 3 TGIA_3 TGRA_3 input capture/compare match TGIB_3 TGRB_3 input capture/compare match TGIC_3 TGRC_3 input capture/compare match TGID_3 TGRD_3 input capture/compare match TCIV_3 TCNT_3 overflow 4 TGIA_4 TGRA_4 input capture/compare match TGIB_4 TGRB_4 input capture/compare match TGIC_4 TGRC_4 input capture/compare match TGID_4 TGRD_4 input capture/compare match TCIV_4 TCNT_4 overflow/underflow 5 TGIU_5 TGRU_5 input capture/compare match TGIV_5 TGRV_5 input capture/compare match TGIW_5 TGRW_5 input capture/compare match TGFW_5 Not possible Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 3.00 Jun. 18, 2008 Page 595 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2. 10.5.2 DMAC Activation The DMAC can be activated by the TGRA input capture/compare match interrupt in each channel. For details, see section 9, Direct Memory Access Controller (DMAC). In the MTU2, a total of five TGRA input capture/compare match interrupts can be used as DMAC activation sources, one each for channels 0 to 4. Rev. 3.00 Jun. 18, 2008 Page 596 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.5.3 A/D Converter Activation The A/D converter can be activated by one of the following three methods in the MTU2. Table 10.58 shows the relationship between interrupt sources and A/D converter start request signals. (1) A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions. * When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1 * When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. (2) A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0 The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. Rev. 3.00 Jun. 18, 2008 Page 597 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (3) A/D Converter Activation by A/D Converter Start Request Delaying Function The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 10.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A/D converter when TRG4BN is generated. Table 10.58 Interrupt Sources and A/D Converter Start Request Signals Target Registers TGRA_0 and TCNT_0 TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 TCNT_4 TGRE_0 and TCNT_0 TADCORA and TCNT_4 TADCORB and TCNT_4 TCNT_4 trough in complementary PWM mode Compare match TRG0N TRG4AN TRG4BN Interrupt Source Input capture/compare match A/D Converter Start Request Signal TRGAN Rev. 3.00 Jun. 18, 2008 Page 598 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.6 10.6.1 (1) Operation Timing Input/Output Timing TCNT Count Timing Figures 10.93 and 94 show TCNT count timing in internal clock operation, and figure 10.95 shows TCNT count timing in external clock operation (normal mode), and figure 10.96 shows TCNT count timing in external clock operation (phase counting mode). P Internal clock TCNT input clock TCNT Falling edge Rising edge N-1 N N+1 Figure 10.93 Count Timing in Internal Clock Operation (Channels 0 to 4) P Internal clock TCNT input clock TCNT Rising edge N-1 N Figure 10.94 Count Timing in Internal Clock Operation (Channel 5) P External clock TCNT input clock TCNT Falling edge Rising edge N-1 N N+1 Figure 10.95 Count Timing in External Clock Operation (Channels 0 to 4) Rev. 3.00 Jun. 18, 2008 Page 599 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P External clock TCNT input clock Rising edge Falling edge TCNT N-1 N N-1 Figure 10.96 Count Timing in External Clock Operation (Phase Counting Mode) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.97 shows output compare output timing (normal mode and PWM mode) and figure 10.98 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). P TCNT input clock N N+1 TCNT TGR Compare match signal TIOC pin N Figure 10.97 Output Compare Output Timing (Normal Mode/PWM Mode) Rev. 3.00 Jun. 18, 2008 Page 600 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 10.98 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) (3) Input Capture Signal Timing Figure 10.99 shows input capture signal timing. P Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10.99 Input Capture Input Signal Timing Rev. 3.00 Jun. 18, 2008 Page 601 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (4) Timing for Counter Clearing by Compare Match/Input Capture Figures 10.100 and 101 show the timing when counter clearing on compare match is specified, and figure 10.102 shows the timing when counter clearing on input capture is specified. P Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 10.100 Counter Clear Timing (Compare Match) (Channels 0 to 4) P Compare match signal Counter clear signal TCNT N-1 H'0000 TGR N Figure 10.101 Counter Clear Timing (Compare Match) (Channel 5) Rev. 3.00 Jun. 18, 2008 Page 602 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 10.102 Counter Clear Timing (Input Capture) (Channels 0 to 5) (5) Buffer Operation Timing Figures 10.103 to 10.105 show the timing in buffer operation. P TCNT Compare match buffer signal TGRA, TGRB TGRC, TGRD n n+1 n N N Figure 10.103 Buffer Operation Timing (Compare Match) Rev. 3.00 Jun. 18, 2008 Page 603 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 10.104 Buffer Operation Timing (Input Capture) P TCNT n H'0000 TCNT clear signal Buffer transfer signal TGRA, TGRB, TGRE TGRC, TGRD, TGRF n N N Figure 10.105 Buffer Transfer Timing (when TCNT Cleared) Rev. 3.00 Jun. 18, 2008 Page 604 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (6) Buffer Transfer Timing (Complementary PWM Mode) Figures 10.106 to 10.108 show the buffer transfer timing in complementary PWM mode. P TCNTS H'0000 TGRD_4 write signal Temporary register transfer signal Buffer register Temporary register n N n N Figure 10.106 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) P TCNTS P-x P H'0000 TGRD_4 write signal Buffer register Temporary register n N n N Figure 10.107 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating) Rev. 3.00 Jun. 18, 2008 Page 605 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P TCNTS P-1 P H'0000 Buffer transfer signal Temporary register Compare register N n N Figure 10.108 Transfer Timing from Temporary Register to Compare Register 10.6.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figures 10.109 and 110 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. P TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag N TGI interrupt Figure 10.109 TGI Interrupt Timing (Compare Match) Rev. 3.00 Jun. 18, 2008 Page 606 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P TCNT input clock TCNT N-1 N TGR Compare match signal TGF flag N TGI interrupt Figure 10.110 TGI Interrupt Timing (Compare Match) (Channel 5) (2) TGF Flag Setting Timing in Case of Input Capture Figures 10.111 and 112 show the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. P Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.111 TGI Interrupt Timing (Input Capture) (Channels 0 to 4) Rev. 3.00 Jun. 18, 2008 Page 607 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.112 TGI Interrupt Timing (Input Capture) (Channel 5) (3) TCFV Flag/TCFU Flag Setting Timing Figure 10.113 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.114 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. P TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 10.113 TCIV Interrupt Setting Timing Rev. 3.00 Jun. 18, 2008 Page 608 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) P TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF TCIU interrupt Figure 10.114 TCIU Interrupt Setting Timing (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figures 10.115 and 116 show the timing for status flag clearing by the CPU, and figure 10.117 shows the timing for status flag clearing by the DMAC. TSR write cycle T1 T2 P Address TSR address Write signal Status flag Interrupt request signal Figure 10.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4) Rev. 3.00 Jun. 18, 2008 Page 609 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TSR write cycle T1 T2 P Address TSR address Write signal Status flag Interrupt request signal Figure 10.116 Timing for Status Flag Clearing by CPU (Channel 5) DMAC read cycle P, B Destination address DMAC write cycle Address Source address Status flag Interrupt request signal Flag clear signal Figure 10.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4) Rev. 3.00 Jun. 18, 2008 Page 610 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7 10.7.1 Usage Notes Module Standby Mode Setting MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 22, Power-Down Modes. 10.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.118 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 10.118 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 3.00 Jun. 18, 2008 Page 611 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: * Channel 0 to 4 f= * Channel 5 f= Where f: P: N: P N Counter frequency Peripheral clock operating frequency TGR set value P (N + 1) 10.7.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.119 shows the timing in this case. TCNT write cycle T1 T2 P Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 10.119 Contention between TCNT Write and Clear Operations Rev. 3.00 Jun. 18, 2008 Page 612 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.120 shows the timing in this case. TCNT write cycle T1 T2 P Address TCNT address Write signal TCNT input clock TCNT N TCNT write data M Figure 10.120 Contention between TCNT Write and Increment Operations Rev. 3.00 Jun. 18, 2008 Page 613 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 10.121 shows the timing in this case. TGR write cycle T1 T2 P Address TGR address Write signal Compare match signal TCNT TGR N N+1 N TGR write data M Figure 10.121 Contention between TGR Write and Compare Match Rev. 3.00 Jun. 18, 2008 Page 614 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data after write. Figure 10.122 shows the timing in this case. TGR write cycle T1 T2 P Address Buffer register address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register N M TGR N Figure 10.122 Contention between Buffer Register Write and Compare Match Rev. 3.00 Jun. 18, 2008 Page 615 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.8 Contention between Buffer Register Write and TCNT Clear When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 10.123 shows the timing in this case. TGR write cycle T1 T2 P Address Buffer register address Write signal TCNT clear signal Buffer transfer signal Buffer register Buffer register write data N M TGR N Figure 10.123 Contention between Buffer Register Write and TCNT Clear Rev. 3.00 Jun. 18, 2008 Page 616 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.9 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 10.124 and 125 show the timing in this case. TGR read cycle T1 T2 P Address TGR address Read signal Input capture signal TGR Internal data bus N M N Figure 10.124 Contention between TGR Read and Input Capture (Channels 0 to 4) TGR read cycle T1 T2 P Address TGR address Read signal Input capture signal TGR Internal data bus N M M Figure 10.125 Contention between TGR Read and Input Capture (Channel 5) Rev. 3.00 Jun. 18, 2008 Page 617 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated. Figures 10.126 and 127 show the timing in this case. TGR write cycle T1 T2 P Address TGR address Write signal Input capture signal TCNT TGR M M Figure 10.126 Contention between TGR Write and Input Capture (Channels 0 to 4) TGR write cycle T1 T2 P Address TGR address Write signal Input capture signal TCNT TGR M TGR write data N Figure 10.127 Contention between TGR Write and Input Capture (Channel 5) Rev. 3.00 Jun. 18, 2008 Page 618 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.11 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.128 shows the timing in this case. Buffer register write cycle T2 T1 P Address Buffer register address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 10.128 Contention between Buffer Register Write and Input Capture 10.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 10.129. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Rev. 3.00 Jun. 18, 2008 Page 619 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT write cycle T1 T2 P Address Write signal TCNT_2 H'FFFE H'FFFF TCNT_2 write data TGRA_2 to TGRB_2 Ch2 comparematch signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 comparematch signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D P N M M M Disabled H'FFFF N N+1 TCNT_2 address Q P Figure 10.129 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection Rev. 3.00 Jun. 18, 2008 Page 620 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 10.130. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Counter operation stop Complementary PWM mode operation Complementary PMW restart Figure 10.130 Counter Value during Complementary PWM Mode Stop 10.7.14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register. Rev. 3.00 Jun. 18, 2008 Page 621 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 10.131 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TCNT3 Point a Buffer transfer with compare match A3 TGRC_3 TGRA_3, TGRC_3 TGRB_3, TGRA_4, TGRB_4 Point b TGRD_3, TGRC_4, TGRD_4 H'0000 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 10.131 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode Rev. 3.00 Jun. 18, 2008 Page 622 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 10.132 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 10.132 Reset Synchronous PWM Mode Overflow Flag Rev. 3.00 Jun. 18, 2008 Page 623 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.133 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. MP TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000 TCFV Figure 10.133 Contention between Overflow and Counter Clearing Rev. 3.00 Jun. 18, 2008 Page 624 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.134 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 MP Address TCNT address Write signal TCNT write data TCNT H'FFFF M TCFV flag Disabled Figure 10.134 Contention between TCNT Write and Overflow 10.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to resetsynchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode. Rev. 3.00 Jun. 18, 2008 Page 625 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00. 10.7.21 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module standby mode. 10.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. Rev. 3.00 Jun. 18, 2008 Page 626 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.8 10.8.1 MTU2 Output Pin Initialization Operating Modes The MTU2 has the following six operating modes. Waveform output is possible in all of these modes. * * * * * * Normal mode (channels 0 to 4) PWM mode 1 (channels 0 to 4) PWM mode 2 (channels 0 to 2) Phase counting modes 1 to 4 (channels 1 and 2) Complementary PWM mode (channels 3 and 4) Reset-synchronized PWM mode (channels 3 and 4) The MTU2 output pin initialization method for each of these modes is described in this section. 10.8.2 Reset Start Operation The MTU2 output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU2 pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC immediately after a reset, the MTU2 output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU2 output pins is completed. Note: Channel number and port notation are substituted for *. Rev. 3.00 Jun. 18, 2008 Page 627 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.8.3 Operation in Case of Re-Setting Due to Error during Operation, Etc. If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU2 has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 10.59. Table 10.59 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (7) (13) (17) (21) (26) PWM1 (2) (8) (14) (18) (22) (27) PWM2 (3) (9) (15) (19) None None PCM (4) (10) (16) (20) None None CPWM (5) (11) None None (23) (24) (28) RPWM (6) (12) None None (25) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode Rev. 3.00 Jun. 18, 2008 Page 628 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. * When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC*D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. * When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. Pin initialization procedures are described below for the numbered combinations in table 10.59. The active level is assumed to be low. Rev. 3.00 Jun. 18, 2008 Page 629 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode Figure 10.135 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 10.135 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Not necessary when restarting in normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 630 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.136 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 10.136 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.135. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 631 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 10.137 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 10.137 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 10.135. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Rev. 3.00 Jun. 18, 2008 Page 632 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 10.138 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 10.138 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 10.135. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev. 3.00 Jun. 18, 2008 Page 633 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.139 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting. 12 6 7 8 9 10 11 1 2 3 4 5 14 15 (16) (17) (18) 13 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0 init (disabled) (0) (normal) (1) (1 init (MTU2) (1) (CPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.139 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.135. 11. 12. 13. 14. 15. 16. 17. 18. Initialize the normal mode waveform generation section with TIOR. Disable operation of the normal mode waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 634 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.140 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting. 1 2 3 4 5 6 RESET TMDR TOER TIOR PFC TSTR (normal) (1) (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 11 12 13 14 15 16 17 18 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.140 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 10.135. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 635 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode Figure 10.141 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 10.141 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 636 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 10.142 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Not initialized (TIOC*B) Figure 10.142 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.141. 11. 12. 13. 14. Not necessary when restarting in PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 637 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 10.143 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Not initialized (cycle register) Figure 10.143 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 10.141. 11. 12. 13. 14. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Rev. 3.00 Jun. 18, 2008 Page 638 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 10.144 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 10.144 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 10.141. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev. 3.00 Jun. 18, 2008 Page 639 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.145 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU2) (1) occurs (PORT) (0) (normal) (0 init (disabled) (0) (CPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 10.145 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.141. 11. 12. 13. 14. 15. 16. 17. 18. 19. Set normal mode for initialization of the normal mode waveform generation section. Initialize the PWM mode 1 waveform generation section with TIOR. Disable operation of the PWM mode 1 waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 640 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.146 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU2) (1) occurs (PORT) (0) (normal) (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 10.146 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 10.145. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 641 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 10.147 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 10.147 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU2 output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Rev. 3.00 Jun. 18, 2008 Page 642 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 10.148 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Not initialized (TIOC*B) Figure 10.148 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.147. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 643 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 10.149 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Not initialized (cycle register) Figure 10.149 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.147. 10. 11. 12. 13. Not necessary when restarting in PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 644 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 10.150 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (PCM) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 10.150 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.147. 10. 11. 12. 13. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 645 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 10.151 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PCM) 3 5 4 6 7 8 9 10 11 12 13 TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (1 init (MTU2) (1) occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 10.151 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, MTU2 output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set in normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 646 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.152 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU2) (1) occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 10.152 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.151. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 647 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 10.153 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 3 5 4 6 7 8 9 10 11 12 13 TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (1 init (MTU2) (1) occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 10.153 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.151. 10. 11. 12. 13. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 648 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 10.154 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 3 5 4 6 7 8 9 10 11 12 13 TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (1 init (MTU2) (1) occurs (PORT) (0) (PCM) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 10.154 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.151. 10. 11. 12. 13. Not necessary when restarting in phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 649 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 10.155 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.155 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU2 output becomes the complementary PWM output initial value.) Set normal mode. (MTU2 output goes low.) Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 650 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.156 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 10.156 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.155. 11. 12. 13. 14. Set PWM mode 1. (MTU2 output goes low.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 651 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.157 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.157 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.155. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. Rev. 3.00 Jun. 18, 2008 Page 652 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.158 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). 1 2 3 5 14 4 15 6 7 8 16 9 17 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.158 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.155. 11. Set normal mode and make new settings. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 653 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.159 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) (RPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.159 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 10.155. 11. Set normal mode. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 654 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (26) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 10.160 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.160 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronized PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. The count operation is started by TSTR. The reset-synchronized PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized PWM output initial value.) Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 655 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (27) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 10.161 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 10.161 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 10.160. 11. 12. 13. 14. Set PWM mode 1. (MTU2 positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 656 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (28) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 10.162 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in complementary PWM mode after resetting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 15 16 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.162 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 10.160. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU2 cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU2 output with the PFC. 16. Operation is restarted by TSTR. Rev. 3.00 Jun. 18, 2008 Page 657 of 1160 REJ09B0191-0300 Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) (29) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 10.163 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in reset-synchronized PWM mode after resetting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.163 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 10.160. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence. Rev. 3.00 Jun. 18, 2008 Page 658 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) This LSI has an on-chip multi-function timer pulse unit 2S (MTU2S) that comprises three 16-bit timer channels. The MTU2S includes channels 3 to 5 of the MTU2. For details, refer to section 10, Multi-Function Timer Pulse Unit 2 (MTU2). The MYU2S operates on M clock (MTU clock) while the MTU2 operates on P clock (peripheral clock) Thus the term P in the MTU2 corresponds to M in the MTU2S. To distinguish from the MTU2, "S" is added to the end of the MTU2S input/output pin and register names. For example, TIOC3A is called TIOC3AS and TGRA_3 is called TGRA_3S in this section. The MTU2S can operate at 100 MHz max. for complementary PWM output functions or at 33 MHz max. for the other functions. Rev. 3.00 Jun. 18, 2008 Page 659 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Table 11.1 MTU2S Functions Item Count clock Channel 3 M/1 M/4 M/16 M/64 M/256 M/1024 TGRA_3S TGRB_3S TGRC_3S TGRD_3S TIOC3AS TIOC3BS TIOC3CS TIOC3DS TGR compare match or input capture Channel 4 M/1 M/4 M/16 M/64 M/256 M/1024 TGRA_4S TGRB_4S TGRC_4S TGRD_4S TIOC4AS TIOC4BS TIOC4CS TIOC4DS TGR compare match or input capture Channel 5 M/1 M/4 M/16 M/64 General registers TGRU_5S TGRV_5S TGRW_5S -- Input pins TIC5US TIC5VS TIC5WS TGR compare match or input capture -- -- -- General registers/ buffer registers I/O pins Counter clear function Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset PWM mode AC synchronous motor drive mode Phase counting mode Buffer operation -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 3.00 Jun. 18, 2008 Page 660 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Item Counter function of compensation for dead time DMAC activation A/D converter start trigger Channel 3 -- Channel 4 -- Channel 5 -- TGRA_3S compare match or input capture -- TGRA_4S compare match or input capture TCNT_4S underflow (trough) in complementary PWM mode -- -- Interrupt sources 5 sources * * * * * Compare match or input capture 3AS Compare match or input capture 3BS Compare match or input capture 3CS Compare match or input capture 3DS Overflow 5 sources * * * * * * Compare match or input capture 4AS Compare match or input capture 4BS Compare match or input capture 4CS Compare match or input capture 4DS Overflow or underflow A/D converter start request at a match between TADCORA_4S and TCNT_4S A/D converter start request at a match between TADCORB_4S and TCNT_4S 3 sources * * * Compare match or input capture 5US Compare match or input capture 5VS Compare match or input capture 5WS A/D converter start request delaying function -- -- * Rev. 3.00 Jun. 18, 2008 Page 661 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Item Interrupt skipping function [Legend] : Possible --: Not possible Channel 3 * Skips TGRA_3S compare match interrupts Channel 4 * Skips TCIV_4S interrupts Channel 5 -- Rev. 3.00 Jun. 18, 2008 Page 662 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) 11.1 Input/Output Pins Table 11.2 Pin Configuration Channel Symbol 3 I/O Function TGRA_3S input capture input/output compare output/PWM output pin TGRB_3S input capture input/output compare output/PWM output pin TGRC_3S input capture input/output compare output/PWM output pin TGRD_3S input capture input/output compare output/PWM output pin TGRA_4S input capture input/output compare output/PWM output pin TGRB_4S input capture input/output compare output/PWM output pin TGRC_4S input capture input/output compare output/PWM output pin TGRD_4S input capture input/output compare output/PWM output pin TIOC3AS I/O TIOC3BS I/O TIOC3CS I/O TIOC3DS I/O 4 TIOC4AS I/O TIOC4BS I/O TIOC4CS I/O TIOC4DS I/O 5 TIC5US TIC5VS TIC5WS Input TGRU_5S input capture input/external pulse input pin Input TGRV_5S input capture input/external pulse input pin Input TGRW_5S input capture input/external pulse input pin Note: For the pin configuration in complementary PWM mode, see table 10.54 in section 10.4.8, Complementary PWM Mode. Rev. 3.00 Jun. 18, 2008 Page 663 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) 11.2 Register Descriptions The MTU2S has the following registers. For details on register addresses and register states during each process, refer to section 24, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 3 is expressed as TCR_3S. Table 11.3 Register Configuration Channel Register Name 3 Timer control register_3S Timer mode register_3S Abbreviation TCR_3S TMDR_3S R/W R/W R/W Initial value H'00 H'00 H'00 H'00 H'00 H'C0 H'0000 Address H'FFFE4200 H'FFFE4202 H'FFFE4204 H'FFFE4205 H'FFFE4208 Access Size 8 8 8 8 8 Timer I/O control register H_3S TIORH_3S R/W Timer I/O control register L_3S TIORL_3S Timer interrupt enable register_3S Timer status register_3S Timer counter_3S Timer general register A_3S Timer general register B_3S Timer general register C_3S Timer general register D_3S Timer buffer operation transfer mode register_3S 4 Timer control register_4S Timer mode register_4S TIER_3S TSR_3S TCNT_3S TGRA_3S TGRB_3S TGRC_3S TGRD_3S TBTM_3S TCR_4S TMDR_4S R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'FFFE422C 8 H'FFFE4210 16 16 16 16 16 8 8 8 8 8 8 H'FFFF H'FFFE4218 H'FFFF H'FFFE421A H'FFFF H'FFFE4224 H'FFFF H'FFFE4226 H'00 H'00 H'00 H'00 H'00 H'00 H'C0 H'0000 H'FFFE4238 H'FFFE4201 H'FFFE4203 H'FFFE4206 H'FFFE4207 H'FFFE4209 Timer I/O control register H_4S TIORH_4S R/W Timer I/O control register L_4S TIORL_4S Timer interrupt enable register_4S Timer status register_4S Timer counter_4S Timer general register A_4S Timer general register B_4S TIER_4S TSR_4S TCNT_4S TGRA_4S TGRB_4S R/W R/W R/W R/W R/W R/W H'FFFE422D 8 H'FFFE4212 16 H'FFFF H'FFFE421C 16 H'FFFF H'FFFE421E 16 Rev. 3.00 Jun. 18, 2008 Page 664 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Channel Register Name 4 Timer general register C_4S Timer general register D_4S Timer buffer operation transfer mode register_4S Timer A/D converter start request control register S Abbreviation TGRC_4S TGRD_4S TBTM_4S TADCRS Initial R/W value Address Access Size 16 R/W H'FFFF H'FFFE4228 R/W H'FFFF H'FFFE422A 16 R/W H'00 H'FFFE4239 8 16 16 16 16 R/W H'0000 H'FFFE4240 R/W H'FFFF H'FFFE4244 R/W H'FFFF H'FFFE4246 R/W H'FFFF H'FFFE4248 Timer A/D converter start TADCORA_ request cycle set register A_4S 4S Timer A/D converter start TADCORB_ request cycle set register B_4S 4S Timer A/D converter start request cycle set buffer register A_4S Timer A/D converter start request cycle set buffer register B_4S 5 Timer control register U_5S Timer control register V_5S Timer control register W_5S TADCOBRA _4S TADCOBRB_ 4S R/W H'FFFF H'FFFE424A 16 TCRU_5S TCRV_5S TCRW_5S R/W H'00 R/W H'00 R/W H'00 R/W H'00 R/W H'00 R/W H'00 R/W H'00 R/W H'00 R/W H'00 H'FFFE4084 H'FFFE4094 8 8 H'FFFE40A4 8 H'FFFE4086 H'FFFE4096 8 8 Timer I/O control register U_5S TIORU_5S Timer I/O control register V_5S TIORV_5S Timer I/O control register W_5S TIORW_5S Timer interrupt enable register_5S Timer status register_5S Timer start register_5S Timer counter U_5S Timer counter V_5S Timer counter W_5S Timer general register U_5S Timer general register V_5S Timer general register W_5S Timer compare match clear register S TIER_5S TSR_5S TSTR_5S TCNTU_5S TCNTV_5S TCNTW_5S TGRU_5S TGRV_5S TGRW_5S TCNTCMPCLRS H'FFFE40A6 8 H'FFFE40B2 8 H'FFFE40B0 8 H'FFFE40B4 8 16 16 R/W H'0000 H'FFFE4080 R/W H'0000 H'FFFE4090 R/W H'0000 H'FFFE40A0 16 R/W H'FFFF H'FFFE4082 R/W H'FFFF H'FFFE4092 16 16 R/W H'FFFF H'FFFE40A2 16 R/W H'00 H'FFFE40B6 8 Rev. 3.00 Jun. 18, 2008 Page 665 of 1160 REJ09B0191-0300 Section 11 Multi-Function Timer Pulse Unit 2S (MTU2S) Channel Register Name Common Timer start register S Timer synchronous register S Timer counter synchronous start register S Timer read/write enable register S Abbreviation TSTRS TSYRS R/W R/W R/W Initial value H'00 H'00 H'00 H'01 H'C0 H'00 H'00 H80 Address H'FFFE4280 H'FFFE4281 H'FFFE4282 H'FFFE4284 H'FFFE420A H'FFFE420E H'FFFE420F Access Size 8 8 8 8 8 8 8 TCSYSTRS R/W TRWERS R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W Common Timer output master enable TOERS to 3 and register S 4 Timer output control register 1S TOCR1S Timer output control register 2S TOCR2S Timer gate control register S Timer cycle control register S TGCRS TCDRS H'FFFE420D 8 16 16 16 16 8 8 8 8 8 8 8 H'FFFF H'FFFE4214 H'FFFF H'FFFE4216 H'0000 H'FFFE4220 Timer dead time data register S TDDRS Timer subcounter S Timer cycle buffer register S Timer interrupt skipping set register S TCNTSS TCBRS TITCRS H'FFFF H'FFFE4222 H'00 H'00 H'00 H'01 H'00 H'00 H'00 H'FFFE4230 H'FFFE4231 H'FFFE4232 H'FFFE4234 H'FFFE4250 H'FFFE4260 H'FFFE4236 Timer interrupt skipping counter TITCNTS S Timer buffer transfer set register S Timer dead time enable register S Timer synchronous clear register S TBTERS TDERS TSYCRS Timer waveform control register TWCRS S Timer output level buffer register S TOLBRS Rev. 3.00 Jun. 18, 2008 Page 666 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Section 12 Port Output Enable 2 (POE2) The port output enable 2 (POE2) can be used to place the high-current pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B, PE14/TIOC4C, PE15/TIOC4D, PD9/TIOC3BS, PD11/TIOC3DS, PD12/TIOC4AS, PD13/TIOC4BS, PD14/TIOC4CS, PD15/TIOC4DS, PD29/TIOC3BS, PD28/TIOC3DS, PD27/TIOC4AS, PD26/TIOC4BS, PD25/TIOC4CS, and PD24/TIOC4DS) and the pins for channel 0 of the MTU2 (PE0/TIOC0A, PE1/TIOC0B, PE2/TIOC0C, and PE3/TIOC0D) in high-impedance state, depending on the change on the POE0 to POE8 input pins and the output status of the high-current pins, or by modifying register settings. It can also simultaneously generate interrupt requests. Rev. 3.00 Jun. 18, 2008 Page 667 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.1 Features * Each of the POE0 to POE8 input pins can be set for falling edge, P/8 x 16, P/16 x 16, or P/128 x 16 low-level sampling. * High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by POE0 to POE8 pin falling-edge or low-level sampling. * High-current pins can be placed in high-impedance state when the high-current pin output levels are compared and simultaneous active-level output continues for one cycle or more. * High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by modifying the POE2 register settings. * Interrupts can be generated by input-level sampling or output-level comparison results. The POE2 has input level detection circuits, output level comparison circuits, and a highimpedance request/interrupt request generating circuit as shown in the block diagram of figure 12.1. Rev. 3.00 Jun. 18, 2008 Page 668 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Figure 12.1 shows a block diagram of the POE2. POECR1, POECR2 TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TIOC3BS TIOC3DS TIOC4AS TIOC4CS TIOC4BS TIOC4DS Output level comparison circuit Output level comparison circuit Output level comparison circuit Output level comparison circuit Output level comparison circuit OCSR1 Output level comparison circuit High-impedance request signal for MTU2 high-current pins High-impedance request signal for MTU2 channel 0 pins High-impedance request signal for MTU2S high-current pins OCSR2 Input level detection circuit POE3 POE2 POE1 POE0 Low level sampling circuit ICSR1 Falling edge detection circuit High-impedance request/interrupt request generating circuit Interrupt request signal Input level detection circuit POE7 POE6 POE5 POE4 Low level sampling circuit Input level detection circuit ICSR3 POE8 Falling edge detection circuit Low level sampling circuit P/8 P/16 P/128 Frequency divider ICSR2 Falling edge detection circuit SPOER [Legend] ICSR1: ICSR2: ICSR3: OCSR1: OCSR2: P Input level control/status register 1 Input level control/status register 2 Input level control/status register 3 Output level control/status register 1 Output level control/status register 2 SPOER: Software port output enable register POECR1: Port output enable control register 1 POECR2: Port output enable control register 2 Figure 12.1 Block Diagram of POE2 Rev. 3.00 Jun. 18, 2008 Page 669 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.2 Input/Output Pins Table 12.1 Pin Configuration Pin Name Port output enable input pins 0 to 3 Symbol POE0 to POE3 I/O Input Function Input request signals to place highcurrent pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B, PE14/TIOC4C, and PE15/TIOC4D) for MTU2 in highimpedance state Input request signals to place highcurrent pins (PD9/TIOC3BS, PD11/TIOC3DS, PD12/TIOC4AS, PD13/TIOC4BS, PD14/TIOC4CS, PD15/TIOC4DS, PD29/TIOC3BS, PD28/TIOC3DS, PD27/TIOC4AS, PD26/TIOC4BS, PD25/TIOC4CS, and PD24/TIOC4DS) for MTU2S in high-impedance state Inputs a request signal to place pins (PE0/TIOC0A, PE1/TIOC0B, PE2/TIOC0C, and PE3/TIOC0D) for channel 0 in MTU2 in highimpedance state Port output enable input pins 4 to 7 POE4 to POE7 Input Port output enable input pin 8 POE8 Input Rev. 3.00 Jun. 18, 2008 Page 670 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Table 12.2 shows output-level comparisons with pin combinations. Table 12.2 Pin Combinations Pin Combination PE9/TIOC3B and PE11/TIOC3D PE12/TIOC4A and PE14/TIOC4C PE13/TIOC4B and PE15/TIOC4D I/O Description Output The high-current pins for the MTU2 are placed in high-impedance state when the pins simultaneously output an active level for one or more cycles of the peripheral clock (P). (In the case of TOCS = 0 in timer output control register 1 (TOCR1) in the MTU2, low level when the output level select P (OLSP) bit is 0, or high level when the OLSP bit is 1. In the case of TOCS = 1, low level when the OLS3N, OLS3P, OLS2N, OLS2P, OLS1N, and OLS1P bits are 0 in TOCR2, or high level when these bits are 1.) This active level comparison is done when the MTU2 output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and highimpedance control can be selected by POE2 registers. PD9/TIOC3BS and PD11/TIOC3DS PD12/TIOC4AS and PD14/TIOC4CS PD13/TIOC4BS and PD15/TIOC4DS PD29/TIOC3BS and PD28/TIOC3DS PD27/TIOC4AS and PD25/TIOC4CS PD26/TIOC4BS and PD24/TIOC4DS Output The high-current pins for the MTU2S are placed in high-impedance state when the pins simultaneously output an active level for one or more cycles of the peripheral clock (P). (In the case of TOCS = 0 in timer output control register 1S (TOCR1S) in the MTU2S, low level when the output level select P (OLSP) bit is 0, or high level when the OLSP bit is 1. In the case of TOCS = 1, low level when the OLS3N, OLS3P, OLS2N, OLS2P, OLS1N, and OLS1P bits are 0 in TOCR2S, or high level when these bits are 1.) This active level comparison is done when the MTU2S output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and highimpedance control can be selected by POE2 registers. Rev. 3.00 Jun. 18, 2008 Page 671 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.3 Register Descriptions The POE2 has the following registers. Table 12.3 Register Configuration Register Name Input level control/status register 1 Output level control/status register 1 Input level control/status register 2 Output level control/status register 2 Input level control/status register 3 Software port output enable register Port output enable control register 1 Port output enable control register 2 Abbreviation ICSR1 OCSR1 ICSR2 OCSR2 ICSR3 SPOER POECR1 POECR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'00 H'7700 Address H'FFFE5000 H'FFFE5002 H'FFFE5004 H'FFFE5006 H'FFFE5008 H'FFFE500A H'FFFE500B H'FFFE500C Access Size 16 16 16 16 16 8 8 16 All POE2 registers are initialized by a power-on reset, but not by a manual reset or in sleep mode, software standby mode, or module standby mode. Rev. 3.00 Jun. 18, 2008 Page 672 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.3.1 Input Level Control/Status Register 1 (ICSR1) ICSR1 is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: 15 14 13 12 11 - 10 - 9 - 8 PIE1 7 6 5 4 3 2 1 0 POE3F POE2F POE1F POE0F POE3M[1:0] POE2M[1:0] POE1M[1:0] POE0M[1:0] 0 0 0 0 Initial value: R/W: R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 0 R 0 R 0 R 0 R/W 0 0 0 0 0 0 0 0 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. Bit 15 Bit Name POE3F Initial Value 0 R/W 1 Description R/(W)* POE3 Flag Indicates that a high impedance request has been input to the POE3 pin. [Clearing conditions] * By writing 0 to POE3F after reading POE3F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR1) By writing 0 to POE3F after reading POE3F = 1 after a high level input to POE3 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR1) When the input set by bits 7 and 6 in ICSR1 occurs at the POE3 pin * [Setting condition] * Rev. 3.00 Jun. 18, 2008 Page 673 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 14 Bit Name POE2F Initial Value 0 R/W 1 Description R/(W)* POE2 Flag Indicates that a high impedance request has been input to the POE2 pin. [Clearing conditions] * By writing 0 to POE2F after reading POE2F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR1) By writing 0 to POE2F after reading POE2F = 1 after a high level input to POE2 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR1) When the input set by bits 5 and 4 in ICSR1 occurs at the POE2 pin * [Setting condition] * 13 POE1F 0 R/(W)*1 POE1 Flag Indicates that a high impedance request has been input to the POE1 pin. [Clearing conditions] * By writing 0 to POE1F after reading POE1F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR1) By writing 0 to POE1F after reading POE1F = 1 after a high level input to POE1 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR1) When the input set by bits 3 and 2 in ICSR1 occurs at the POE1 pin * [Setting condition] * Rev. 3.00 Jun. 18, 2008 Page 674 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 12 Bit Name POE0F Initial Value 0 R/W 1 Description R/(W)* POE0 Flag Indicates that a high impedance request has been input to the POE0 pin. [Clear conditions] * By writing 0 to POE0F after reading POE0F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR1) By writing 0 to POE0F after reading POE0F = 1 after a high level input to POE0 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR1) When the input set by bits 1 and 0 in ICSR1 occurs at the POE0 pin * [Set condition] * 11 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 PIE1 0 R/W Port Interrupt Enable 1 Enables or disables interrupt requests when any one of the POE0F to POE3F bits of the ICSR1 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE3M[1:0] 00 R/W*2 POE3 Mode These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE3 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE3 input has been sampled for 16 P/128 clock pulses and all are low level. Rev. 3.00 Jun. 18, 2008 Page 675 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 5, 4 Bit Name Initial Value R/W R/W* 2 Description POE2 Mode These bits select the input mode of the POE2 pin. 00: Accept request on falling edge of POE2 input 01: Accept request when POE2 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE2 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE2 input has been sampled for 16 P/128 clock pulses and all are low level. POE2M[1:0] 00 3, 2 POE1M[1:0] 00 R/W*2 POE1 Mode These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE1 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE1 input has been sampled for 16 P/128 clock pulses and all are low level. 1, 0 POE0M[1:0] 00 R/W*2 POE0 Mode These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE0 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE0 input has been sampled for 16 P/128 clock pulses and all are low level. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. Rev. 3.00 Jun. 18, 2008 Page 676 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.3.2 Output Level Control/Status Register 1 (OCSR1) OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. Bit: 15 OSF1 14 - 13 - 12 - 11 - 10 - 9 OCE1 8 OIE1 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 0 0 Initial value: R/W: R/(W)*1 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. Bit 15 Initial Bit Name Value OSF1 0 R/W 1 Description R/(W)* Output Short Flag 1 Indicates that any one of the three pairs of MTU2 2phase outputs to be compared has simultaneously become an active level. [Clearing condition] * * By writing 0 to OSF1 after reading OSF1 = 1 When any one of the three pairs of 2-phase outputs has simultaneously become an active level [Setting condition] 14 to 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 OCE1 0 R/W*2 Output Short High-Impedance Enable 1 Specifies whether to place the pins in high-impedance state when the OSF1 bit in OCSR1 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state 8 OIE1 0 R/W Output Short Interrupt Enable 1 Enables or disables interrupt requests when the OSF1 bit in OCSR is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled Rev. 3.00 Jun. 18, 2008 Page 677 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 7 to 0 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. 12.3.3 Input Level Control/Status Register 2 (ICSR2) ICSR2 is a 16-bit readable/writable register that selects the POE4 to POE7 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: 15 14 13 12 11 - 10 - 9 - 8 PIE2 7 6 5 4 3 2 1 0 POE7F POE6F POE5F POE4F POE7M[1:0] POE6M[1:0] POE5M[1:0] POE4M[1:0] 0 0 0 0 Initial value: R/W: R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 0 R 0 R 0 R 0 R/W 0 0 0 0 0 0 0 0 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. Bit 15 Bit Name POE7F Initial Value 0 R/W 1 Description R/(W)* POE7 Flag Indicates that a high impedance request has been input to the POE7 pin. [Clearing conditions] * By writing 0 to POE7F after reading POE7F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR2) By writing 0 to POE7F after reading POE7F = 1 after a high level input to POE7 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR2) When the input condition set by bits 7 and 6 in ICSR2 occurs at the POE7 pin * [Setting condition] * Rev. 3.00 Jun. 18, 2008 Page 678 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 14 Bit Name POE6F Initial Value 0 R/W 1 Description R/(W)* POE6 Flag Indicates that a high impedance request has been input to the POE6 pin. [Clearing conditions] * By writing 0 to POE6F after reading POE6F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR2) By writing 0 to POE6F after reading POE6F = 1 after a high level input to POE6 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR2) When the input condition set by bits 5 and 4 in ICSR2 occurs at the POE6 pin * [Setting condition] * 13 POE5F 0 R/(W)*1 POE5 Flag Indicates that a high impedance request has been input to the POE5 pin. [Clearing conditions] * By writing 0 to POE5F after reading POE5F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR2) By writing 0 to POE5F after reading POE5F = 1 after a high level input to POE5 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR2) When the input condition set by bits 3 and 2 in ICSR2 occurs at the POE5 pin * [Setting condition] * Rev. 3.00 Jun. 18, 2008 Page 679 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 12 Bit Name POE4F Initial Value 0 R/W 1 Description R/(W)* POE4 Flag Indicates that a high impedance request has been input to the POE4 pin. [Clearing conditions] * By writing 0 to POE4F after reading POE4F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR2) By writing 0 to POE4F after reading POE4F = 1 after a high level input to POE4 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR2) When the input condition set by bits 1 and 0 in ICSR2 occurs at the POE4 pin * [Setting condition] * 11 to 9 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 PIE2 0 R/W Port Interrupt Enable 2 Enables or disables interrupt requests when any one of the POE4F to POE7F bits of the ICSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE7M[1:0] 00 R/W*2 POE7 Mode These bits select the input mode of the POE7 pin. 00: Accept request on falling edge of POE7 input 01: Accept request when POE7 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE7 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE7 input has been sampled for 16 P/128 clock pulses and all are at a low level. Rev. 3.00 Jun. 18, 2008 Page 680 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 5, 4 Bit Name Initial Value R/W R/W* 2 Description POE6 Mode These bits select the input mode of the POE6 pin. 00: Accept request on falling edge of POE6 input 01: Accept request when POE6 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE6 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE6 input has been sampled for 16 P/128 clock pulses and all are at a low level. POE6M[1:0] 00 3, 2 POE5M[1:0] 00 R/W*2 POE5 Mode These bits select the input mode of the POE5 pin. 00: Accept request on falling edge of POE5 input 01: Accept request when POE5 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE5 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE5 input has been sampled for 16 P/128 clock pulses and all are at a low level. 1, 0 POE4M[1:0] 00 R/W*2 POE4 Mode These bits select the input mode of the POE4 pin. 00: Accept request on falling edge of POE4 input 01: Accept request when POE4 input has been sampled for 16 P/8 clock pulses and all are at a low level. 10: Accept request when POE4 input has been sampled for 16 P/16 clock pulses and all are at a low level. 11: Accept request when POE4 input has been sampled for 16 P/128 clock pulses and all are at a low level. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. Rev. 3.00 Jun. 18, 2008 Page 681 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.3.4 Output Level Control/Status Register 2 (OCSR2) OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. Bit: 15 OSF2 14 - 13 - 12 - 11 - 10 - 9 OCE2 8 OIE2 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 0 0 Initial value: R/W: R/(W)*1 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. Bit 15 Initial Bit Name Value OSF2 0 R/W 1 Description R/(W)* Output Short Flag 2 Indicates that any one of the three pairs of MTU2S 2phase outputs to be compared has simultaneously become an active level. [Clearing condition] * * By writing 0 to OSF2 after reading OSF2 = 1 When any one of the three pairs of 2-phase outputs has simultaneously become an active level [Setting condition] 14 to 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 OCE2 0 R/W*2 Output Short High-Impedance Enable 2 Specifies whether to place the pins in high-impedance state when the OSF2 bit in OCSR2 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state Rev. 3.00 Jun. 18, 2008 Page 682 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 8 Bit Name OIE2 Initial Value 0 R/W R/W Description Output Short Interrupt Enable 2 Enables or disables interrupt requests when the OSF2 bit in OCSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. 12.3.5 Input Level Control/Status Register 3 (ICSR3) ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the enable/disable of interrupts, and indicates status. Bit: 15 - 14 - 13 - 12 POE8F 11 - 10 - 9 POE8E 8 PIE3 7 - 6 - 5 - 4 - 3 - 2 - 1 0 POE8M[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/(W)*1 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W*2 Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 13 -- Rev. 3.00 Jun. 18, 2008 Page 683 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 12 Bit Name POE8F Initial Value 0 R/W R/(W)* 1 Description POE8 Flag Indicates that a high impedance request has been input to the POE8 pin. [Clearing conditions] * By writing 0 to POE8F after reading POE8F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR3) By writing 0 to POE8F after reading POE8F = 1 after a high level input to POE8 is sampled at P/8, P/16, or P/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR3) When the input condition set by bits 1 and 0 in ICSR3 occurs at the POE8 pin * [Setting condition] * 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 POE8E 0 R/W*2 POE8 High-Impedance Enable Specifies whether to place the pins in high-impedance state when the POE8F bit in ICSR3 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state 8 PIE3 0 R/W Port Interrupt Enable 3 Enables or disables interrupt requests when the POE8 bit in ICSR3 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 684 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 1, 0 Bit Name Initial Value R/W R/W* 2 Description POE8 Mode These bits select the input mode of the POE8 pin. 00: Accept request on falling edge of POE8 input 01: Accept request when POE8 input has been sampled for 16 P/8 clock pulses and all are low level. 10: Accept request when POE8 input has been sampled for 16 P/16 clock pulses and all are low level. 11: Accept request when POE8 input has been sampled for 16 P/128 clock pulses and all are low level. POE8M[1:0] 00 Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Can be modified only once after a power-on reset. 12.3.6 Software Port Output Enable Register (SPOER) SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 MTU2S MTU2 MTU2 HIZ CH0HIZ CH34HIZ Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 3 -- Rev. 3.00 Jun. 18, 2008 Page 685 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 2 Bit Name MTU2SHIZ Initial Value 0 R/W R/W Description MTU2S Output High-Impedance Specifies whether to place the high-current pins for the MTU2S in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] * * Power-on reset By writing 0 to MTU2SHIZ after reading MTU2SHIZ = 1 1: Places the pins in high-impedance state [Setting condition] * 1 MTU2CH0HIZ 0 R/W By writing 1 to MTU2SHIZ MTU2 Channel 0 Output High-Impedance Specifies whether to place the pins for channel 0 in the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] * * Power-on reset By writing 0 to MTU2CH0HIZ after reading MTU2CH0HIZ = 1 1: Places the pins in high-impedance state [Setting condition] * 0 MTU2CH34HIZ 0 R/W By writing 1 to MTU2CH0HIZ MTU2 Channel 3 and 4 Output High-Impedance Specifies whether to place the high-current pins for the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] * * Power-on reset By writing 0 to MTU2CH34HIZ after reading MTU2CH34HIZ = 1 1: Places the pins in high-impedance state [Setting condition] * By writing 1 to MTU2CH34HIZ Rev. 3.00 Jun. 18, 2008 Page 686 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.3.7 Port Output Enable Control Register 1 (POECR1) POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: 7 - 6 - 5 - 4 - 3 2 1 0 MTU2 MTU2 MTU2 MTU2 PE3ZE PE2ZE PE1ZE PE0ZE Initial value: R/W: 0 R 0 R 0 R 0 R 0 0 0 0 R/W* R/W* R/W* R/W* Note: * Can be modified only once after a power-on reset. Bit 7 to 4 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 MTU2PE3ZE 0 R/W* MTU2 PE3 High-Impedance Enable Specifies whether to place the PE3/TIOC0D pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state 2 MTU2PE2ZE 0 R/W* MTU2 PE2 High-Impedance Enable Specifies whether to place the PE2/TIOC0C pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state 1 MTU2PE1ZE 0 R/W* MTU2 PE1 High-Impedance Enable Specifies whether to place the PE1/TIOC0B pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state Rev. 3.00 Jun. 18, 2008 Page 687 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 0 Bit Name MTU2PE0ZE Initial Value 0 R/W R/W* Description MTU2 PE0 High-Impedance Enable Specifies whether to place the PE0/TIOC0A pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state 12.3.8 Port Output Enable Control Register 2 (POECR2) POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins. Bit: 15 - 14 13 12 11 - 10 9 8 7 - 6 5 4 3 - 2 1 0 MTU2 MTU2 MTU2 P1CZE P2CZE P3CZE MTU2S MTU2S MTU2S P1CZE P2CZE P3CZE MTU2S MTU2S MTU2S P4CZE P5CZE P6CZE MTU2S MTU2S MTU2S P7CZE P8CZE P9CZE Initial value: R/W: 0 R 1 1 1 R/W* R/W* R/W* 0 R 1 1 1 R/W* R/W* R/W* 0 R 0 0 0 R/W* R/W* R/W* 0 R 0 0 0 R/W* R/W* R/W* Note: * Can be modified only once after a power-on reset. Bit 15 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 MTU2P1CZE 1 R/W* MTU2 Port 1 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2 high-current PE9/TIOC3B and PE11/TIOC3D pins and to place them in high-impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state Rev. 3.00 Jun. 18, 2008 Page 688 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 13 Bit Name MTU2P2CZE Initial Value 1 R/W R/W* Description MTU2 Port 2 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2 high-current PE12/TIOC4A and PE14/TIOC4C pins and to place them in high-impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 12 MTU2P3CZE 1 R/W* MTU2 Port 3 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2 high-current PE13/TIOC4B and PE15/TIOC4D pins and to place them in high-impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 11 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 MTU2SP1CZE 1 R/W* MTU2S Port 1 High-Impedance Disable This bit should be cleared to 0 when any of bits 6 to 4 and 2 to 0 in POECR2 is set to enable output comparison and high impedance. Otherwise, the pin state may be affected. 9 MTU2SP2CZE 1 R/W* MTU2S Port 2 High-Impedance Disable This bit should be cleared to 0 when any of bits 6 to 4 and 2 to 0 in POECR2 is set to enable output comparison and high impedance. Otherwise, the pin state may be affected. Rev. 3.00 Jun. 18, 2008 Page 689 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 8 Bit Name Initial Value R/W R/W* Description MTU2S Port 3 High-Impedance Disable This bit should be cleared to 0 when any of bits 6 to 4 and 2 to 0 in POECR2 is set to enable output comparison and high impedance. Otherwise, the pin state may be affected. MTU2SP3CZE 1 7 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 MTU2SP4CZE 0 R/W* MTU2S Port 4 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2S high-current PD9/TIOC3BS and PD11/TIOC3DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. Note that when this bit is used, bits 10 to 8 should be cleared to 0. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 5 MTU2SP5CZE 0 R/W* MTU2S Port 5 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2S high-current PD12/TIOC4AS and PD14/TIOC4CS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. Note that when this bit is used, bits 10 to 8 should be cleared to 0. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state Rev. 3.00 Jun. 18, 2008 Page 690 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 4 Bit Name Initial Value R/W R/W* Description MTU2S Port 6 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2S high-current PD13/TIOC4BS and PD15/TIOC4DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. Note that when this bit is used, bits 10 to 8 should be cleared to 0. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state MTU2SP6CZE 0 3 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 MTU2SP7CZE 0 R/W* MTU2S Port 7 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2S high-current PD29/TIOC3BS and PD28/TIOC3DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. Note that when this bit is used, bits 10 to 8 should be cleared to 0. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state Rev. 3.00 Jun. 18, 2008 Page 691 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Bit 1 Bit Name Initial Value R/W R/W* Description MTU2S Port 8 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2S high-current PD27/TIOC4AS and PD25/TIOC4CS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. Note that when this bit is used, bits 10 to 8 should be cleared to 0. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state MTU2SP8CZE 0 0 MTU2SP9CZE 0 R/W* MTU2S Port 9 Output Comparison/High-Impedance Enable Specifies whether to compare output levels for the MTU2S high-current PD26/TIOC4BS and PD24/TIOC4DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. Note that when this bit is used, bits 10 to 8 should be cleared to 0. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state Note: * Can be modified only once after a power-on reset. Rev. 3.00 Jun. 18, 2008 Page 692 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.4 Operation Table 12.4 shows the target pins for high-impedance control and conditions to place the pins in high-impedance state. Table 12.4 Target Pins and Conditions for High-Impedance Control Pins MTU2 high-current pins (PE9/TIOC3B and PE11/TIOC3D) MTU2 high-current pins (PE12/TIOC4A and PE14/TIOC4C) MTU2 high-current pins (PE13/TIOC4B and PE15/TIOC4D) Conditions Input level detection, output level comparison, or SPOER setting Input level detection, output level comparison, or SPOER setting Input level detection, output level comparison, or SPOER setting Detailed Conditions MTU2P1CZE * ((POE0F + POE1F + POE2F + POE3F) + (OSF1 * OCE1) + (MTU2CH34HIZ)) MTU2P2CZE * ((POE0F + POE1F + POE2F + POE3F) + (OSF1 * OCE1) + (MTU2CH34HIZ)) MTU2P3CZE * ((POE0F + POE1F + POE2F + POE3F) + (OSF1 * OCE1) + (MTU2CH34HIZ)) MTU2SP4CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2SP5CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2SP6CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2SP7CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2SP8CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2SP9CZE * ((POE4F + POE5F + POE6F + POE7F) + (OSF2 * OCE2) + (MTU2SHIZ)) MTU2PE0ZE * ((POE8F * POE8E) + (MTU2CH0HIZ)) MTU2S high-current pins Input level detection, (PD9/TIOC3BS and output level comparison, or PD11/TIOC3DS) SPOER setting MTU2S high-current pins Input level detection, (PD12/TIOC4AS and output level comparison, or PD14/TIOC4CS) SPOER setting MTU2S high-current pins Input level detection, (PD13/TIOC4BS and output level comparison, or PD15/TIOC4DS) SPOER setting MTU2S high-current pins Input level detection, (PD29/TIOC3BS and output level comparison, or PD28/TIOC3DS) SPOER setting MTU2S high-current pins Input level detection, (PD27/TIOC4AS and output level comparison, or PD25/TIOC4CS) SPOER setting MTU2S high-current pins Input level detection, (PD26/TIOC4BS and output level comparison, or PD24/TIOC4DS) SPOER setting MTU2 channel 0 pins (PE0/TIOC0A) Input level detection or SPOER setting Rev. 3.00 Jun. 18, 2008 Page 693 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Pins MTU2 channel 0 pins (PE1/TIOC0B) MTU2 channel 0 pins (PE2/TIOC0C) MTU2 channel 0 pins (PE3/TIOC0D) Conditions Input level detection or SPOER setting Input level detection or SPOER setting Input level detection or SPOER setting Detailed Conditions MTU2PE1ZE * ((POE8F * POE8E) + (MTU2CH0HIZ)) MTU2PE2ZE * ((POE8F * POE8E) + (MTU2CH0HIZ)) MTU2PE3ZE * ((POE8F * POE8E) + (MTU2CH0HIZ)) 12.4.1 Input Level Detection Operation If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however, that these high-current and MTU2 pins enter high-impedance state only when general input/output function, MTU2 function, or MTU2S function is selected for these pins. (1) Falling Edge Detection When a change from a high to low level is input to the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Figure 12.2 shows the sample timing after the level changes in input to the POE0 to POE8 pins until the respective pins enter high-impedance state. P P rising edge POE input Falling edge detection PE9/ TIOC3B High-impedance state Note: The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing. Figure 12.2 Falling Edge Detection Rev. 3.00 Jun. 18, 2008 Page 694 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) (2) Low-Level Detection Figure 12.3 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this interval, the low level is not accepted. The timing when the high-current pins enter the high-impedance state after the sampling clock is input is the same in both falling-edge detection and in low-level detection. 8/16/128 clock cycles P Sampling clock POE input PE9/TIOC3B High-impedance state* When low level is sampled at all points When high level is sampled at least once (1) (1) (2) (2) (3) (16) (13) Flag set (POE received) Flag not set Note: * The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing. Figure 12.3 Low-Level Detection Operation 12.4.2 Output-Level Compare Operation Figure 12.4 shows an example of the output-level compare operation for the combination of TIOC3B and TIOC3D. The operation is the same for the other pin combinations. P Low level overlapping detected PE9/ TIOC3B PE11/ TIOC3D High impedance state Figure 12.4 Output-Level Compare Operation Rev. 3.00 Jun. 18, 2008 Page 695 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.4.3 Release from High-Impedance State High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the flags in bits 15 to 12 (POE8F to POE0F) of ICSR1 to ICSR3. However, note that when lowlevel sampling is selected by bits 7 to 0 in ICSR1 to ICSR3, just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to one of the POE0 to POE8 pins and is sampled. High-current pins that have entered high-impedance state due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing the flag in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the high-current pins. Inactive-level outputs can be achieved by setting the MTU2 and MTU2S internal registers. Rev. 3.00 Jun. 18, 2008 Page 696 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) 12.5 Interrupts The POE2 issues a request to generate an interrupt when the specified condition is satisfied during input level detection or output level comparison. Table 12.5 shows the interrupt sources and their conditions. Table 12.5 Interrupt Sources and Conditions Name OEI1 Interrupt Source Output enable interrupt 1 Interrupt Flag POE0F, POE1F, POE2F, POE3F, and OSF1 POE8F POE4F, POE5F, POE6F, POE7F, and OSF2 Condition PIE1 * (POE0F + POE1F + POE2F + POE3F) + OIE1 * OSF1 PIE3 * POE8F PIE2 * (POE4F + POE5F + POE6F + POE7F) + OIE2 * OSF2 OEI2 OEI3 Output enable interrupt 2 Output enable interrupt 3 Rev. 3.00 Jun. 18, 2008 Page 697 of 1160 REJ09B0191-0300 Section 12 Port Output Enable 2 (POE2) Rev. 3.00 Jun. 18, 2008 Page 698 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) Section 13 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer. The CMT has a 16-bit counter, and can generate interrupts at set intervals. 13.1 Features * Independent selection of four counter input clocks at two channels Any of four internal clocks (P/8, P/32, P/128, and P/512) can be selected. * Selection of DMA transfer request or interrupt request generation on compare match by DMAC setting * When not in use, the CMT can be stopped by halting its clock supply to reduce power consumption. Figure 13.1 shows a block diagram of CMT. CMI0 CMI1 P/8 P/32 P/128 P/512 P/8 P/32 P/128 P/512 Control circuit Clock selection Control circuit Clock selection Comparator CMCOR_0 CMCOR_1 CMCSR_0 CMCSR_1 CMCNT_0 Comparator Channel 0 Module bus CMCNT_1 CMSTR Channel 1 Bus interface CMT [Legend] CMSTR: CMCSR: CMCOR: CMCNT: CMI: Peripheral bus Compare match timer start register Compare match timer control/status register Compare match constant register Compare match counter Compare match interrupt Figure 13.1 Block Diagram of CMT Rev. 3.00 Jun. 18, 2008 Page 699 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.2 Register Descriptions The CMT has the following registers. Table 13.1 Register Configuration Channel Common 0 Register Name Compare match timer start register Compare match timer control/ status register_0 Compare match counter_0 Compare match constant register_0 1 Compare match timer control/ status register_1 Compare match counter_1 Compare match constant register_1 Abbreviation CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 R/W R/W Initial Value H'0000 Address Access Size H'FFFEC000 16 H'FFFEC002 16 H'FFFEC004 8, 16 H'FFFEC006 8, 16 H'FFFEC008 16 H'FFFEC00A 8, 16 H'FFFEC00C 8, 16 R/(W)* H'0000 R/W R/W H'0000 H'FFFF R/(W)* H'0000 R/W R/W H'0000 H'FFFF Rev. 3.00 Jun. 18, 2008 Page 700 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.2.1 Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. CMSTR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its previous value in module standby mode. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 STR1 0 STR0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 15 to 2 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 Specifies whether compare match counter_1 operates or is stopped. 0: CMCNT_1 count is stopped 1: CMCNT_1 count is started 0 STR0 0 R/W Count Start 0 Specifies whether compare match counter_0 operates or is stopped. 0: CMCNT_0 count is stopped 1: CMCNT_0 count is started Rev. 3.00 Jun. 18, 2008 Page 701 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables or disables interrupts, and selects the counter input clock. CMCSR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its previous value in module standby mode. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 CMF 6 CMIE 5 - 4 - 3 - 2 - 1 0 CKS[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 R/(W)* R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Note: * Only 0 can be written to clear the flag after 1 is read. Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)* Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing condition] * When 0 is written to CMF after reading CMF = 1 1: CMCNT and CMCOR values match 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF = 1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 702 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) Bit 1, 0 Bit Name CKS[1:0] Initial Value 00 R/W R/W Description Clock Select These bits select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral clock (P). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS[1:0]. 00: P/8 01: P/32 10: P/128 11: P/512 Note: * Only 0 can be written to clear the flag after 1 is read. Rev. 3.00 Jun. 18, 2008 Page 703 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.2.3 Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS[1:0] in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT is initialized to H'0000 when the corresponding count start bit for a channel in the compare match timer start register (CMSTR) is cleared from 1 to 0. CMCNT is initialized to H'0000 by a power-on reset or in software standby mode, but retains its previous value in module standby mode. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 13.2.4 Compare Match Constant Register (CMCOR) CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. CMCOR is initialized to H'FFFF by a power-on reset or in software standby mode, but retains its previous value in module standby mode. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Rev. 3.00 Jun. 18, 2008 Page 704 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.3 13.3.1 Operation Interval Count Operation When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 13.2 shows the operation of the compare match counter. CMCNT value Counter cleared by compare match with CMCOR CMCOR H'0000 Time Figure 13.2 Counter Operation 13.3.2 CMCNT Count Timing One of four clocks (P/8, P/32, P/128, and P/512) obtained by dividing the peripheral clock (P) can be selected with the CKS[1:0] bits in CMCSR. Figure 13.3 shows the timing. Peripheral clock (P) Internal clock Count clock Clock N N Clock N+1 N+1 CMCNT Figure 13.3 Count Timing Rev. 3.00 Jun. 18, 2008 Page 705 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.4 13.4.1 Interrupts Interrupt Sources and DMA Transfer Requests The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt. When both the compare match flag (CMF) and the interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 5, Interrupt Controller (INTC). Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out, another interrupt will be generated. The direct memory access controller (DMAC) can be set to be activated when a compare match interrupt is requested. In this case, an interrupt is not issued to the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the CPU. The CMF bit is automatically cleared to 0 when data is transferred by the DMAC. 13.4.2 Timing of Compare Match Flag Setting When CMCOR and CMCNT match, a compare match signal is generated at the last state in which the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 13.4 shows the timing of CMF bit setting. Rev. 3.00 Jun. 18, 2008 Page 706 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) Peripheral clock (P) Counter clock Clock N+1 CMCNT N 0 CMCOR N Compare match signal Figure 13.4 Timing of CMF Setting 13.4.3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of the DMAC being activated, the CMF bit is automatically cleared to 0 when data is transferred by the DMAC. Rev. 3.00 Jun. 18, 2008 Page 707 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.5 13.5.1 Usage Notes Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 13.5 shows the timing to clear the CMCNT counter. CMCSR write cycle T1 T2 Peripheral clock (P) Address signal CMCNT Internal write signal Counter clear signal CMCNT N H'0000 Figure 13.5 Conflict between Write and Compare Match Processes of CMCNT Rev. 3.00 Jun. 18, 2008 Page 708 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 13.6 shows the timing to write to CMCNT in words. CMCSR write cycle T1 Peripheral clock (P) T2 Address signal CMCNT Internal write signal CMCNT count-up enable signal CMCNT N M Figure 13.6 Conflict between Word-Write and Count-Up Processes of CMCNT Rev. 3.00 Jun. 18, 2008 Page 709 of 1160 REJ09B0191-0300 Section 13 Compare Match Timer (CMT) 13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has priority over the count-up. In this case, the count-up is not performed. The byte data on the other side, which is not written to, is also not counted and the previous contents are retained. Figure 13.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNTH in bytes. CMCSR write cycle T1 Peripheral clock (P) T2 Address signal CMCNTH Internal write signal CMCNT count-up enable signal CMCNTH N M CMCNTL X X Figure 13.7 Conflict between Byte-Write and Count-Up Processes of CMCNT 13.5.4 Compare Match between CMCNT and CMCOR Do not set a same value to CMCNT and CMCOR while the count operation of CMCNT is stopped. Rev. 3.00 Jun. 18, 2008 Page 710 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT), which externally outputs an overflow signal (WDTOVF) on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT can simultaneously generate an internal reset signal for the entire LSI. The WDT is a single channel timer that counts up the clock oscillation settling period when the system leaves software standby mode or the temporary standby periods that occur when the clock frequency is changed. It can also be used as a general watchdog timer or interval timer. 14.1 Features * Can be used to ensure the clock oscillation settling time The WDT is used in leaving software standby mode or the temporary standby periods that occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Outputs WDTOVF signal in watchdog timer mode When the counter overflows in watchdog timer mode, the WDTOVF signal is output externally. It is possible to select whether to reset the LSI internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset type. * Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows. * Choice of eight counter input clocks Eight clocks (P x 1 to P x 1/16384) that are obtained by dividing the peripheral clock can be selected. Rev. 3.00 Jun. 18, 2008 Page 711 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) Figure 14.1 shows a block diagram of the WDT. WDT Standby cancellation Standby control Standby mode Peripheral clock Divider Interrupt request Interrupt control Reset control WRCSR Clock selection Clock selector WDTOVF Internal reset request* Overflow Clock WTCSR WTCNT Bus interface [Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter WRCSR: Watchdog reset control/status register Note: * The internal reset signal can be generated by making a register setting. Figure 14.1 Block Diagram of WDT Rev. 3.00 Jun. 18, 2008 Page 712 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pin Table 14.1 shows the pin configuration of the WDT. Table 14.1 Pin Configuration Pin Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs the counter overflow signal in watchdog timer mode Rev. 3.00 Jun. 18, 2008 Page 713 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.3 Register Descriptions The WDT has the following registers. Table 14.2 Register Configuration Register Name Watchdog timer counter Watchdog timer control/status register Watchdog reset control/status register Note: * Abbreviation R/W WTCNT WTCSR WRCSR R/W R/W R/W Initial Value H'00 H'18 H'1F Address H'FFFE0002 H'FFFE0000 H'FFFE0004 Access Size 16* 16* 16* For the access size, see section 14.3.4, Notes on Register Access. 14.3.1 Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in watchdog timer mode and an interrupt in interval timer mode. WTCNT is initialized to H'00 by a power-on reset caused by the RES pin or in software standby mode. Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read from WTCNT. Note: The method for writing to WTCNT differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 714 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.3.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. WTCSR is initialized to H'18 by a power-on reset caused by the RES pin or in software standby mode. When used to count the clock oscillation settling time for canceling software standby mode, it retains its value after counter overflow. Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from WTCSR. Note: The method for writing to WTCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. Bit: 7 IOVF 6 WT/IT 5 TME 4 - 3 - 2 1 CKS[2:0] 0 0 Initial value: R/W: R/(W) 0 R/W 0 R/W 1 R 1 R 0 R/W 0 R/W 0 R/W Bit 7 Bit Name IOVF Initial Value 0 R/W R/(W) Description Interval Timer Overflow Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: No overflow 1: WTCNT overflow in interval timer mode [Clearing condition] * When 0 is written to IOVF after reading IOVF 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: When the WTCNT overflows in watchdog timer mode, the WDTOVF signal is output externally. If this bit is modified when the WDT is running, the up-count may not be performed correctly. Rev. 3.00 Jun. 18, 2008 Page 715 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) Bit 5 Bit Name TME Initial Value 0 R/W R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled 4, 3 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 2 to 0 CKS[2:0] 000 R/W Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (P). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (P) is 33 MHz. Bits 2 to 0 000: 001: 010: 011: 100: 101: 110: 111: Clock Ratio 1 x P 1/64 x P 1/128 x P 1/256 x P 1/512 x P 1/1024 x P 1/4096 x P 1/16384 x P Overflow Cycle 7.7 s 500 s 1.0 ms 2.0 ms 4.0 ms 8.0 ms 32 ms 128 ms Note: If bits CKS[2:0] are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. Rev. 3.00 Jun. 18, 2008 Page 716 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.3.3 Watchdog Reset Control/Status Register (WRCSR) WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog timer counter (WTCNT) overflow. WRCSR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. WRCSR is initialized to H'1F in software standby mode. Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. Bit: 7 WOVF 6 RSTE 5 RSTS 4 - 3 - 2 - 1 - 0 - 0 Initial value: R/W: R/(W) 0 R/W 0 R/W 1 R 1 R 1 R 1 R 1 R Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W) Description Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode [Clearing condition] * When 0 is written to WOVF after reading WOVF 6 RSTE 0 R/W Reset Enable Selects whether to generate a signal to reset the LSI internally if WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Not reset when WTCNT overflows* 1: Reset when WTCNT overflows Note: * LSI not reset internally, but WTCNT and WTCSR reset within WDT. Rev. 3.00 Jun. 18, 2008 Page 717 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) Bit 5 Bit Name RSTS Initial Value 0 R/W R/W Description Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 to 0 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 14.3.4 Notes on Register Access The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. (1) Writing to WTCNT and WTCSR These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 14.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write Address: H'FFFE0002 15 H'5A 8 7 Write data 0 WTCSR write Address: H'FFFE0000 15 H'A5 8 7 Write data 0 Figure 14.2 Writing to WTCNT and WTCSR Rev. 3.00 Jun. 18, 2008 Page 718 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) (2) Writing to WRCSR WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte transfer or longword transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 14.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit 15 Address: H'FFFE0004 H'A5 8 7 H'00 0 Writing to the RSTE and RSTS bits Address: H'FFFE0004 15 H'5A 8 7 Write data 0 Figure 14.3 Writing to WRCSR (3) Reading from WTCNT, WTCSR, and WRCSR WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address H'FFFE0004. Byte transfer instructions must be used for reading from these registers. Rev. 3.00 Jun. 18, 2008 Page 719 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.4 14.4.1 WDT Usage Canceling Software Standby Mode The WDT can be used to cancel software standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (The WDT does not operate when resets are used for canceling, so keep the RES or MRES pin low until clock oscillation settles.) 1. Before making a transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. After setting the STBY bit of the standby control register (STBCR: see section 22, PowerDown Modes) to 1, the execution of a SLEEP instruction puts the system in software standby mode and clock operation then stops. 4. The WDT starts counting by detecting the edge change of the NMI signal. 5. When the WDT count overflows, the CPG starts supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. Rev. 3.00 Jun. 18, 2008 Page 720 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.4.2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. However, the WDT counts up using the clock after the setting. 3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. 5. The counter stops at the value of H'00. 6. Before changing WTCNT after execution of the frequency change instruction, always confirm that the value of WTCNT is H'00 by reading from WTCNT. Rev. 3.00 Jun. 18, 2008 Page 721 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.4.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR, whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the WDTOVF signal is output externally (figure 14.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 64 x P clock cycles. 5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for 128 x P clock cycles. 6. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin, the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0. Rev. 3.00 Jun. 18, 2008 Page 722 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) WTCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 WDTOVF signal 64 x P clock cycles Internal reset signal* 128 x P clock cycles [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. H'00 written in WTCNT WT/IT = 1 TME = 1 WDTOVF and internal reset generated Time WOVF = 1 H'00 written in WTCNT Figure 14.4 Operation in Watchdog Timer Mode Rev. 3.00 Jun. 18, 2008 Page 723 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.4.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in WTCSR, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting. WTCNT value Overflow Overflow Overflow Overflow H'FF H'00 WT/IT = 0 TME = 1 Time ITI ITI ITI ITI [Legend] ITI: Interval timer interrupt request generation Figure 14.5 Operation in Interval Timer Mode Rev. 3.00 Jun. 18, 2008 Page 724 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.5 Usage Notes Pay attention to the following points when using the WDT in either the interval timer or watchdog timer mode. 14.5.1 Timer Variation After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The shortest such time period is thus one cycle of the peripheral clock, P, while the longest is the result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent incrementation is in accord with the selected frequency division ratio. Accordingly, this time difference is referred to as timer variation. This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation. 14.5.2 Prohibition against Setting H'FF to WTCNT When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred. Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur immediately, regardless of the current clock selection by the CKS[2:0] bits. 14.5.3 Interval Timer Overflow Flag When the value in WTCNT is H'FF, the IOVF flag in WTCSR cannot be cleared. Only clear the IOVF flag when the value in WTCNT has either become H'00 or been changed to a value other than H'FF. Rev. 3.00 Jun. 18, 2008 Page 725 of 1160 REJ09B0191-0300 Section 14 Watchdog Timer (WDT) 14.5.4 System Reset by WDTOVF Signal If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly. Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 14.6. Reset input (Low active) Reset signal to entire system (Low active) RES WDTOVF Figure 14.6 Example of System Reset Circuit Using WDTOVF Signal 14.5.5 Manual Reset in Watchdog Timer Mode When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception handling will be pended until the CPU acquires the bus mastership. However, if the duration from generation of the manual reset to the bus cycle end is equal to or longer than the duration of the internal manual reset activated, the occurrence of the internal manual reset source is ignored instead of being pended, and the manual reset exception handling is not executed. Rev. 3.00 Jun. 18, 2008 Page 726 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Section 15 Serial Communication Interface with FIFO (SCIF) This LSI has a four-channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clocked synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication. 15.1 Features * Asynchronous serial communication: Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, framing, and overrun errors Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RxD level directly from the serial port register when a framing error occurs. * Clocked synchronous serial communication: Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clocked synchronous communication function. There is one serial data communication format. Data length: 8 bits Receive error detection: Overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) Rev. 3.00 Jun. 18, 2008 Page 727 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) * Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFOdata-full interrupt, and receive-error interrupts are requested independently. * When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. * In asynchronous mode, on-chip modem control functions (RTS and CTS) (only channel 3). * The quantity of data in the transmit and receive FIFO data registers and the number of receive errors of the receive data in the receive FIFO data register can be ascertained. * A time-out error (DR) can be detected when receiving in asynchronous mode. Figure 15.1 shows a block diagram of the SCIF. Module data bus Peripheral bus SCFRDR (16 stage) SCFTDR (16 stage) SCSMR SCLSR SCFDR SCFCR SCBRR RxD SCRSR SCTSR SCFSR SCSCR SCSPTR Transmission/reception control Baud rate generator Bus interface P P/4 P/16 P/64 TxD Parity generation Parity check SCK CTS RTS Clock External clock TXI RXI ERI BRI SCIF [Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transmit FIFO data register SCSMR: Serial mode register SCSCR: Serial control register SCFSR: Serial status register SCBRR: Bit rate register SCSPTR: Serial port register SCFCR: FIFO control register SCFDR: FIFO data count set register SCLSR: Line status register Figure 15.1 Block Diagram of SCIF Rev. 3.00 Jun. 18, 2008 Page 728 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the SCIF. Table 15.1 Pin Configuration Channel 0 to 3 Pin Name Serial clock pins Receive data pins Transmit data pins 3 Request to send pin Clear to send pin Symbol SCK0 to SCK3 RxD0 to RxD3 TxD0 to TxD3 RTS3 CTS3 I/O I/O Input Output I/O I/O Function Clock I/O Receive data input Transmit data output Request to send Clear to send Rev. 3.00 Jun. 18, 2008 Page 729 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3 Register Descriptions The SCIF has the following registers. Table 15.2 Register Configuration Channel 0 Register Name Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit FIFO data register_0 Serial status register_0 Receive FIFO data register_0 FIFO control register_0 FIFO data count register_0 Serial port register_0 Line status register_0 1 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit FIFO data register_1 Serial status register_1 Receive FIFO data register_1 FIFO control register_1 FIFO data count register_1 Serial port register_1 Line status register_1 Abbreviation SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 R/W R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* 2 1 2 1 Initial Value Address H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'FFFE8000 H'FFFE8004 H'FFFE8008 H'FFFE800C H'FFFE8010 H'FFFE8014 H'FFFE8018 H'FFFE801C H'FFFE8020 H'FFFE8024 H'FFFE8800 H'FFFE8804 H'FFFE8808 H'FFFE880C H'FFFE8810 H'FFFE8814 H'FFFE8818 H'FFFE881C H'FFFE8820 H'FFFE8824 Access Size 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 Rev. 3.00 Jun. 18, 2008 Page 730 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Channel 2 Register Name Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit FIFO data register_2 Serial status register_2 Receive FIFO data register_2 FIFO control register_2 FIFO data count register_2 Serial port register_2 Line status register_2 Abbreviation SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 SCSMR_3 SCBRR_3 SCSCR_3 SCFTDR_3 SCFSR_3 SCFRDR_3 SCFCR_3 SCFDR_3 SCSPTR_3 SCLSR_3 R/W R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* 2 1 2 1 Initial Value Address H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'FFFE9000 H'FFFE9004 H'FFFE9008 H'FFFE900C H'FFFE9010 H'FFFE9014 H'FFFE9018 H'FFFE901C H'FFFE9020 H'FFFE9024 H'FFFE9800 H'FFFE9804 H'FFFE9808 H'FFFE980C H'FFFE9810 H'FFFE9814 H'FFFE9818 H'FFFE981C H'FFFE9820 H'FFFE9824 Access Size 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 3 Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit FIFO data register_3 Serial status register_3 Receive FIFO data register_3 FIFO control register_3 FIFO data count register_3 Serial port register_3 Line status register_3 Notes: 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that cannot be modified. 2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 731 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.1 Receive Shift Register (SCRSR) SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the receive FIFO data register (SCFRDR). The CPU cannot read or write to SCRSR directly. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - 15.3.2 Receive FIFO Data Register (SCFRDR) SCFRDR is a 16-byte FIFO register that stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When SCFRDR is full of receive data, subsequent serial data is lost. SCFRDR is initialized to an undefined value by a power-on reset. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: R R R R R R R R Rev. 3.00 Jun. 18, 2008 Page 732 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.3 Transmit Shift Register (SCTSR) SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - 15.3.4 Transmit FIFO Data Register (SCFTDR) SCFTDR is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can write to SCFTDR at all times. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. SCFTDR is initialized to an undefined value by a power-on reset. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: W W W W W W W W Rev. 3.00 Jun. 18, 2008 Page 733 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.5 Serial Mode Register (SCSMR) SCSMR specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 C/A 6 CHR 5 PE 4 O/E 3 STOP 2 - 1 0 CKS[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 C/A 0 R/W Communication Mode Selects whether the SCIF operates in asynchronous or clocked synchronous mode. 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length Selects 7-bit or 8-bit data length in asynchronous mode. In the clocked synchronous mode, the data length is always 8 bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted. Rev. 3.00 Jun. 18, 2008 Page 734 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 5 Bit Name PE Initial Value 0 R/W R/W Description Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clocked synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. 4 O/E 0 R/W Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clocked synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity* 1: Odd parity* 2 1 Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Rev. 3.00 Jun. 18, 2008 Page 735 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 3 Bit Name STOP Initial Value 0 R/W R/W Description Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clocked synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character. 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select Select the internal clock source of the on-chip baud rate generator. For further information on the clock source, bit rate register settings, and baud rate, see section 15.3.8, Bit Rate Register (SCBRR). 00: P 01: P/4 10: P/16 11: P/64 Note: P: Peripheral clock Rev. 3.00 Jun. 18, 2008 Page 736 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.6 Serial Control Register (SCSCR) SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 TIE 6 RIE 5 TE 4 RE 3 REIE 2 - 1 0 CKE[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 TIE 0 R/W Transmit Interrupt Enable Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers, and when the TDFE flag in the serial status register (SCFSR) is set to1. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled* Note: * The TXI interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to SCFTDR and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0. Rev. 3.00 Jun. 18, 2008 Page 737 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 6 Bit Name RIE Initial Value 0 R/W R/W Description Receive Interrupt Enable Enables or disables the receive FIFO data full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1. 0: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are disabled 1: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are enabled* Note: * RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. 5 TE 0 R/W Transmit Enable Enables or disables the serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1. Rev. 3.00 Jun. 18, 2008 Page 738 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 4 Bit Name RE Initial Value 0 R/W R/W Description Receive Enable Enables or disables the serial receiver. 0: Receiver disabled* 1: Receiver enabled* 1 2 Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock is detected in clocked synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1. 3 REIE 0 R/W Receive Error Interrupt Enable Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled* Note: * ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERI or BRI interrupt requests are enabled. Set so If SCIF wants to inform INTC of ERI or BRI interrupt requests during DMA transfer. Rev. 3.00 Jun. 18, 2008 Page 739 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 2 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKE[1:0] 00 R/W Clock Enable Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on CKE[1:0], the SCK pin can be used for serial clock output or serial clock input. If serial clock output is set in clocked synchronous mode, set the C/A bit in SCSMR to 1, and then set CKE[1:0]. * Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited * Clocked synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 740 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.7 Serial Status Register (SCFSR) SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive FIFO data register, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. Bit: 15 14 13 12 11 10 9 8 7 ER 6 TEND 5 TDFE 4 BRK 3 FER 2 PER 1 RDF 0 DR PER[3:0] FER[3:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 1 1 0 R/(W)* R/(W)* R/(W)* R/(W)* 0 R 0 R 0 0 R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit 15 to 12 Bit Name PER[3:0] Initial Value 0000 R/W R Description Number of Parity Errors Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 after the ER bit in SCFSR is set, represents the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER[3:0] shows 0000. 11 to 8 FER[3:0] 0000 R Number of Framing Errors Indicate the quantity of data including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to 8 after the ER bit in SCFSR is set, represents the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER[3:0] shows 0000. Rev. 3.00 Jun. 18, 2008 Page 741 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 7 Bit Name ER Initial Value 0 R/W Description R/(W)* Receive Error Indicates the occurrence of a framing error, or of a 1 parity error when receiving data that includes parity.* 0: Receiving is in progress or has ended normally [Clearing conditions] * * ER is cleared to 0 a power-on reset ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER 1: A framing error or parity error has occurred. [Setting conditions] * ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive 2 operation* * ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCFRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked. Rev. 3.00 Jun. 18, 2008 Page 742 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 6 Bit Name TEND Initial Value 1 R/W Description R/(W)* Transmit End Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition] * TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in 1 SCFTDR* 1: End of transmission [Setting conditions] * * * TEND is set to 1 when the chip is a power-on reset TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR) TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted Note: 1. Do not use this bit as a transmit end flag when the DMAC writes data to SCFTDR due to a TXI interrupt request. Rev. 3.00 Jun. 18, 2008 Page 743 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 5 Bit Name TDFE Initial Value 1 R/W Description R/(W)* Transmit FIFO Data Empty Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG[1:0] bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions] * TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written TDFE is cleared to 0 when DMAC is activated by transmit FIFO data empty interrupt (TXI) and write data exceeding the specified transmission trigger number to SCFTDR * 1: The quantity of transmit data in SCFTDR is less than or equal to the specified transmission trigger 1 number* [Setting conditions] * * TDFE is set to 1 by a power-on reset TDFE is set to 1 when the quantity of transmit data in SCFTDR becomes less than or equal to the specified transmission trigger number as a result of transmission Note: 1. Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFDR. Rev. 3.00 Jun. 18, 2008 Page 744 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 4 Bit Name BRK Initial Value 0 R/W Description R/(W)* Break Detection Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions] * * BRK is cleared to 0 when the chip is a power-on reset BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK 1 1: Break signal received* [Setting condition] * BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data Note: 1. When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. 3 FER 0 R Framing Error Indication Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions] * * FER is cleared to 0 when the chip undergoes a power-on reset FER is cleared to 0 when no framing error is present in the next data read from SCFRDR 1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition] * FER is set to 1 when a framing error is present in the next data read from SCFRDR Rev. 3.00 Jun. 18, 2008 Page 745 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 2 Bit Name PER Initial Value 0 R/W R Description Parity Error Indication Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions] * * PER is cleared to 0 when the chip undergoes a power-on reset PER is cleared to 0 when no parity error is present in the next data read from SCFRDR 1: A receive parity error occurred in the next data read from SCFRDR [Setting condition] * PER is set to 1 when a parity error is present in the next data read from SCFRDR Rev. 3.00 Jun. 18, 2008 Page 746 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 1 Bit Name RDF Initial Value 0 R/W Description R/(W)* Receive FIFO Data Full Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG[1:0] bits in the FIFO control register (SCFCR). 0: The quantity of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions] * * RDF is cleared to 0 by a power-on reset, standby mode RDF is cleared to 0 when the SCFRDR is read until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written RDF is cleared to 0 when DMAC is activated by receive FIFO data full interrupt (RXI) and read SCFRDR until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number * 1: The quantity of receive data in SCFRDR is more than the specified receive trigger number [Setting condition] * RDF is set to 1 when a quantity of receive data more than the specified receive trigger number is 1 stored in SCFRDR* Note: 1. As SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read when RDF is 1 becomes the specified receive trigger number. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR. Rev. 3.00 Jun. 18, 2008 Page 747 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 0 Bit Name DR Initial Value 0 R/W Description R/(W)* Receive Data Ready Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clocked synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions] * * * DR is cleared to 0 when the chip undergoes a power-on reset DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written. DR is cleared to 0 when all receive data are read after DMAC is activated by receive FIFO data full interrupt (RXI). 1: Next receive data has not been received [Setting condition] * DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the 1 elapse of 15 ETU from the last stop bit.* Note: 1. This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (ETU: elementary time unit) Note: * Only 0 can be written to clear the flag after 1 is read. Rev. 3.00 Jun. 18, 2008 Page 748 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.8 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS[1:0] bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. Each channel has independent baud rate generator control, so different values can be set in three channels. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The SCBRR setting is calculated as follows: * Asynchronous mode: N= P x 106 - 1 64 x 22n-1 x B * Clocked synchronous mode: N= P x 106 - 1 8 x 22n-1 x B B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 N 255) (The setting must satisfy the electrical characteristics.) P: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 15.3.) Rev. 3.00 Jun. 18, 2008 Page 749 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.3 SCSMR Settings SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS[1] 0 0 1 1 CKS[0] 0 1 0 1 The bit rate error in asynchronous is given by the following formula: Error (%) = P x 106 -1 (N + 1) x B x 64 x 22n-1 x 100 Table 15.4 lists examples of SCBRR settings in asynchronous mode, and table 15.5 lists examples of SCBRR settings in clocked synchronous mode. Table 15.4 Bit Rates and SCBRR Settings (Asynchronous Mode) P (MHz) 5 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 Error (%) n -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) n -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 6.144 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Rev. 3.00 Jun. 18, 2008 Page 750 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) P (MHz) 7.3728 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) n -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 9.8304 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 P (MHz) 10 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 Rev. 3.00 Jun. 18, 2008 Page 751 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) P (MHz) 16 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 24 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 P (MHz) 24.576 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 Error (%) 0.31 0.46 -0.08 0.46 -0.08 0.46 -0.08 0.46 -0.61 -1.03 1.55 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 145 106 214 106 214 106 214 106 53 32 26 33 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0.00 -0.54 Note: Settings with an error of 1% or less are recommended. Rev. 3.00 Jun. 18, 2008 Page 752 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.5 Bit Rates and SCBRR Settings (Clocked Synchronous Mode) P (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2M 5 n -- 3 3 2 1 0 0 0 0 -- 0 -- -- N -- 77 38 77 124 249 124 49 24 -- 4 -- -- n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 0 -- 33 N -- -- 255 125 200 100 200 80 160 80 31 15 7 -- [Legend] Blank: No setting possible --: Setting possible, but error occurs *: Continuous transmission/reception not possible Rev. 3.00 Jun. 18, 2008 Page 753 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 15.7 lists the maximum bit rates in asynchronous mode when the external clock input is used. Table 15.8 lists the maximum bit rates in clocked synchronous mode when the external clock input is used (when tScyc = 12tpcyc*). Note: * Make sure that the electrical characteristics of this LSI and that of a connected LSI are satisfied. Table 15.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 5 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 33 Maximum Bit Rate (bits/s) 156250 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 1031250 n 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 3.00 Jun. 18, 2008 Page 754 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode) P (MHz) 5 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 33 External Input Clock (MHz) 1.2500 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 8.25 Maximum Bit Rate (bits/s) 78125 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 515625 Table 15.8 Maximum Bit Rates with External Clock Input (Clocked Synchronous Mode, tScyc = 12tpcyc) P (MHz) 5 8 16 24 28.7 30 33 External Input Clock (MHz) 0.4166 0.6666 1.3333 2.0000 2.3916 2.5000 2.7500 Maximum Bit Rate (bits/s) 416666.6 666666.6 1333333.3 2000000.0 2391666.6 2500000.0 2750000.0 Rev. 3.00 Jun. 18, 2008 Page 755 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.9 FIFO Control Register (SCFCR) SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 9 RSTRG[2:0] 8 7 6 5 4 3 MCE 2 1 0 LOOP RTRG[1:0] TTRG[1:0] TFRST RFRST Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 11 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 RSTRG[2:0] 000 R/W RTS Output Active Trigger When the quantity of receive data in receive FIFO data register (SCFRDR) becomes more than the number shown below, RTS signal is set to high. 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14 Rev. 3.00 Jun. 18, 2008 Page 756 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 7, 6 Bit Name RTRG[1:0] Initial Value 00 R/W R/W Description Receive FIFO Data Trigger Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO register (SCFRDR) is increased more than the set trigger number shown below. * Asynchronous mode * 00: 1 01: 4 10: 8 11: 14 Clocked synchronous mode 00: 1 01: 2 10: 8 11: 14 Note: In clock synchronous mode, to transfer the receive data using DMAC, set the receive trigger number to 1. If set to other than 1, CPU must read the receive data left in SCFRDR. 5, 4 TTRG[1:0] 00 R/W Transmit FIFO Data Trigger Set the quantity of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR). The TDFE flag is set to 1 when the quantity of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the set trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of empty bytes in SCFTDR when the TDFE flag is set to 1. Rev. 3.00 Jun. 18, 2008 Page 757 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 3 Bit Name MCE Initial Value 0 R/W R/W Description Modem Control Enable Enables modem control signals CTS and RTS. For channels 0 to 2 in clocked synchronous mode, MCE bit should always be 0. 0: Modem signal disabled* 1: Modem signal enabled Note: * Regardless of the input value, CTS level and RTS level have no effect on the transmit operation and the receive operation. 2 TFRST 0 R/W Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset. 1 RFRST 0 R/W Receive FIFO Data Register Reset Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset. 0 LOOP 0 R/W Loop-Back Test Internally connects the transmit output pin (TxD) and receive input pin (RxD) and internally connects the RTS pin and CTS pin and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled Rev. 3.00 Jun. 18, 2008 Page 758 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.10 FIFO Data Count Set Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is initialized to H'0000 by a power on reset. Bit: 15 - 14 - 13 - 12 11 10 T[4:0] 9 8 7 - 6 - 5 - 4 3 2 R[4:0] 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 13 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 to 8 T[4:0] 00000 R T4 to T0 bits indicate the quantity of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. Reserved These bits are always read as 0. The write value should always be 0. 7 to 5 -- All 0 R 4 to 0 R[4:0] 00000 R R4 to R0 bits indicate the quantity of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data. Rev. 3.00 Jun. 18, 2008 Page 759 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.11 Serial Port Register (SCSPTR) SCSPTR controls input/output and data of pins multiplexed to SCIF function. Bits 7 and 6 can control input/output data of RTS pin. Bits 5 and 4 can control input/output data of CTS pin. Bits 3 and 2 can control input/output data of SCK pin. Bits 1 and 0 can input data from RxD pin and output data to TxD pin, so they control break of serial transmitting/receiving. The CPU can always read and write to SCSPTR. SCSPTR is initialized to H'0050 by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IOSPB2DT Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 RTSIO 0 R/W RTS Port Input/Output Indicates input or output of the serial port RTS pin. When the RTS pin is actually used as a port outputting the RTSDT bit value, the MCE bit in SCFCR should be cleared to 0. 0: RTSDT bit value not output to RTS pin 1: RTSDT bit value output to RTS pin 6 RTSDT 1 R/W RTS Port Data Indicates the input/output data of the serial port RTS pin. Input/output is specified by the RTSIO bit. For output, the RTSDT bit value is output to the RTS pin. The RTS pin status is read from the RTSDT bit regardless of the RTSIO bit setting. However, RTS input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level Rev. 3.00 Jun. 18, 2008 Page 760 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 5 Bit Name CTSIO Initial Value 0 R/W R/W Description CTS Port Input/Output Indicates input or output of the serial port CTS pin. When the CTS pin is actually used as a port outputting the CTSDT bit value, the MCE bit in SCFCR should be cleared to 0. 0: CTSDT bit value not output to CTS pin 1: CTSDT bit value output to CTS pin 4 CTSDT 1 R/W CTS Port Data Indicates the input/output data of the serial port CTS pin. Input/output is specified by the CTSIO bit. For output, the CTSDT bit value is output to the CTS pin. The CTS pin status is read from the CTSDT bit regardless of the CTSIO bit setting. However, CTS input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level 3 SCKIO 0 R/W SCK Port Input/Output Indicates input or output of the serial port SCK pin. When the SCK pin is actually used as a port outputting the SCKDT bit value, the CKE[1:0] bits in SCSCR should be cleared to 0. 0: SCKDT bit value not output to SCK pin 1: SCKDT bit value output to SCK pin 2 SCKDT 0 R/W SCK Port Data Indicates the input/output data of the serial port SCK pin. Input/output is specified by the SCKIO bit. For output, the SCKDT bit value is output to the SCK pin. The SCK pin status is read from the SCKDT bit regardless of the SCKIO bit setting. However, SCK input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level Rev. 3.00 Jun. 18, 2008 Page 761 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 1 Bit Name SPB2IO Initial Value 0 R/W R/W Description Serial Port Break Input/Output Indicates input or output of the serial port TxD pin. When the TxD pin is actually used as a port outputting the SPB2DT bit value, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value not output to TxD pin 1: SPB2DT bit value output to TxD pin 0 SPB2DT 0 R/W Serial Port Break Data Indicates the input data of the RxD pin and the output data of the TxD pin used as serial ports. Input/output is specified by the SPB2IO bit. When the TxD pin is set to output, the SPB2DT bit value is output to the TxD pin. The RxD pin status is read from the SPB2DT bit regardless of the SPB2IO bit setting. However, RxD input and TxD output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level 15.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ORER Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Rev. 3.00 Jun. 18, 2008 Page 762 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 15 to 1 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 ORER 0 R/(W)* Overrun Error Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally* [Clearing conditions] * * ORER is cleared to 0 when the chip is a power-on reset ORER is cleared to 0 when 0 is written after 1 is read from ORER. 1 1: An overrun error has occurred*2 [Setting condition] * ORER is set to 1 when the next serial receiving is finished while the receive FIFO is full of 16-byte receive data. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) retains the data before an overrun error has occurred, and the next received data is discarded. When the ORER bit is set to 1, the SCIF cannot continue the next serial reception. Rev. 3.00 Jun. 18, 2008 Page 763 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.4 15.4.1 Operation Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a clocked synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-stage FIFO buffer for both transmission and receptions, reducing the overhead of the CPU, and enabling continuous high-speed communication. Furthermore, channel 3 has RTS and CTS signals to be used as modem control signals. The transmission format is selected in the serial mode register (SCSMR), as shown in table 15.9. The SCIF clock source is selected by the combination of the CKE[1:0] bits in the serial control register (SCSCR), as shown in table 15.10. (1) Asynchronous Mode * Data length is selectable: 7 or 8 bits * Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks. * The number of stored data bytes is indicated for both the transmit and receive FIFO registers. * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the clock of on-chip baud rate generator. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clocked Synchronous Mode * The transmission/reception format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the clock of the on-chip baud rate generator, and outputs this clock to external devices as the synchronous clock. When an external clock is selected, the SCIF operates on the input external synchronous clock not using the on-chip baud rate generator. Rev. 3.00 Jun. 18, 2008 Page 764 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.9 SCSMR Settings and SCIF Communication Formats SCSMR Settings Bit 7 Bit 6 Bit 5 Bit 3 C/A CHR PE STOP Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 x x x Clocked synchronous 8 bits Not set Set 7 bits Not set Set Asynchronous SCIF Communication Format Data Length 8 bits Parity Bit Not set Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None [Legend] x: Don't care Table 15.10 SCSMR and SCSCR Settings and SCIF Clock Source Selection SCSMR Bit 7 C/A 0 SCSCR Bit 1, 0 CKE[1:0] 00 01 10 11 1 0x 10 11 [Legend] x: Don't care Clocked synchronous External Mode Asynchronous Clock Source Internal SCIF Transmit/Receive Clock SCK Pin Function SCIF does not use the SCK pin Outputs a clock with a frequency 16 times the bit rate Inputs a clock with frequency 16 times the bit rate Setting prohibited Internal External Outputs the serial clock Inputs the serial clock Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 765 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 15.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCIF monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit. The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 Parity bit 1 bit or none 1 Stop bit 1 1 Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 15.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) Rev. 3.00 Jun. 18, 2008 Page 766 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) (1) Transmit/Receive Formats Table 15.11 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 15.11 Serial Communication Formats (Asynchronous Mode) SCSMR Bits CHR 0 0 0 0 1 1 1 1 PE STOP 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 START START START START START START START START 2 Serial Transmit/Receive Format and Frame Length 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data [Legend] START: Start bit STOP: Stop bit P: Parity bit (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE[1:0] in the serial control register (SCSCR). For clock source selection, refer to table 15.10, SCSMR and SCSCR Settings and SCIF Clock Source Selection. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal on the SCK pin. The frequency of this output clock is 16 times the desired bit rate. Rev. 3.00 Jun. 18, 2008 Page 767 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) (3) Transmitting and Receiving Data * SCIF Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped. Rev. 3.00 Jun. 18, 2008 Page 768 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.3 shows a sample flowchart for initializing the SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 [1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [1] [4] Sets PFC for external pins used. Set as RxD input at receiving and TxD at transmission. However, no setting for SCK pin is required when CKE[1:0] is 00. In the case when internal synchronous clock output is set, the SCK pin starts outputting the clock at this stage. Set TFRST and RFRST bits in SCFCR to 1 After reading ER, DR, and BRK flags in SCFSR, and each flag in SCLSR, write 0 to clear them Set CKE[1:0] in SCSCR (leaving TIE, RIE, TE, and RE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Set RTRG[1:0], TTRG[1:0], and MCE bits in SCFCR, and clear TFRST and RFRST bits to 0 PFC setting for external pins used SCK, TxD, RxD [2] [3] [4] Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization [5] [5] Set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. Figure 15.3 Sample Flowchart for SCIF Initialization Rev. 3.00 Jun. 18, 2008 Page 769 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) * Transmitting Serial Data (Asynchronous Mode) Figure 15.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear to 0. The quantity of transmit data that can be written is 16 - (transmit trigger set number). [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [3] Break output during serial transmission: To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. Read TDFE flag in SCFSR No TDFE = 1? Yes Write transmit data in SCFTDR, and read 1 from TDFE flag and TEND flag in SCFSR, then clear to 0 [1] All data transmitted? Yes Read TEND flag in SCFSR No [2] TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 No No In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of SCFDR. [3] Clear TE bit in SCSCR to 0 End of transmission Figure 15.4 Sample Flowchart for Transmitting Serial Data Rev. 3.00 Jun. 18, 2008 Page 770 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. Rev. 3.00 Jun. 18, 2008 Page 771 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.5 shows an example of the operation for transmission. Start bit Parity bit Stop bit Start bit Parity bit Stop bit 1 Data Data 1 Serial data 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 Idle state (mark state) TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame TXI interrupt request Figure 15.5 Example of Transmit Operation (8-Bit Data, Parity, 1 Stop Bit) 4. When modem control is enabled in channel 3, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 15.6 shows an example of the operation when modem control is used. Start bit Serial data TxD Parity Stop bit bit Start bit 0 D0 D1 D7 0/1 0 D0 D1 D7 0/1 CTS Drive high before stop bit Figure 15.6 Example of Operation Using Modem Control (CTS) Rev. 3.00 Jun. 18, 2008 Page 772 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) * Receiving Serial Data (Asynchronous Mode) Figures 15.7 and 15.8 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. [1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF flag = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by a receive FIFO data full interrupt (RXI). [3] [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR. Start of reception Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR [1] ER, DR, BRK or ORER = 1? No Yes Error handling [2] Read RDF flag in SCFSR No RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Figure 15.7 Sample Flowchart for Receiving Serial Data Rev. 3.00 Jun. 18, 2008 Page 773 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling * Whether a framing error or parity error has occurred in the receive data that is to be read from the receive FIFO data register (SCFRDR) can be ascertained from the FER and PER bits in the serial status register (SCFSR). * When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored. No ER = 1? Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR to 0 End Figure 15.8 Sample Flowchart for Receiving Serial Data (cont) Rev. 3.00 Jun. 18, 2008 Page 774 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error has not occurred. D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: When a parity error or a framing error occurs, reception is not suspended. 4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 15.9 shows an example of the operation for reception. Rev. 3.00 Jun. 18, 2008 Page 775 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 1 Start bit 0 D0 D1 Data D7 Parity bit 0/1 Stop bit 1 Start bit 0 D0 D1 Data D7 Parity bit 0/1 Stop bit 1 1 Serial data Idle state (mark state) RDF FER RXI interrupt request Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler One frame ERI interrupt request generated by receive error Figure 15.9 Example of SCIF Receive Operation (8-Bit Data, Parity, 1 Stop Bit) 5. When modem control is enabled in channel 3, the RTS signal is output according to the empty situation of SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR exceeds the number set for the RTS output active trigger. Figure 15.10 shows an example of the operation when modem control is used. Start bit Serial data RxD 0 D0 D1 D2 D7 Parity bit 0/1 1 Start bit 0 D0 D1 D7 D1 RTS Figure 15.10 Example of Operation Using Modem Control (RTS) Rev. 3.00 Jun. 18, 2008 Page 776 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.4.3 Operation in Clocked Synchronous Mode In clocked synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCIF transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 15.11 shows the general format in clocked synchronous serial communication. One unit of transfer data (character or frame) * Serial clock * LSB Serial data Don't care MSB Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 15.11 Data Format in Clocked Synchronous Communication Rev. 3.00 Jun. 18, 2008 Page 777 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) In clocked synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clocked synchronous mode, the SCIF receives data by synchronizing with the rising edge of the serial clock. (1) Transmit/Receive Formats The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCIF is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive FIFO data trigger number. (3) Transmitting and Receiving Data * SCIF Initialization (Clocked Synchronous Mode) Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. Rev. 3.00 Jun. 18, 2008 Page 778 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.12 shows a sample flowchart for initializing the SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer After reading ER, DR, and BRK flags in SCFSR, write 0 to clear them Set data transfer format in SCSMR Set CKE[1:0] in SCSCR (leaving TIE, RIE, TE, and RE bits cleared to 0) [1] [1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, RIE, TE, and RE bits to 0. [2] Set the data transfer format in SCSMR. [3] Set CKE[1:0]. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. [5] Sets PFC for external pins used. Set as RxD input at receiving and TxD at transmission. [2] [3] Set value in SCBRR [4] Set RTRG[1:0] and TTRG[1:0] bits in SCFCR, and clear TFRST and RFRST bits to 0 PFC setting for external pins used SCK, TxD, RxD [5] [6] Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE, and REIE bits to enable the TxD, RxD, and SCK pins to be used. When transmitting, the TxD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCK pin at this point. Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization [6] Figure 15.12 Sample Flowchart for SCIF Initialization Rev. 3.00 Jun. 18, 2008 Page 779 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) * Transmitting Serial Data (Clocked Synchronous Mode) Figure 15.13 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0 after reading 1. [1] [2] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE Read TDFE flag in SCFSR No TDFE = 1? Yes Write transmit data to SCFTDR and clear TDFE and TEND flags in SCFSR to 0 after reading 1 No [2] All data transmitted? Yes Read TEND flag in SCFSR No TEND = 1? Yes Clear TE bit in SCSCR to 0 End of transmission Figure 15.13 Sample Flowchart for Transmitting Serial Data Rev. 3.00 Jun. 18, 2008 Page 780 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. If clock output mode is selected, the SCIF outputs eight synchronous clock pulses. If an external clock source is selected, the SCIF outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCIF checks the SCFTDR transmit data at the timing for sending the MSB (bit 7). If data is present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the next frame is started. If there is no data, the TxD pin holds the state after the TEND flag in SCFSR is set to 1 and the MSB (bit 7) is sent. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 15.14 shows an example of SCIF transmit operation. Serial clock LSB Bit 0 MSB Bit 7 Serial data Bit 1 Bit 0 Bit 1 Bit 6 Bit 7 TDFE TEND TXI interrupt request Data written to SCFTDR TXI and TDFE flag cleared interrupt to 0 by TXI interrupt request handler One frame Figure 15.14 Example of SCIF Transmit Operation Rev. 3.00 Jun. 18, 2008 Page 781 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) * Receiving Serial Data (Clocked Synchronous Mode) Figures 15.15 and 15.16 show sample flowcharts for receiving serial data. When switching from asynchronous mode to clocked synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared to 0. Start of reception Read ORER flag in SCLSR ORER = 1? No Read RDF flag in SCFSR No Yes [1] Error handling [2] [1] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 [3] [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by a receive FIFO data full interrupt (RXI). No All data received? Yes Clear RE bit in SCSCR to 0 End of reception [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFRDR. However, the RDF bit is cleared to 0 automatically when an RXI interrupt activates the DMAC to read the data in SCFRDR. Figure 15.15 Sample Flowchart for Receiving Serial Data (1) Rev. 3.00 Jun. 18, 2008 Page 782 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCLSR to 0 End Figure 15.16 Sample Flowchart for Receiving Serial Data (2) Rev. 3.00 Jun. 18, 2008 Page 783 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF synchronizes with serial clock input or output and starts the reception. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If the check is not passed (overrun error is detected), further reception is prevented. 3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI). Figure 15.17 shows an example of SCIF receive operation. Serial clock LSB Serial data Bit 7 Bit 0 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDF ORER RXI interrupt request Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler One frame RXI interrupt request BRI interrupt request by overrun error Figure 15.17 Example of SCIF Receive Operation Rev. 3.00 Jun. 18, 2008 Page 784 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) * Transmitting and Receiving Serial Data Simultaneously (Clocked Synchronous Mode) Figure 15.18 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmission/reception of serial data, after enabling the SCIF for transmission/reception. [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0 after reading 1. The transition of the TDFE flag from 0 to 1 can also be identified by a transmit FIFO data empty Initialization Start of transmission and reception Read TDFE flag in SCFSR interrupt (TXI). No TDFE = 1? Yes Write transmit data to SCFTDR, and clear TDFE and TEND flags in SCFSR to 0 after reading 1 [1] [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [3] SCIF status check and receive data read: Read ORER flag in SCLSR Yes [2] No Read RDF flag in SCFSR Error handling Read SCFSR and check that RDF flag = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by a ORER = 1? receive FIFO data full interrupt (RXI). [4] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0. No RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 [3] No All data received? Yes Clear TE and RE bits in SCSCR to 0 [4] End of transmission and reception Note: When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1. Figure 15.18 Sample Flowchart for Transmitting/Receiving Serial Data Rev. 3.00 Jun. 18, 2008 Page 785 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.5 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive FIFO data full (RXI), and break (BRI). Table 15.12 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed by this TXI interrupt request. At this time, an interrupt request is not sent to the CPU. When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed by this RXI interrupt request. At this time, an interrupt request is not sent to the CPU. The RXI interrupt request caused by the DR flag is generated only in asynchronous mode. When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt without requesting an RXI interrupt. The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data in SCFRDR. Table 15.12 SCIF Interrupt Sources Interrupt Source BRI ERI RXI TXI Description Interrupt initiated by break (BRK) or overrun error (ORER) Interrupt initiated by receive error (ER) DMAC Activation Not possible Not possible Priority on Reset Release High Interrupt initiated by receive FIFO data full (RDF) or Possible data ready (DR) Interrupt initiated by transmit FIFO data empty (TDFE) Possible Low Rev. 3.00 Jun. 18, 2008 Page 786 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.6 Usage Notes Note the following when using the SCIF. 15.6.1 SCFTDR Writing and TDFE Flag The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG[1:0] in the FIFO control register (SCFCR). After the TDFE flag is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE flag clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). 15.6.2 SCFRDR Reading and RDF Flag The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG[1:0] in the FIFO control register (SCFCR). After RDF flag is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. The RDF flag should therefore be cleared to 0 after being read as 1 after reading the number of the received data in the receive FIFO data register (SCFRDR) which is less than the trigger number. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). Rev. 3.00 Jun. 18, 2008 Page 787 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.6.3 Restriction on DMAC Usage 1. When the DMAC writes data to SCFTDR due to a TXI interrupt request, the state of the TEND flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end flag in such a case. 2. When a channel is being used in full-duplex transmission, in which the DMAC is on the transmit side and the CPU on the receive side, the RDF or DR flag in the serial status register (SCFSR) could be cleared after these flags are set and receive data is read from the receive FIFO data register (SCFRDR). 3. When a channel is being used in full-duplex transmission, in which the DMAC is on the receive side and the CPU on the transmit side, the TDFE or TEND flag in the serial status register (SCFSR) could be cleared after these flags are set and transmit data is written to the transmit FIFO data register (SCFTDR). 15.6.4 Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF receiver continues to operate. 15.6.5 Sending a Break Signal The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work. During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and SPB2DT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin. Rev. 3.00 Jun. 18, 2008 Page 788 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) 15.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.19. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RxD) Synchronization sampling timing Start bit +7.5 clocks D0 D1 Data sampling timing Figure 15.19 Receive Data Sampling Timing in Asynchronous Mode Rev. 3.00 Jun. 18, 2008 Page 789 of 1160 REJ09B0191-0300 Section 15 Serial Communication Interface with FIFO (SCIF) The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = (0.5 - D - 0.5 1 ) - (L - 0.5) F - (1 + F) x 100 % 2N N Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 3.00 Jun. 18, 2008 Page 790 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Section 16 I2C Bus Interface 3 (IIC3) The I2C bus interface 3 conforms to and provides a subset of the Philips I2C (Inter-IC) bus interface functions. However, the configuration of the registers that control the I2C bus differs partly from the Philips register configuration. 16.1 Features * Selection of I2C format or clocked synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. I2C bus format: * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * The direct memory access controller (DMAC) can be activated by a transmit-data-empty request or receive-data-full request to transfer data. * Direct bus drive Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive function is selected. Clocked synchronous serial format: * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error * The direct memory access controller (DMAC) can be activated by a transmit-data-empty request or receive-data-full request to transfer data. Rev. 3.00 Jun. 18, 2008 Page 791 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Figure 16.1 shows a block diagram of the I2C bus interface 3. Transfer clock generation circuit SCL Output control Transmission/ reception control circuit ICCR1 ICCR2 ICMR Noise filter ICDRT SAR SDA Output control ICDRS Noise canceler Address comparator ICDRR NF2CYC Bus state decision circuit Arbitration decision circuit [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: NF2CYC: ICIER ICSR I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register NF2CYC register Interrupt generator Figure 16.1 Block Diagram of I2C Bus Interface 3 Rev. 3.00 Jun. 18, 2008 Page 792 of 1160 REJ09B0191-0300 Peripheral bus Interrupt request Section 16 I C Bus Interface 3 (IIC3) 2 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the I2C bus interface 3. Table 16.1 Pin Configuration Pin Name Serial clock Serial data Symbol SCL SDA I/O I/O I/O Function I2C serial clock input/output I2C serial data input/output Figure 16.2 shows an example of I/O pin connections to external circuits. PVcc* PVcc* SCL in SCL out SCL SCL SDA in SDA out SDA SDA SCL SDA (Master) SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Note: * Turn on/off PVcc for the I2C bus power supply and for this LSI simultaneously. Figure 16.2 External Circuit Connections of I/O Pins Rev. 3.00 Jun. 18, 2008 Page 793 of 1160 REJ09B0191-0300 SCL SDA Section 16 I C Bus Interface 3 (IIC3) 2 16.3 Register Descriptions The I2C bus interface 3 has the following registers. Table 16.2 Register Configuration Register Name I2C bus control register 1 I C bus control register 2 I C bus mode register I C bus interrupt enable register I C bus status register Slave address register I C bus transmit data register I2C bus receive data register NF2CYC register 2 2 2 2 2 Abbreviation ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR NF2CYC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'7D H'38 H'00 H'00 H'00 H'FF H'FF H'00 Address H'FFFEE000 H'FFFEE001 H'FFFEE002 H'FFFEE003 H'FFFEE004 H'FFFEE005 H'FFFEE006 H'FFFEE007 H'FFFEE008 Access Size 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jun. 18, 2008 Page 794 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.1 I2C Bus Control Register 1 (ICCR1) ICCR1 is an 8-bit readable/writable register that enables or disables the I2C bus interface 3, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. ICCR1 is initialized to H'00 by a power-on reset. Bit: 7 ICE 6 RCVD 5 MST 4 TRS 3 2 1 0 CKS[3:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I C Bus Interface 3 Enable 0: This module is halted. 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 2 6 RCVD 0 R/W Reception Disable Enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception Rev. 3.00 Jun. 18, 2008 Page 795 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Bit 5 4 Bit Name MST TRS Initial Value 0 0 R/W R/W R/W Description Master/Slave Select Transmit/Receive Select In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. When seven bits after the start condition is issued in slave receive mode match the slave address set to SAR and the 8th bit is set to 1, TRS is automatically set to 1. If an overrun error occurs in master receive mode with the clocked synchronous serial format, MST is cleared and the mode changes to slave receive mode. Operating modes are described below according to MST and TRS combination. When clocked synchronous serial format is selected and MST = 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode 2 3 to 0 CKS[3:0] 0000 R/W Transfer Clock Select These bits should be set according to the necessary transfer rate (table 16.3) in master mode. Rev. 3.00 Jun. 18, 2008 Page 796 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Table 16.3 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 P = 16.7 MHz 595 kHz 417 kHz 347 kHz 260 kHz 208 kHz 167 kHz 149 kHz 130 kHz 149 kHz 104 kHz 86.8 kHz 65.1 kHz 52.1 kHz 41.7 kHz 37.2 kHz 32.6 kHz P = 20.0 MHz 714 kHz 500 kHz 417 kHz 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz Transfer Rate P = 25.0 MHz 893 kHz 625 kHz 521 kHz 391 kHz 313 kHz 250 kHz 223 kHz 195 kHz 223 kHz 156 kHz 130 kHz 97.7 kHz 78.1 kHz 62.5 kHz 55.8 kHz 48.8 kHz P = 30.0 MHz 1071 kHz 750 kHz 625 kHz 469 kHz 375 kHz 300 kHz 268 kHz 234 kHz 268 kHz 188 kHz 156 kHz 117 kHz 93.8 kHz 75.0 kHz 67.0 kHz 58.6 kHz P = 33.3 MHz 1189 kHz 833 kHz 694 kHz 520 kHz 416 kHz 333 kHz 297 kHz 260 kHz 297 kHz 208 kHz 173 kHz 130 kHz 104 kHz 83.3 kHz 74.3 kHz 65.0 kHz CKS3 CKS2 CKS1 CKS0 Clock 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 P/28 P/40 P/48 P/64 P/80 P/100 P/112 P/128 P/112 P/160 P/192 P/256 P/320 P/400 P/448 P/512 Note: The settings should satisfy external specifications. Rev. 3.00 Jun. 18, 2008 Page 797 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.2 I2C Bus Control Register 2 (ICCR2) ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus. ICCR2 is initialized to H'7D by a power-on reset. Bit: 7 BBSY 6 SCP 5 4 3 2 - 1 IICRST 0 - SDAO SDAOP SCLO Initial value: R/W: 0 R/W 1 R/W 1 R/W 1 R/W 1 R 1 R 0 R/W 1 R Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy Enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial format, this 2 bit is always read as 0. With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. 2 6 SCP 1 R/W Start/Stop Issue Condition Disable Controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. Even if 1 is written to this bit, the data will not be stored. Rev. 3.00 Jun. 18, 2008 Page 798 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Bit 5 Bit Name SDAO Initial Value 1 R/W R/W Description SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance). 4 SDAOP 1 R/W SDAO Write Protect Controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0. This bit is always read as 1. 3 SCLO 1 R SCL Output Level Monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. 2 1 R Reserved This bit is always read as 1. The write value should always be 1. 1 IICRST 0 R/W IIC Control Part Reset Resets bits BC[2:0] in ICMR and IIC3 internal circuits. If this bit is set to 1 when hang-up occurs because of 2 communication failure during I C bus operation, bits BC[2:0] in ICMR and IIC3 internal circuits can be reset. 0 1 R Reserved This bit is always read as 1. The write value should always be 1. Rev. 3.00 Jun. 18, 2008 Page 799 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.3 I2C Bus Mode Register (ICMR) ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. ICMR is initialized to H'38 by a power-on reset. Bits BC[2:0] are initialized to H'0 by the IICRST bit in ICCR2. Bit: 7 MLS 6 - 5 - 4 - 3 BCWP 2 1 BC[2:0] 0 Initial value: R/W: 0 R/W 0 R 1 R 1 R 1 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 2 6 0 R Reserved This bit is always read as 0. The write value should always be 0. 5, 4 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 3 BCWP 1 R/W BC Write Protect Controls the BC[2:0] modifications. When modifying the BC[2:0] bits, this bit should be cleared to 0. In clocked synchronous serial mode, the BC[2:0] bits should not be modified. 0: When writing, values of the BC[2:0] bits are set. 1: When reading, 1 is always read. When writing, settings of the BC[2:0] bits are invalid. Rev. 3.00 Jun. 18, 2008 Page 800 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Bit 2 to 0 Bit Name BC[2:0] Initial Value 000 R/W R/W Description Bit Counter These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits 2 is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. Should be made between transfer frames. If these bits are set to a value other than B'000, the setting should be made while the SCL pin is low. The value returns to B'000 at the end of a data transfer, including the acknowledge bit. And the value becomes B'111 automatically after the stop condition detection. These bits are cleared by a power-on reset and in software standby mode and module standby mode. These bits are also cleared by setting the IICRST bit of ICCR2 to 1. With the clocked synchronous serial format, these bits should not be modified. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits 2 Clocked Synchronous Serial Format 000: 8 bits 001: 1 bit 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 3.00 Jun. 18, 2008 Page 801 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits received. ICIER is initialized to H'00 by a power-on reset. Bit: 7 TIE 6 TEIE 5 RIE 4 NAKIE 3 STIE 2 1 0 ACKE ACKBR ACKBT Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1 or 0, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable Enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable Enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) in the clocked synchronous format when receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) are disabled. 1: Receive data full interrupt request (RXI) are enabled. Rev. 3.00 Jun. 18, 2008 Page 802 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Bit 4 Bit Name NAKIE Initial Value 0 R/W R/W Description NACK Receive Interrupt Enable Enables or disables the NACK detection interrupt request (NAKI) and the overrun error (OVE set in ICSR) interrupt request (ERI) in the clocked synchronous format when the NACKF or AL/OVE bit in ICSR is set. NAKI can be canceled by clearing the NACKF, AL/OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled. 3 STIE 0 R/W Stop Condition Detection Interrupt Enable Enables or disables the stop condition detection interrupt request (STPI) when the STOP bit in ICSR is set. 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled. 2 ACKE 0 R/W Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted. 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. This bit can be canceled by setting the BBSY bit in ICCR2 to 1. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0 ACKBT 0 R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. Rev. 3.00 Jun. 18, 2008 Page 803 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.5 I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status. ICSR is initialized to H'00 by a power-on reset. Bit: 7 TDRE 6 TEND 5 4 3 2 1 AAS 0 ADZ RDRF NACKF STOP AL/OVE Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Clearing conditions] * * * * * * When 0 is written in TDRE after reading TDRE = 1 When data is written to ICDRT When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When the start condition (including retransmission) is issued When slave mode is changed from receive mode to transmit mode [Setting conditions] 6 TEND 0 R/W Transmit End [Clearing conditions] * * * * When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clocked synchronous serial format 2 [Setting conditions] Rev. 3.00 Jun. 18, 2008 Page 804 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Bit 5 Bit Name RDRF Initial Value 0 R/W R/W Description Receive Data Full [Clearing conditions] * * * When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read When a receive data is transferred from ICDRS to ICDRR [Setting condition] 4 NACKF 0 R/W No Acknowledge Detection Flag [Clearing condition] * When 0 is written in NACKF after reading NACKF =1 When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Setting condition] * 3 STOP 0 R/W Stop Condition Detection Flag [Clearing condition] * * * When 0 is written in STOP after reading STOP = 1 In master mode, when a stop condition is detected after frame transfer In slave mode, when the slave address in the first byte after the general call and detecting start condition matches the address set in SAR, and then the stop condition is detected [Setting conditions] Rev. 3.00 Jun. 18, 2008 Page 805 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Bit 2 Bit Name AL/OVE Initial Value 0 R/W R/W Description Arbitration Lost Flag/Overrun Error Flag Indicates that arbitration was lost in master mode with 2 the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface 3 detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been occupied by another master. [Clearing condition] * When 0 is written in AL/OVE after reading AL/OVE =1 If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clocked synchronous format while RDRF = 1 [Setting conditions] * * * 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA[6:0] in SAR. [Clearing condition] * * * When 0 is written in AAS after reading AAS = 1 When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. 2 [Setting conditions] 0 ADZ 0 R/W General Call Address Recognition Flag This bit is valid in slave receive mode with the I C bus format. [Clearing condition] * * When 0 is written in ADZ after reading ADZ = 1 When the general call address is detected in slave receive mode [Setting condition] Rev. 3.00 Jun. 18, 2008 Page 806 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.6 Slave Address Register (SAR) SAR is an 8-bit readable/writable register that selects the communications format and sets the slave address. In slave mode with the I2C bus format, if the upper seven bits of SAR match the upper seven bits of the first frame received after a start condition, this module operates as the slave device. SAR is initialized to H'00 by a power-on reset. Bit: 7 6 5 4 SVA[6:0] 3 2 1 0 FS Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 1 Bit Name SVA[6:0] Initial Value 0000000 R/W R/W Description Slave Address These bits set a unique address in these bits, differing form the addresses of other slave devices 2 connected to the I C bus. 0 FS 0 R/W Format Select 0: I C bus format is selected 1: Clocked synchronous serial format is selected 2 16.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Rev. 3.00 Jun. 18, 2008 Page 807 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.8 I2C Bus Receive Data Register (ICDRR) ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. ICDRR is initialized to H'FF by a power-on reset. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 16.3.9 I2C Bus Shift Register (ICDRS) ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Rev. 3.00 Jun. 18, 2008 Page 808 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.3.10 NF2CYC Register (NF2CYC) NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the SCL and SDA pins. For details of the noise filter, see section 16.4.7, Noise Filter. NF2CYC is initialized to H'00 by a power-on reset. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 NF2 CYC Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 7 to 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 NF2CYC 0 R/W Noise Filtering Range Select 0: The noise less than one cycle of the peripheral clock can be filtered out 1: The noise less than two cycles of the peripheral clock can be filtered out Rev. 3.00 Jun. 18, 2008 Page 809 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4 Operation The I2C bus interface 3 can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 16.4.1 I2C Bus Format Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of eight bits. (a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1) (b) I2C bus format (Start condition retransmission, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1) Figure 16.3 I2C Bus Formats SDA SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A P Figure 16.4 I2C Bus Timing [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. Rev. 3.00 Jun. 18, 2008 Page 810 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 16.5 and 16.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Also, set bits CKS[3:0] in ICCR1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. Rev. 3.00 Jun. 18, 2008 Page 811 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 SCL (Master output) SDA (Master output) 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 1 Bit 7 2 Bit 6 Slave address SDA (Slave output) R/W A TDRE TEND ICDRT Address + R/W Data 1 Data 2 ICDRS Address + R/W Data 1 User [2] Instruction of start processing condition issuance [4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte) Figure 16.5 Master Transmit Mode Operation Timing (1) SCL (Master output) SDA (Master output) SDA (Slave output) 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 A A/A TDRE TEND ICDRT Data n ICDRS Data n User [5] Write data to ICDRT processing [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 16.6 Master Transmit Mode Operation Timing (2) Rev. 3.00 Jun. 18, 2008 Page 812 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 16.7 and 16.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICSR is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode. Note: If only one byte is received, read ICDRR (dummy-read) after the RCVD bit in ICCR1 is set. Rev. 3.00 Jun. 18, 2008 Page 813 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) Master receive mode 9 1 2 3 4 5 6 7 8 9 A 1 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 16.7 Master Receive Mode Operation Timing (1) SCL (Master output) SDA (Master output) SDA (Slave output) RDRF RCVD ICDRS Data n 9 A 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data n-1 ICDRR User processing Data n-1 [6] Issue stop condition Data n [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [8] Set slave receive mode Figure 16.8 Master Receive Mode Operation Timing (2) Rev. 3.00 Jun. 18, 2008 Page 814 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 16.9 and 16.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS bit in ICCR1 and the TDRE bit in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened. 5. Clear TDRE. Rev. 3.00 Jun. 18, 2008 Page 815 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) Slave transmit mode 9 1 2 3 4 5 6 7 8 9 A 1 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT Data 1 Data 2 Data 3 ICDRS Data 1 Data 2 ICDRR User processing [2] Write data to ICDRT (data 3) [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) Figure 16.9 Slave Transmit Mode Operation Timing (1) Rev. 3.00 Jun. 18, 2008 Page 816 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE 9 A Slave receive mode 1 2 3 4 5 6 7 8 9 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 16.10 Slave Transmit Mode Operation Timing (2) Rev. 3.00 Jun. 18, 2008 Page 817 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR. SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 1 Bit 7 A A RDRF ICDRS Data 1 Data 2 ICDRR Data 1 User processing [2] Read ICDRR (dummy read) [2] Read ICDRR Figure 16.11 Slave Receive Mode Operation Timing (1) Rev. 3.00 Jun. 18, 2008 Page 818 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 A A RDRF ICDRS Data 1 Data 2 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 16.12 Slave Receive Mode Operation Timing (2) Rev. 3.00 Jun. 18, 2008 Page 819 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format Figure 16.13 shows the clocked synchronous serial transfer format. The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2. SCL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SDA Figure 16.13 Clocked Synchronous Serial Transfer Format (2) Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 16.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS[3:0] bits in ICCR1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1. Rev. 3.00 Jun. 18, 2008 Page 820 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 SCL SDA (Output) 1 2 7 Bit 6 8 Bit 7 1 Bit 0 7 Bit 6 8 Bit 7 1 Bit 0 Bit 0 Bit 1 TRS TDRE ICDRT ICDRS Data 1 Data 1 Data 2 Data 2 Data 3 User processing [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS [3] Write data to ICDRT [3] Write data to ICDRT Figure 16.14 Transmit Mode Operation Timing (3) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 16.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data. Rev. 3.00 Jun. 18, 2008 Page 821 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Notes: Follow the steps below to receive only one byte with MST = 1 specified. See figure 16.16 for the operation timing. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 2. Set MST = 1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be output. 3. Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1. This causes the SCL to be fixed to the high level after outputting one byte of the receive clock. SCL SDA (Input) MST TRS 1 2 7 Bit 6 8 Bit 7 1 Bit 0 7 Bit 6 8 Bit 7 1 Bit 0 2 Bit 1 Bit 0 Bit 1 RDRF ICDRS ICDRR Data 1 Data 2 Data 1 [2] Set MST (when outputting the clock) Data 3 Data 2 User processing [3] Read ICDRR [3] Read ICDRR Figure 16.15 Receive Mode Operation Timing Rev. 3.00 Jun. 18, 2008 Page 822 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 SCL SDA (Input) 1 2 3 4 5 6 7 8 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MST RCVD BC2 to BC0 000 111 110 101 100 011 010 001 000 [2] Set MST [3] Set the RCVD bit after checking if BC2 = 1 Figure 16.16 Operation Timing for Receiving One Byte (MST = 1) Rev. 3.00 Jun. 18, 2008 Page 823 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4.7 Noise Filter The logic levels at the SCL and SDA pins are routed through noise filters before being latched internally. Figure 16.17 shows a block diagram of the noise filter circuit. The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do not agree, the previous value is held. Sampling clock SCL or SDA input signal C D Latch Q D C Q Latch D C Q Latch Match detector 1 Internal SCL or SDA signal 0 Match detector NF2CYC Peripheral clock cycle Sampling clock Figure 16.17 Block Diagram of Noise Filter Rev. 3.00 Jun. 18, 2008 Page 824 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.4.8 Example of Use Flowcharts in respective modes that use the I2C bus interface 3 are shown in figures 16.18 to 16.21. Start Initialize Read BBSY in ICCR2 [1] [2] Test the status of the SCL and SDA lines. Set master transmit mode. Issue the start condition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the final byte) of transmit data. Wait for ICDRT empty. Set the last byte of transmit data. No [1] BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1 Write 1 to BBSY and 0 to SCP Write transmit data in ICDRT Read TEND in ICSR [3] [4] [2] [5] [3] [6] [4] [7] [8] [9] No [5] TEND=1 ? Yes Read ACKBR in ICIER ACKBR=0 ? Yes Transmit mode? Yes No No [6] [10] Wait for last byte to be transmitted. [11] Clear the TEND flag. Master receive mode [12] Clear the STOP flag. [13] Issue the stop condition. Write transmit data in ICDRT Read TDRE in ICSR No [7] [8] TDRE=1 ? Yes [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. No Last byte? Yes Write transmit data in ICDRT [9] Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR [11] [12] Write 0 to BBSY and SCP Read STOP in ICSR No STOP=1 ? Yes Set MST and TRS in ICCR1 to 0 [13] [14] [15] Clear TDRE in ICSR End Figure 16.18 Sample Flowchart for Master Transmit Mode Rev. 3.00 Jun. 18, 2008 Page 825 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Master receive mode [1] Clear TEND, select master receive mode, and then clear TDRE. * Set acknowledge to the transmit device. * Dummy-read ICDDR. * Wait for 1 byte to be received Check whether it is the (last receive - 1). Read the receive data. Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). Read the (final byte - 1) of received data. Wait for the last byte to be receive. Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No [2] [3] [1] [2] [3] [4] [5] [6] [4] [7] [8] RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes [5] [9] [10] Clear the STOP flag. [6] [11] Issue the stop condition. [12] Wait for the creation of stop condition. Set ACKBT in ICIER to 1 [7] [13] Read the last byte of receive data. [14] Clear RCVD. [8] [15] Set slave receive mode. Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR Notes: * Make sure that no interrupt will be generated during steps [1] to [3]. [9] When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR. No RDRF=1 ? Yes Clear STOP in ICSR [10] [11] Write 0 to BBSY and SCP Read STOP in ICSR No [12] STOP=1 ? Yes Read ICDRR Clear RCVD in ICCR1 to 0 [13] [14] [15] Clear MST in ICCR1 to 0 End Figure 16.19 Sample Flowchart for Master Receive Mode Rev. 3.00 Jun. 18, 2008 Page 826 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] [1] [1] Clear the AAS flag. [2] Set transmit data for ICDRT (except for the last byte). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag. [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL. [4] TDRE=1 ? Yes No Last byte? Yes [9] Clear the TDRE flag. Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy-read ICDRR Clear TDRE in ICSR End [6] [7] [8] [9] Figure 16.20 Sample Flowchart for Slave Transmit Mode Rev. 3.00 Jun. 18, 2008 Page 827 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR [1] [2] Set acknowledge to the transmit device. [2] [3] Dummy-read ICDRR. [3] [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the last byte. Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? Yes [5] [8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received. No Read ICDRR [6] [10] Read for the last byte of receive data. Note: When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR. Set ACKBT in ICIER to 1 [7] Read ICDRR Read RDRF in ICSR No [8] [9] RDRF=1 ? Yes Read ICDRR End [10] Figure 16.21 Sample Flowchart for Slave Receive Mode Rev. 3.00 Jun. 18, 2008 Page 828 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.5 Interrupt Requests There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost/overrun error. Table 16.4 shows the contents of each interrupt request. Table 16.4 Interrupt Requests Interrupt Request Transmit data Empty Transmit end Receive data full STOP recognition NACK detection Arbitration lost/ overrun error Abbreviation TXI TEI RXI STPI NAKI Interrupt Condition (TDRE = 1) * (TIE = 1) (TEND = 1) * (TEIE = 1) (RDRF = 1) * (RIE = 1) (STOP = 1) * (STIE = 1) {(NACKF = 1) + (AL = 1)} * (NAKIE = 1) I C Bus Format 2 Clocked Synchronous Serial Format When the interrupt condition described in table 16.4 is 1, the CPU executes an interrupt exception handling. Note that a TXI or RXI interrupt can activate the DMAC if the setting for DMAC activation has been made. In such a case, an interrupt request is not sent to the CPU. Interrupt sources should be cleared in the exception handling. The TDRE and TEND bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an excessive data of one byte may be transmitted. Rev. 3.00 Jun. 18, 2008 Page 829 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 16.22 shows the timing of the bit synchronous circuit and table 16.5 shows the time when the SCL output changes from low to Hi-Z then SCL is monitored. Rev. 3.00 Jun. 18, 2008 Page 830 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 (a) SCL is normally driven 1 Synchronous clock * SCL pin VIH Internal delay *2 Internal SCL monitor The monitor value is high level. Time for monitoring SCL (b) When SCL is driven to low by the slave device Synchronous clock *1 SCL is driven to low by the slave device. SCL pin 2 Internal * delay VIH SCL is not driven to low. VIH Internal delay *2 Internal SCL monitor The monitor value The monitor value is high level. is low level. Time for Time for monitoring SCL monitoring SCL The monitor value is high level. Time for monitoring SCL (c) When the rising speed of SCL is lowered 1 Synchronous clock * SCL pin VIH SCL is not driven to low. 2 Internal * delay The frequency is not the setting frequency. Internal SCL monitor The monitor value is low level. SCL Notes: 1. The clock is the transfer rate clock set by the CKS[3:0] bits in the I2C bus control register 1 (ICCR1). 2. When the NF2CYC bit in NF2CYC (NF2CYC) is set to 0, the internal delay time is 3 to 4 tpcyc. When this bit is set to 1, the internal delay time is 4 to 5 tpcyc. Figure 16.22 Bit Synchronous Circuit Timing Rev. 3.00 Jun. 18, 2008 Page 831 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 Table 16.5 Time for Monitoring SCL CKS3 0 CKS2 0 1 1 Note: * 0 1 Time for Monitoring SCL* 9 tpcyc* 21 tpcyc* 33 tpcyc* 81 tpcyc* tpcyc indicates the freguency of the peripheral clock (P). Rev. 3.00 Jun. 18, 2008 Page 832 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.7 16.7.1 Usage Notes Note on Issue of Stop/Start Conditions Issue the stop condition or start (re-transmit) condition after recognizing the falling edge of the ninth clock. The falling edge of the ninth clock can be recognized by checking the SCLO bit in the I2C control register 2 (ICCR2). Note that if the stop condition or start (re-transmit) condition is issued in a particular timing and the situations shown below, these conditions may not correctly output. No problem will occur otherwise. 1. The rising edge of the SCL becomes less sharp and longer due to the SCL bus load (load capacitor and pull-up resistor) than the period defined in section 16.6, Bit Synchronous Circuit. 2. When the slave device elongates the low level period between the eighth and ninth clocks and activates the bit synchronous circuit. 16.7.2 Settings for Multi-Master Operation In multi-master operation, when the setting for IIC transfer rate (ICCR1.CKS[3:0]) makes this LSI slower than the other masters, pulse cycles with an unexpected length will infrequently be output on SCL. Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other masters. 16.7.3 Note on Master Receive Mode Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data. In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer is full, a stop condition may not be issued. Use either 1 or 2 below as a measure against the situations above. 1. In master receive mode, read ICDRR before the rising edge of the 8th clock. 2. In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units. Rev. 3.00 Jun. 18, 2008 Page 833 of 1160 REJ09B0191-0300 Section 16 I C Bus Interface 3 (IIC3) 2 16.7.4 Note on Setting ACKBT in Master Receive Mode In master receive mode operation, set ACKBT before the falling edge of the 8th SCL cycle of the last data being continuously transferred. Not doing so can lead to an overrun for the slave transmission device. 16.7.5 Note on the States of Bits MST and TRN when Arbitration is Lost When sequential bit-manipulation instructions are used to set the MST and TRS bits to select master transmission in multi-master operation, a conflicting situation where AL in ICSR = 1 but the mode is master transmit mode (MST = 1 and TRS = 1) may arise; this depends on the timing of the loss of arbitration when the bit manipulation instruction for TRS is executed. This can be avoided in either of the following ways. * In multi-master operation, use the MOV instruction to set the MST and TRS bits. * When arbitration is lost, check whether the MST and TRS bits are 0. If the MST and TRS bits have been set to a value other than 0, clear the bits to 0 Rev. 3.00 Jun. 18, 2008 Page 834 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Section 17 A/D Converter (ADC) This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. 17.1 * * * * * Features * * * * * * Resolution: 10 bits Input channels: 8 Minimum conversion time: 3.9 s per channel (P = 33 MHz operation) Absolute accuracy: 4 LSB Operating modes: 3 Single mode: A/D conversion on one channel Multi mode: A/D conversion on one to four channels or on one to eight channels Scan mode: Continuous A/D conversion on one to four channels or on one to eight channels Data registers: 16 Conversion results are held in a 16-bit data register for each channel Sample-and-hold function Conversion can be carried out simultaneously on two channels. A/D conversion start methods: 3 Software Conversion start trigger from multi-function timer pulse unit 2 (MTU2) or multi-function timer pulse unit 2S (MTU2S) External trigger signal Interrupt source An A/D conversion end interrupt (ADI) request can be generated on completion of A/D conversion. Module standby mode can be set Rev. 3.00 Jun. 18, 2008 Page 835 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Figure 17.1 shows a block diagram of the A/D converter. Module data bus Bus interface ADC0 Peripheral bus ADDRG_0 ADDRC_0 ADDRD_0 AVref AVSS 10-bit D/A ADDRH_0 ADDRA_0 ADDRB_0 ADDRE_0 ADDRF_0 ADCSR_0 AVCC Successiveapproximation register ADTRG, conversion start trigger from MTU2 or MTU2S + - Comparator Sample-and-hold circuit ADI0 interrupt signal Control circuit ADCR Module data bus Bus interface ADC1 Peripheral bus ADDRG_1 ADDRC_1 ADDRD_1 AVref AVSS 10-bit D/A Multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 + - Comparator Sample-and-hold circuit ADI1 interrupt signal Control circuit [Legend] ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D ADDRE: A/D data register E ADDRF: A/D data register F ADDRG: A/D data register G ADDRH: A/D data register H ADCR: A/D0, A/D1 control register Figure 17.1 Block Diagram of A/D Converter Rev. 3.00 Jun. 18, 2008 Page 836 of 1160 REJ09B0191-0300 ADDRH_1 ADDRA_1 ADDRB_1 ADDRE_1 ADDRF_1 ADCSR_1 AVCC Successiveapproximation register Section 17 A/D Converter (ADC) 17.2 Input/Output Pins Table 17.1 summarizes the A/D converter's input pins. Table 17.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Analog reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Symbol AVcc AVss AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input to start A/D conversion Function Analog power supply pin Analog ground pin and A/D conversion reference ground A/D converter reference voltage pin Analog input Rev. 3.00 Jun. 18, 2008 Page 837 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.3 Register Descriptions The A/D converter has the following registers. Table 17.2 Register Configuration Channel 0 Register Name A/D data register A_0 A/D data register B_0 A/D data register C_0 A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 1 A/D data register A_1 A/D data register B_1 A/D data register C_1 A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 0 1 Common A/D control/status register_0 A/D control/status register_1 A/D0, A/D1 control register Abbreviation ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_0 ADCSR_1 ADCR R/W R R R R R R R R R R R R R R R R R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0040 H'0040 H'0000 Address H'FFFE5800 H'FFFE5802 H'FFFE5804 H'FFFE5806 H'FFFE5808 H'FFFE580A H'FFFE580C H'FFFE580E H'FFFE5810 H'FFFE5812 H'FFFE5814 H'FFFE5816 H'FFFE5818 H'FFFE581A H'FFFE581C H'FFFE581E H'FFFE5820 H'FFFE5822 H'FFFE5824 Access Size 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Rev. 3.00 Jun. 18, 2008 Page 838 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) The sixteen A/D data registers, ADDRA_0 to ADDRH_0 (A/D0) and ADDRA_1 to ADDRH_1 (A/D1), are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the ADDR corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15 to 6) of ADDR. Bits 5 to 0 of ADDR are reserved bits that are always read as 0. Access to ADDR in 8-bit units is prohibited. ADDR must always be accessed in 16-bit units. ADDR is initialized to H'0000 by a power-on reset or in software standby mode or module standby mode. Table 17.3 indicates the pairings of analog input channels and ADDR. Bit: 15 14 13 12 11 10 9 8 7 6 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 6 5 to 0 Bit Name Initial Value All 0 All 0 R/W R R Description Bit data (10 bits) Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 839 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Table 17.3 Analog Input Channels and ADDR A/D Data Register to Store Conversion Result Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D0 ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 A/D1 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 17.3.2 A/D Control/Status Register (ADCSR) ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter, and enables or disables starting of A/D conversion by external trigger input. ADCSR is initialized to H'0040 by a power-on reset or in software standby mode or module standby mode. Bit: 15 ADF 14 ADIE 13 ADST 12 - 11 10 9 8 7 6 5 4 MDS[2:0] 3 2 1 CH[2:0] 0 TRGS[3:0] CKS[1:0] 0 0 Initial value: R/W: R/(W)* R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * Only 0 can be written to clear the flag after 1 is read. Rev. 3.00 Jun. 18, 2008 Page 840 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Bit 15 Bit Name ADF Initial Value 0 R/W Description R/(W)* A/D End Flag Status flag indicating the end of A/D conversion. [Clearing conditions] * * Cleared by reading ADF while ADF = 1, then writing 0 to ADF Cleared when DMAC is activated by ADI interrupt and ADDR is read A/D conversion ends in single mode A/D conversion ends for the selected channels in multi mode A/D conversion ends for the selected channels in scan mode [Setting conditions] * * * 14 ADIE 0 R/W A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made. 0: A/D end interrupt request (ADI) is disabled 1: A/D end interrupt request (ADI) is enabled 13 ADST 0 R/W A/D Start Starts or stops A/D conversion. This bit remains set to 1 during A/D conversion. 0: A/D conversion is stopped 1: Single mode: A/D conversion starts. This bit is automatically cleared to 0 when A/D conversion ends on the selected channel. Multi mode: A/D conversion starts. This bit is automatically cleared to 0 when A/D conversion is completed cycling through the selected channels. Scan mode: A/D conversion starts. A/D conversion is continuously performed until this bit is cleared to 0 by software, by a power-on reset, or by a transition to software standby mode or module standby mode. 12 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 841 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Bit 11 to 8 Bit Name TRGS[3:0] Initial Value 0000 R/W R/W Description Timer Trigger Select These bits enable or disable starting of A/D conversion by a trigger signal. 0000: Start of A/D conversion by external trigger input is disabled 0001: A/D conversion is started by conversion trigger TRGAN from MTU2 0010: A/D conversion is started by conversion trigger TRG0N from MTU2 0011: A/D conversion is started by conversion trigger TRG4AN from MTU2 0100: A/D conversion is started by conversion trigger TRG4BN from MTU2 0101: A/D conversion is started by conversion trigger TRGAN from MTU2S 0110: Setting prohibited 0111: A/D conversion is started by conversion trigger TRG4AN from MTU2S 1000: A/D conversion is started by conversion trigger TRG4BN from MTU2S 1001: A/D conversion is started by ADTRG 1010 to 1111: Setting prohibited 7, 6 CKS[1:0] 01 R/W Clock Select These bits select the A/D conversion time. Set the A/D conversion time while A/D conversion is halted (ADST = 0). 00: Conversion time = 138 states (maximum), clock = P/4 01: Conversion time = 274 states (maximum), clock = P/8 10: Conversion time = 546 states (maximum), clock = P/16 11: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 842 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Bit 5 to 3 Bit Name MDS[2:0] Initial Value 000 R/W R/W Description Multi-scan Mode These bits select the operating mode for A/D conversion. 0xx: Single mode 100: Multi mode: A/D conversion on 1 to 4 channels 101: Multi mode: A/D conversion on 1 to 8 channels 110: Scan mode: A/D conversion on 1 to 4 channels 111: Scan mode: A/D conversion on 1 to 8 channels 2 to 0 CH[2:0] 000 R/W Channel Select These bits and the MDS bits in ADCSR select the analog input channels. MDS[2] = 1, MDS[2] = 1, MDS[0] = 1 MDS[2] = 0 MDS[0] = 0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 000: AN0 001: AN0, AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4, AN5 110: AN4 to AN6 111: AN4 to AN7 000: AN0 001: AN0, AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN0 to AN4 101: AN0 to AN5 110: AN0 to AN6 111: AN0 to AN7 Note: These bits must be set so that ADCSR_0 and ADCSR_1 do not have the same analog inputs. [Legend] x: Don't care Note: * Only 0 can be written to clear the flag after 1 is read. Rev. 3.00 Jun. 18, 2008 Page 843 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.3.3 A/D0, A/D1 Control Register (ADCR) ADCR is a 16-bit readable/writable register that selects the simultaneous sampling of two channels. ADCR is initialized to H'0000 by a power-on reset or in software standby mode or module standby mode. Bit: 15 DSMP 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 Bit Name DSMP Initial Value 0 R/W R/W Description Simultaneous Sampling Operation Select Selects A/D0 and A/D1 simultaneous sampling. Starts simultaneous sampling of two channels when this bit is set to 1. This bit remains set to 1 during A/D conversion. This bit is automatically cleared to 0 when A/D conversion ends on all selected channels for each operating mode. Note: Set ADCSR before setting this bit. Reserved These bits are always read as 0. The write value should always be 0. 14 to 0 All 0 R Rev. 3.00 Jun. 18, 2008 Page 844 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.4 Operation The A/D converter uses the successive-approximation method, and the resolution is 10 bits. It has three operating modes: single mode, multi mode, and scan mode. Switching the operating mode or analog input channels must be done while the ADST bit in ADCSR is 0 to prevent incorrect operation. The ADST bit can be set at the same time as the operating mode or analog input channels are changed. 17.4.1 Single Mode Single mode should be selected when only A/D conversion on one channel is required. In single mode, A/D conversion is performed once for the specified one analog input channel, as follows: 1. A/D conversion for the selected channel starts when the ADST bit in ADCSR is set to 1 by software, MTU2, MTU2S, or external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the A/D data register corresponding to the channel. 3. After A/D conversion has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D conversion is completed, and the A/D converter becomes idle. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel selection is switched. Typical operations when a single channel (AN1) is selected in single mode are described next. Figure 17.2 shows a timing diagram for this example (the bits which are set in this example belong to ADCSR). 1. Single mode is selected, input channel AN1 is selected (CH[2:0] = 001), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB_0. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI0 interrupt is requested. 4. The A/D interrupt handling routine starts. Rev. 3.00 Jun. 18, 2008 Page 845 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 5. The routine reads ADF = 1, and then writes 0 to the ADF flag. 6. The routine reads and processes the A/D conversion result (ADDRB_0). 7. Execution of the A/D interrupts handling routine ends. Then, when the ADST bit is set to 1, A/D conversion starts and steps 2. to 7. are executed. Rev. 3.00 Jun. 18, 2008 Page 846 of 1160 REJ09B0191-0300 Set* ADIE Set* A/D conversion starts Clear* Clear* Set* ADST ADF Waiting Channel 0 (AN0) operating Waiting Waiting Conversion time 1 Conversion time 2 Channel 1 (AN1) operating Waiting Waiting Channel 2 (AN2) operating Waiting Channel 3 (AN3) operating ADDRA_0 Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRB_0 ADDRC_0 ADDRD_0 Figure 17.2 Example of A/D Converter Operation (Single Mode, One Channel Selected) Section 17 A/D Converter (ADC) Rev. 3.00 Jun. 18, 2008 Page 847 of 1160 REJ09B0191-0300 Note: * Vertical arrows ( ) indicate instruction execution by software. Section 17 A/D Converter (ADC) 17.4.2 Multi Mode Multi mode should be selected when performing A/D conversion once on one or more channels. In multi mode, A/D conversion is performed once for a maximum of eight specified analog input channels, as follows: 1. A/D conversion starts from the analog input channel with the lowest number (e.g. AN0, AN1, ..., AN3) when the ADST bit in ADCSR is set to 1 by software, MTU2, MTU2S, or external trigger input. 2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially transferred to the A/D data register corresponding to that channel. 3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D conversion is completed, and the A/D converter becomes idle. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion is halted and the A/D converter becomes idle. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. A/D conversion is to be performed once on all the specified channels. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in multi mode are described next. Figure 17.3 shows a timing diagram for this example. 1. Multi mode is selected (MDS[2] = 1, MDS[1] = 0), analog input channels AN0 to AN2 are selected (CH[2:0] = 010), and A/D conversion is started (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D conversion result is transferred into ADDRA_0. 3. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and the ADST bit cleared to 0. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Rev. 3.00 Jun. 18, 2008 Page 848 of 1160 REJ09B0191-0300 A/D conversion Clear* Set* ADST Clear* ADF Channel 0 (AN0) operating Waiting Conversion time 1 Waiting Channel 1 (AN1) operating Waiting Conversion time 2 Waiting Channel 2 (AN2) operating Waiting Conversion time 3 Waiting Channel 3 (AN3) operating Waiting ADDRA_0 A/D conversion result 1 ADDRB_0 A/D conversion result 2 Figure 17.3 Example of A/D Converter Operation (Multi Mode, Three Channels (AN0 to AN2) Selected) A/D conversion result 3 ADDRC_0 ADDRD_0 Section 17 A/D Converter (ADC) Rev. 3.00 Jun. 18, 2008 Page 849 of 1160 REJ09B0191-0300 Note: * Vertical arrows ( ) indicate instruction execution by software. Section 17 A/D Converter (ADC) 17.4.3 Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels at all times. In scan mode, A/D conversion is performed sequentially for a maximum of eight specified analog input channels, as follows: 1. A/D conversion for the selected channels starts from the analog input channel with the lowest number (e.g. AN0, AN1, ..., AN3) when the ADST bit in ADCSR is set to 1 by software, MTU2, MTU2S, or external trigger input. 2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially transferred to the A/D data register corresponding to that channel. 3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The A/D converter starts A/D conversion again from the channel with the lowest number. 4. The ADST bit is not cleared automatically, so steps 2. and 3. are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion halts and the A/D converter becomes idle. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described as follows. Figure 17.4 shows a timing diagram for this example. 1. Scan mode is selected (MDS[2] = 1, MDS[1] = 1), analog input channels AN0 to AN2 are selected (CH[2:0] = 010), and A/D conversion is started (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D conversion result is transferred into ADDRA_0. 3. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI0 interrupt is requested. Rev. 3.00 Jun. 18, 2008 Page 850 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 6. The ADST bit is not cleared automatically, so steps 2. to 4. are repeated as long as the ADST bit remains set to 1. When steps 2. to 4. are repeated, the ADF flag is kept to 1. When the ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. If both the ADF flag and ADIE bit are set to 1 while steps 2. to 4. are repeated, an ADI0 interrupt is requested at all times. To generate an interrupt on completing conversion of the third channel, clear the ADF bit to 0 after an interrupt is requested. Rev. 3.00 Jun. 18, 2008 Page 851 of 1160 REJ09B0191-0300 Continuous A/D conversion Set*1 Clear*1 REJ09B0191-0300 Clear*1 Waiting Conversion time 1 ADST Section 17 A/D Converter (ADC) ADF Waiting Conversion time 4 Channel 0 (AN0) operating Waiting *2 Rev. 3.00 Jun. 18, 2008 Page 852 of 1160 Waiting Conversion time 2 Channel 1 (AN1) operating Waiting Conversion time 5 Waiting Channel 2 (AN2) operating Waiting Conversion time 3 Waiting Channel 3 (AN3) operating Waiting ADDRA_0 A/D conversion result 1 A/D conversion result 4 ADDRB_0 A/D conversion result 2 Figure 17.4 Example of A/D Converter Operation (Scan Mode, Three Channels (AN0 to AN2) Selected) A/D conversion result 3 ADDRC_0 ADDRD_0 Notes: 1. Vertical arrows ( ) indicate instruction execution by software. 2. A/D conversion data is invalid. Section 17 A/D Converter (ADC) 17.4.4 Simultaneous Sampling Operation With simultaneous sampling, A/D conversion is performed with the input voltages on two channels (A/D0 and A/D1) sampled at the same time. Simultaneous sampling is valid in single mode, multi mode, and scan mode. The channels for simultaneous sampling are determined by the CH[2:0] bits in the A/D control/status register (ADCSR_0 or ADCSR_1). The procedure for setting simultaneous sampling is to select the operating mode, input channels, and operating clock. Writing 1 to the DSMP bit in the A/D0, A/D1 control register (ADCR) starts simultaneous sampling for A/D0 and A/D1. Even though the DSMP bit is changed during A/D conversion, A/D conversion is not halted. To halt A/D conversion, change the ADST bit. The timing for simultaneous sampling is the same as the timing for each operating mode. 17.4.5 A/D Converter Activation by External Trigger, MTU2, or MTU2S The A/D converter can be independently activated by an A/D conversion request from the external trigger, MTU2, or MTU2S. To activate the A/D converter by the external trigger, MTU2, or MTU2S, set the A/D trigger enable bits (TRGS[3:0]). After this bit setting has been made, the ADST bit is automatically set to 1 and A/D conversion is started when an A/D conversion request from the external trigger, MTU2, or MTU2S occurs. If the TRGS[3:0] bits in both ADCSR_0 and ADCSR_1 select the same conversion trigger, A/D conversion starts simultaneously on A/D0 and A/D1. The channel combination is determined by the CH[2:0] bits in ADCSR_0 and ADCSR_1. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 17.4.6 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at the A/D conversion start delay time (tD) after the ADST bit in ADCSR is set to 1, then starts conversion. Figure 17.5 shows the A/D conversion timing. Table 17.4 indicates the A/D conversion time. As indicated in figure 17.5, the A/D conversion time (tCONV) includes tD and the input sampling time(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 17.4. In multi mode and scan mode, the values given in table 17.4 apply to the first conversion. In the second and subsequent conversions, time is the values given in table 17.5. Rev. 3.00 Jun. 18, 2008 Page 853 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) (1) P Address (2) Write signal Input sampling timing ADIF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time Figure 17.5 A/D Conversion Timing Table 17.4 A/D Conversion Time (Single Mode) CKS[1] = 0 CKS[0] = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. 11 -- 135 Typ. -- 33 -- Max. 14 -- 138 Min. 19 -- 267 CKS[0] = 1 Typ. -- 65 -- Max. 26 -- 274 Min. 35 -- 531 CKS[1] = 1 CKS[0] = 0 Typ. -- 129 -- Max. 50 -- 546 Note: Values in the table are the numbers of states. Rev. 3.00 Jun. 18, 2008 Page 854 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Table 17.5 A/D Conversion Time (Multi Mode and Scan Mode) CKS[1] 0 CKS[0] 0 1 1 0 Conversion Time (States) 128 (constant) 256 (constant) 512 (constant) Note: Values in the table are the numbers of states. 17.4.7 External Trigger Input Timing A/D conversion can also be externally triggered. When the TRGS[3:0] bits in ADCSR are set to B'1001, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin, thus starting A/D conversion. If the TRGS[3:0] bits in both ADCSR_0 and ADCSR_1 are set to B'1001 at this time, A/D conversion starts simultaneously on A/D0 and A/D1. Other operations, regardless of the operating mode, are the same as when the ADST bit has been set to 1 by software. Figure 17.6 shows the timing. However, when using the ADTRG pin, keep the initial input to the pin high and do not drive it low until the conversion starts. P ADTRG Internal trigger signal ADST A/D conversion Figure 17.6 External Trigger Input Timing Rev. 3.00 Jun. 18, 2008 Page 855 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.5 Interrupt Sources and DMAC Transfer Request The A/D converter generates an A/D conversion end interrupt (ADI0 or ADI1) at the end of A/D conversion. An ADI0 or ADI1 interrupt request is generated if the ADIE bit is set to 1 when the ADF bit in ADCSR is set to 1 on completion of A/D conversion. Note that the direct memory access controller (DMAC) can be activated by an ADI interrupt depending on the DMAC setting. In this case, an interrupt is not issued to the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the CPU. Having the converted data read by the DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. In single mode, set the DMAC so that DMA transfer initiated by an ADI interrupt is performed only once. In the case of A/D conversion on multiple channels in scan mode or multi mode, setting the DMA transfer count to one causes DMA transfer to finish after transferring only one channel of data. To make the DMAC transfer all conversion data, set the ADDR where A/D conversion data is stored as the transfer source address, and the number of converted channels as the transfer count (set the TC bit of the DMA channel control register (CHCR) in the DMAC to 1 and set the number of converted channels in the DMA transfer count register (DMATCR)). When the DMAC is activated by ADI0 or ADI1, the ADF bit in ADCSR is automatically cleared to 0 when data is transferred by the DMAC. Table 17.6 Relationship between Interrupt Sources and DMAC Transfer Request Name ADI0 ADI1 Interrupt Source A/D conversion end A/D conversion end Interrupt Flag ADF in ADCSR_0 ADF in ADCSR_1 DMAC Activation Possible Possible Rev. 3.00 Jun. 18, 2008 Page 856 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: * * * * Offset error Full-scale error Quantization error Nonlinearity error These four error quantities are explained below with reference to figure 17.7. In the figure, the 10 bits of the A/D converter have been simplified to 3 bits. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) B'0000000000 (000 in the figure) to B'000000001 (001 in the figure)(figure 17.7, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from B'1111111110 (110 in the figure) to the maximum B'1111111111 (111 in the figure)(figure 17.7, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 17.7, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 17.7, item (4)). Note that it does not include offset, full-scale, or quantization error. Digital output Digital output (2) Full-scale error 111 110 101 100 011 010 001 000 0 1 2 10241024 Ideal A/D conversion characteristic Ideal A/D conversion characteristic (4) Nonlinearity error (3) Quantization error Actual A/D convertion characteristic (1) Offset error FS Analog input voltage 10221023 FS 10241024 Analog input voltage [Legend] FS: Full-scale voltage Figure 17.7 Definitions of A/D Conversion Accuracy Rev. 3.00 Jun. 18, 2008 Page 857 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.7 Usage Notes When using the A/D converter, note the following points. 17.7.1 Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, see section 22, Power-Down Modes. 17.7.2 Setting Analog Input Voltage Permanent damage to the LSI may result if the following voltage ranges are exceeded. 1. Analog input range During A/D conversion, voltages on the analog input pins ANn should not go beyond the following range: AVss ANn AVcc (n = 0 to 7). 2. AVcc and AVss input voltages Input voltages AVcc and AVss should be PVcc - 0.3 V AVcc PVcc and AVss = PVss. Do not leave the AVcc and AVss pins open when the A/D converter or D/A converter is not in use and in software standby mode. When not in use, connect AVcc to the power supply (PVcc) and AVss to the ground (PVss). 3. Setting range of AVref input voltage Set the reference voltage range of the AVref pin as 3.0 V AVref AVcc. 17.7.3 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference voltage (AVref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (PVss) on the board. Rev. 3.00 Jun. 18, 2008 Page 858 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 17.7.4 Processing of Analog Input Pins To prevent damage from voltage surges at the analog input pins (AN0 to AN7), connect an input protection circuit like the one shown in figure 17.8. The circuit shown also includes a CR filter to suppress noise. This circuit is shown as an example; the circuit constants should be selected according to actual application conditions. Figure 17.9 shows an equivalent circuit diagram of the analog input ports and table 17.7 lists the analog input pin specifications. AVcc AVref *2 *1 *1 0.1 F Rin 100 This LSI AN0 to AN7 AVss Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 17.8 Example of Analog Input Protection Circuit Rev. 3.00 Jun. 18, 2008 Page 859 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) 3 k AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 17.9 Analog Input Pin Equivalent Circuit Table 17.7 Analog Input Pin Ratings Item Analog input capacitance Allowable signal-source impedance Min. Max. 20 5 Unit pF k 17.7.5 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with a large capacitance provided externally for A/D conversion in single mode, the input load will essentially comprise only the internal input resistance of 3 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 17.10). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Rev. 3.00 Jun. 18, 2008 Page 860 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) This LSI Sensor output impedance Up to 5 k Sensor input Low-pass filter Cin = 15 pF A/D converter equivalent circuit 3 k 20 pF C to 0.1 F Note: Values are reference values. Figure 17.10 Example of Analog Input Circuit 17.7.6 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). 17.7.7 Note on Usage in Scan Mode and Multi Mode Switching to single mode and then starting conversion immediately after having stopped scan mode or multi mode operation may lead to erroneous results of conversion in single mode. To perform conversion in single mode in such cases, set ADST to 0, wait for at least the A/D conversion time for a single channel to elapse, and then start conversion (ADST = 1). (The A/D conversion time for a single channel will vary according to the settings of the ADC registers). Rev. 3.00 Jun. 18, 2008 Page 861 of 1160 REJ09B0191-0300 Section 17 A/D Converter (ADC) Rev. 3.00 Jun. 18, 2008 Page 862 of 1160 REJ09B0191-0300 Section 18 D/A Converter (DAC) Section 18 D/A Converter (DAC) 18.1 * * * * * * Features 8-bit resolution Two output channels Minimum conversion time of 10 s (with 20 pF load) Output voltage of 0 V to AVref D/A output hold function in software standby mode Module standby mode can be set Peripheral bus DA0 DA1 AVss D/A Control circuit [Legend] DADR0: D/A data register 0 DADR1: D/A data register 1 DACR: D/A control register Figure 18.1 Block Diagram of D/A Converter DACR 8-bit DADR0 DADR1 AVcc AVref Rev. 3.00 Jun. 18, 2008 Page 863 of 1160 REJ09B0191-0300 Bus interface Module data bus Section 18 D/A Converter (DAC) 18.2 Input/Output Pins Table 18.1 shows the pin configuration of the D/A converter. Table 18.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Symbol AVcc AVss I/O Input Input Input Output Output Function Analog block power supply Analog block ground D/A conversion reference voltage Channel 0 analog output Channel 1 analog output Analog reference voltage pin AVref Analog output pin 0 Analog output pin 1 DA0 DA1 Rev. 3.00 Jun. 18, 2008 Page 864 of 1160 REJ09B0191-0300 Section 18 D/A Converter (DAC) 18.3 Register Descriptions The D/A converter has the following registers. Table 18.2 Register Configuration Register Name D/A data register 0 D/A data register 1 D/A control register Abbreviation DADR0 DADR1 DACR R/W R/W R/W R/W Initial Value H'00 H'00 H'1F Address H'FFFE6800 H'FFFE6801 H'FFFE6802 Access Size 8, 16 8, 16 8, 16 18.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1) DADR is an 8-bit readable/writable register that stores data to which D/A conversion is to be performed. Whenever analog output is enabled, the values in DADR are converted and output to the analog output pins. DADR is initialized to H'00 by a power-on reset or in module standby mode. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 865 of 1160 REJ09B0191-0300 Section 18 D/A Converter (DAC) 18.3.2 D/A Control Register (DACR) DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a power-on reset or in module standby mode. Bit: 7 6 5 DAE 4 - 3 - 2 - 1 - 0 - DAOE1 DAOE0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 1 - 1 - 1 - 1 - 1 - Bit 7 Bit Name DAOE1 Initial Value 0 R/W R/W Description D/A Output Enable 1 Controls D/A conversion and analog output for channel 1. 0: Analog output of channel 1 (DA1) is disabled 1: D/A conversion of channel 1 is enabled. Analog output of channel 1 (DA1) is enabled. 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output for channel 0. 0: Analog output of channel 0 (DA0) is disabled 1: D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. 5 DAE 0 R/W D/A Enable Used together with the DAOE0 and DAOE1 bits to control D/A conversion. Output of conversion results is always controlled by the DAOE0 and DAOE1 bits. For details, see table 18.3. 0: D/A conversion for channels 0 and 1 is controlled independently 1: D/A conversion for channels 0 and 1 is controlled together 4 to 0 All 1 Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 866 of 1160 REJ09B0191-0300 Section 18 D/A Converter (DAC) Table 18.3 Control of D/A Conversion Bit 5 DAE 0 Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 1 0 1 1 0 0 1 1 0 1 Description D/A conversion is disabled. D/A conversion of channel 0 is enabled and D/A conversion of channel 1 is disabled. D/A conversion of channel 1 is enabled and D/A conversion of channel 0 is disabled. D/A conversion of channels 0 and 1 is enabled. D/A conversion is disabled. D/A conversion of channels 0 and 1 is enabled. Rev. 3.00 Jun. 18, 2008 Page 867 of 1160 REJ09B0191-0300 Section 18 D/A Converter (DAC) 18.4 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and the conversion result is output. An operation example of D/A conversion on channel 0 is shown below. Figure 18.2 shows the timing of this operation. 1. Write the conversion data to DADR0. 2. Set the DAOE0 bit in DACR to 1 to start D/A conversion. The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion result continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The output value is expressed by the following formula: Contents of DADR 256 x AVref 3. If DADR0 is written to again, the conversion is immediately started. The conversion result is output after the conversion time tDCONV has elapsed. 4. If the DAOE0 bit is cleared to 0, analog output is disabled. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion result 2 DA0 High-impedance state [Legend] tDCONV: D/A conversion time tDCONV Conversion result 1 tDCONV Figure 18.2 Example of D/A Converter Operation Rev. 3.00 Jun. 18, 2008 Page 868 of 1160 REJ09B0191-0300 Section 18 D/A Converter (DAC) 18.5 18.5.1 Usage Notes Module Standby Mode Setting Operation of the D/A converter can be disabled or enabled using the standby control register. The initial setting is for operation of the D/A converter to be halted. Register access is enabled by canceling module standby mode. For details, see section 22, Power-Down Modes. 18.5.2 D/A Output Hold Function in Software Standby Mode When this LSI enters software standby mode with D/A conversion enabled, the D/A outputs are retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE0, DAOE1, and DAE bits to 0 to disable the D/A outputs. 18.5.3 Setting Analog Input Voltage The reliability of this LSI may be adversely affected if the following voltage ranges are exceeded. 1. AVcc and AVss input voltages Input voltages AVcc and AVss should be PVcc - 0.3 V AVcc PVcc and AVss = PVss. Do not leave the AVcc and AVss pins open when the A/D converter or D/A converter is not in use and in software standby mode. When not in use, connect AVcc to the power supply (PVcc) and AVss to the ground (PVss). 2. Setting range of AVref input voltage Set the reference voltage range of the AVref pin as 3.0 V AVref AVcc. Rev. 3.00 Jun. 18, 2008 Page 869 of 1160 REJ09B0191-0300 Section 18 D/A Converter (DAC) Rev. 3.00 Jun. 18, 2008 Page 870 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Section 19 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 19.1 to 19.6 list the multiplexed pins of this LSI. Table 19.1 Multiplexed Pins (Port A) Port A Function 1 (Related Module) PA25 I/O (port) Function 2 (Related Module) CE2B output (BSC) CE2A output (BSC) WE3/DQMUU/AH/ ICIOWR output (BSC) Function 3 (Related Module) DACK3 output (DMAC) Function 4 (Related Module) PINT7 input (INTC) Function 5 (Related Module) POE8 input (port) PA24 I/O (port) PA23 I/O (port) DREQ3 input (DMAC) PINT6 input (INTC) TIC5W input (MTU2) PA22 I/O (port) WE2/DQMUL/ICIORD output (BSC) CS5/CE1A output (BSC) CS4 output (BSC) BACK output (BSC) BREQ input (BSC) WAIT input (BSC) WE3/DQMUU/AH/ ICIOWR output (BSC) WE1/DQMLU/WE output (BSC) WE0/DQMLL output (BSC) CS1 output (BSC) TCLKD input (MTU2) TCLKC input (MTU2) TCLKB input (MTU2) CASU output (BSC) RASU output (BSC) TEND1 output (DMAC) TIC5V input (MTU2) PA21 I/O (port) TIC5U input (MTU2) PINT5 input (INTC) PA20 I/O (port) PA19 I/O (port) PINT4 input (INTC) PINT3 input (INTC) PA18 I/O (port) TEND0 output (DMAC) PINT2 input (INTC) PA17 I/O (port) DACK2 output (DMAC) PA16 I/O (port) DREQ2 input (DMAC) IRQ3 input (INTC) IRQ2 input (INTC) CS3 output (BSC) POE7 input (port) POE6 input (port) POE5 input (port) CKE output (BSC) PA13 I/O (port) PA12 I/O (port) PA11 I/O (port) PA9 I/O (port) PA8 I/O (port) PA7 I/O (port) FRAME output (BSC) CKE output (BSC) RD/WR output (BSC) Rev. 3.00 Jun. 18, 2008 Page 871 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Port A Function 1 (Related Module) PA6 I/O (port) PA5 I/O (port) PA4 I/O (port) PA3 I/O (port) PA2 I/O (port) PA1 I/O (port) Function 2 (Related Module) TCLKA input (MTU2) SCK1 I/O (SCIF1) TxD1 output (SCIF1) RxD1 input (SCIF1) SCK0 I/O (SCIF0) TxD0 output (SCIF0) Function 3 (Related Module) CS2 output (BSC) Function 4 (Related Module) Function 5 (Related Module) A22 output (BSC) A23 output (BSC) A24 output (BSC) A25 output (BSC) CS5/CE1A output (BSC) CS4 output (BSC) DREQ1 input (DMAC) IRQ1 input (INTC) DREQ0 input (DMAC) IRQ0 input (INTC) PINT1 input (INTC) PA0 I/O (port) RxD0 input (SCIF0) PINT0 input (INTC) Table 19.2 Multiplexed Pins (Port B) Port B Function 1 (Related Module) PB9 I/O (port) PB5 I/O (port) PB4 I/O (port) PB3 input (port) PB2 input (port) Function 2 (Related Module) IRQ7 input (INTC) IRQ3 input (INTC) IRQ2 input (INTC) IRQ1 input (INTC) IRQ0 input (INTC) Function 3 (Related Module) A21 output (BSC) POE3 input (port) POE2 input (port) POE1 input (port) POE0 input (port) Function 4 (Related Module) ADTRG input (ADC) CASL output (BSC) RASL output (BSC) SDA I/O (IIC3) SCL I/O (IIC3) Function 5 (Related Module) POE8 input (port) Table 19.3 Multiplexed Pins (Port C) Port C Function 1 (Related Module) PC1 I/O (port) PC0 I/O (port) Function 2 (Related Module) A1 output (BSC) A0 output (BSC) Rev. 3.00 Jun. 18, 2008 Page 872 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Table 19.4 Multiplexed Pins (Port D) Port D Function 1 (Related Module) PD31 I/O (port) PD30 I/O (port) Function 2 (Related Module) D31 I/O (BSC) D30 I/O (BSC) Function 3 (Related Module) ADTRG input (ADC) IRQOUT/REFOUT output (INTC/BSC) CS3 output (BSC) CS2 output (BSC) DACK1 output (DMAC) DACK0 output (DMAC) DREQ1 input (DMAC) DREQ0 input (DMAC) IRQ7 input (INTC) IRQ6 input (INTC) IRQ5 input (INTC) IRQ4 input (INTC) IRQ3 input (INTC) IRQ2 input (INTC) IRQ1 input (INTC) IRQ0 input (INTC) Function 4 (Related Module) TIOC3AS I/O (MTU2S) TIOC3CS I/O (MTU2S) PD29 I/O (port) PD28 I/O (port) PD27 I/O (port) PD26 I/O (port) PD25 I/O (port) PD24 I/O (port) PD23 I/O (port) PD22 I/O (port) PD21 I/O (port) PD20 I/O (port) PD19 I/O (port) PD18 I/O (port) PD17 I/O (port) PD16 I/O (port) PD15 I/O (port) PD14 I/O (port) PD13 I/O (port) PD12 I/O (port) PD11 I/O (port) PD10 I/O (port) PD9 I/O (port) PD8 I/O (port) D29 I/O (BSC) D28 I/O (BSC) D27 I/O (BSC) D26 I/O (BSC) D25 I/O (BSC) D24 I/O (BSC) D23 I/O (BSC) D22 I/O (BSC) D21 I/O (BSC) D20 I/O (BSC) D19 I/O (BSC) D18 I/O (BSC) D17 I/O (BSC) D16 I/O (BSC) D15 I/O (BSC) D14 I/O (BSC) D13 I/O (BSC) D12 I/O (BSC) D11 I/O (BSC) D10 I/O (BSC) D9 I/O (BSC) D8 I/O (BSC) TIOC3BS I/O (MTU2S) TIOC3DS I/O (MTU2S) TIOC4AS I/O (MTU2S) TIOC4BS I/O (MTU2S) TIOC4CS I/O (MTU2S) TIOC4DS I/O (MTU2S) TIC5US input (MTU2S) TIC5VS input (MTU2S) TIC5WS input (MTU2S) POE7 input (port) POE6 input (port) POE5 input (port) POE4 input (port) TIOC4DS I/O (MTU2S) TIOC4CS I/O (MTU2S) TIOC4BS I/O (MTU2S) TIOC4AS I/O (MTU2S) TIOC3DS I/O (MTU2S) TIOC3CS I/O (MTU2S) TIOC3BS I/O (MTU2S) TIOC3AS I/O (MTU2S) Rev. 3.00 Jun. 18, 2008 Page 873 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Table 19.5 Multiplexed Pins (Port E) Port E Function 1 (Related Module) PE16 I/O (port) PE15 I/O (port) Function 2 (Related Module) TIOC4D I/O (MTU2) Function 3 (Related Module) DACK1 output (DMAC) Function 4 (Related Module) IRQOUT/REFOUT output (INTC/BSC) CTS3 I/O (SCIF3) RTS3 I/O (SCIF3) BS output (BSC) Function 5 (Related Module) CS8 output (BSC) CKE output (BSC) WE3/DQMUU/AH/ ICIOWR output (BSC) UBCTRG output (UBC) CS7 output (BSC) CS6/CE1B output (BSC) IOIS16 input (BSC) PE14 I/O (port) TIOC4C I/O (MTU2) DACK0 output (DMAC) MRES input (INTC) TxD3 output (SCIF3) RxD3 input (SCIF3) TxD2 output (SCIF2) SCK3 I/O (SCIF3) SCK2 I/O (SCIF2) RxD2 input (SCIF2) PE13 I/O (port) PE12 I/O (port) PE11 I/O (port) PE10 I/O (port) PE9 I/O (port) PE8 I/O (port) PE7 I/O (port) TIOC4B I/O (MTU2) TIOC4A I/O (MTU2) TIOC3D I/O (MTU2) TIOC3C I/O (MTU2) TIOC3B I/O (MTU2) TIOC3A I/O (MTU2) TIOC2B I/O (MTU2) PE6 I/O (port) PE5 I/O (port) TIOC2A I/O (MTU2) TIOC1B I/O (MTU2) SCK3 I/O (SCIF3) TxD3 output (SCIF3) PE4 I/O (port) PE3 I/O (port) TIOC1A I/O (MTU2) TIOC0D I/O (MTU2) RxD3 input (SCIF3) TEND1 output (DMAC) PE2 I/O (port) PE1 I/O (port) TIOC0C I/O (MTU2) TIOC0B I/O (MTU2) DREQ1 input (DMAC) TEND0 output (DMAC) PE0 I/O (port) TIOC0A I/O (MTU2) DREQ0 input (DMAC) Rev. 3.00 Jun. 18, 2008 Page 874 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Table 19.6 Multiplexed Pins (Port F) Port F Function 1 (Related Module) PF7 input (port) PF6 input (port) PF5 input (port) PF4 input (port) PF3 input (port) PF2 input (port) PF1 input (port) PF0 input (port) Function 2 (Related Module) AN7 input (ADC) AN6 input (ADC) AN5 input (ADC) AN4 input (ADC) AN3 input (ADC) AN2 input (ADC) AN1 input (ADC) AN0 input (ADC) Function 3 (Related Module) DA1 output (DAC) DA0 output (DAC) Note: The general input, A/D converter analog input, and D/A converter analog output functions are automatically switched; the PFC has no register for specifying these functions. 19.1 Features * By setting the control registers, multiplexed pin functions can be selectable. * When the general I/O function or TIOC I/O function of MTU2 or MTU2S is specified, the I/O direction can be selected by I/O register settings. * Switching the fort F function by the settings of the A/D control/status register of the A/D converter (ADCSR) or D/A control register of the D/A converter (DACR). Rev. 3.00 Jun. 18, 2008 Page 875 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2 Register Descriptions The PFC has the following registers. Table 19.7 Register Configuration Register Name Port A I/O register H Port A I/O register L Port A control register H3 Port A control register H2 Port A control register H1 Port A control register L4 Port A control register L3 Port A control register L2 Port A control register L1 Port B I/O register Port B control register 3 Port B control register 2 Port B control register 1 Port C I/O register L Port C control register L1 Abbreviation R/W PAIORH PAIORL PACRH3 PACRH2 PACRH1 PACRL4 PACRL3 PACRL2 PACRL1 PBIOR PBCR3 PBCR2 PBCR1 PCIORL PCCRL1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address H'0000 H'0000 H'0000 H'0000 H'0000 H'1100 H'0100 H'0000 H'0000 H'0000 H'0002 H'2200 H'0011 H'0000 H'1100/ H'1110/ H'1111 H'0000 H'0000 H'0000/ H'1111 H'0000/ H'1111 H'0000/ H'1111 H'0000/ H'1111 Access Size H'FFFE3804 8, 16, 32 H'FFFE3806 8, 16 H'FFFE380A 8, 16 H'FFFE380C 8, 16, 32 H'FFFE380E 8, 16 H'FFFE3810 8, 16, 32 H'FFFE3812 8, 16 H'FFFE3814 8, 16, 32 H'FFFE3816 8, 16 H'FFFE3886 8, 16 H'FFFE3892 8, 16 H'FFFE3894 8, 16, 32 H'FFFE3896 8, 16 H'FFFE3906 8, 16 H'FFFE3916 8, 16 Port D I/O register H Port D I/O register L Port D control register H4 Port D control register H3 Port D control register H2 Port D control register H1 PDIORH PDIORL PDCRH4 PDCRH3 PDCRH2 PDCRH1 R/W R/W R/W R/W R/W R/W H'FFFE3984 8, 16, 32 H'FFFE3986 8, 16 H'FFFE3988 8, 16, 32 H'FFFE398A 8, 16 H'FFFE398C 8, 16, 32 H'FFFE398E 8, 16 Rev. 3.00 Jun. 18, 2008 Page 876 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Register Name Port D control register L4 Port D control register L3 Port E I/O register H Port E I/O register L Port E control register H1 Port E control register L4 Port E control register L3 Port E control register L2 Port E control register L1 IRQOUT function control register Abbreviation R/W PDCRL4 PDCRL3 PEIORH PEIORL PECRH1 PECRL4 PECRL3 PECRL2 PECRL1 IFCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address H'0000/ H'1111 H'0000/ H'1111 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Access Size H'FFFE3990 8, 16, 32 H'FFFE3992 8, 16 H'FFFE3A04 8, 16, 32 H'FFFE3A06 8, 16 H'FFFE3A0E 8, 16 H'FFFE3A10 8, 16, 32 H'FFFE3A12 8, 16 H'FFFE3A14 8, 16, 32 H'FFFE3A16 8, 16 H'FFFE3A22 16 Rev. 3.00 Jun. 18, 2008 Page 877 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2.1 Port A I/O Registers H, L (PAIORH, PAIORL) PAIORH and PAIORL are 16-bit readable/writable registers that are used to set the pins on port A as inputs or outputs. Bits PA25IOR to PA16IOR, PA13IOR to PA11IOR, and PA9IOR to PA0IOR correspond to pins PA25/CE2B/DACK3/POE8/PINT7 to PA16/WE3/DQMUU/ICIOWR/AH/DREQ2/CKE, PA13/WE1/DQMLU/WE/POE7 to PA11/CS1/POE5, and PA9/TCLKD/IRQ3/FRAME/CKE to PA0/RxD0/PINT0/CS4. PAIORH and PAIORL are enabled when the port A pins are functioning as general-purpose inputs/outputs (PA25 to PA16, PA13 to PA11, and PA9 to PA0). In other states, they are disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORH or PAIORL is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 10 of PAIORH and bits 15, 14, and 10 of PAIORL are reserved. These bits are always read as 0. The write value should always be 0. PAIORH and PAIORL are initialized to H'0000 by a power-on reset; however, the registers are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port A I/O Register H (PAIORH) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PA25 IOR 8 PA24 IOR 7 PA23 IOR 6 PA22 IOR 5 PA21 IOR 4 PA20 IOR 3 PA19 IOR 2 PA18 IOR 1 PA17 IOR 0 PA16 IOR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W (2) Port A I/O Register L (PAIORL) Bit: 15 - 14 - 13 PA13 IOR 12 PA12 IOR 11 PA11 IOR 10 - 9 PA9 IOR 8 PA8 IOR 7 PA7 IOR 6 PA6 IOR 5 PA5 IOR 4 PA4 IOR 3 PA3 IOR 2 PA2 IOR 1 PA1 IOR 0 PA0 IOR Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 878 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2.2 Port A Control Registers H1 to H3, L1 to L4 (PACRH1 to PACRH3, PACRL1 to PACRL4) PACRH1 to PACRH3 and PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port A. PACRH1 to PACRH3 and PACRL1 to PACRL4 are initialized to the values shown in table 19.7 by a power-on reset; however, the registers are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port A Control Register H3 (PACRH3) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 PA25MD[2:0] 4 3 - 2 1 PA24MD[2:0] 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 to 7 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 6 to 4 PA25MD[2:0] 000 R/W PA25 Mode Select the function of the PA25/CE2B/DACK3/POE8/PINT7 pin. 000: PA25 I/O (port) 001: CE2B output (BSC) 010: DACK3 output (DMAC) 011: POE8 input (POE2) 100: PINT7 input (INTC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 879 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 2 to 0 Bit Name Initial Value R/W R/W Description PA24 Mode Select the function of the PA24/CE2A/DREQ3/PINT6 pin. 000: PA24 I/O (port) 001: CE2A output (BSC) 010: DREQ3 input (DMAC) 011: Setting prohibited 100: PINT6 input (INTC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PA24MD[2:0] 000 (2) Port A Control Register H2 (PACRH2) Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 5 PA21MD[2:0] 4 3 - 2 1 PA20MD[2:0] 0 PA23MD[1:0] PA22MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PA23MD[1:0] 00 R/W PA23 Mode Select the function of the PA23/WE3/DQMUU/ICIOWR/AH/TIC5W pin. 00: PA23 I/O (port) 01: WE3/DQMUU/ICIOWR/AH output (BSC) 10: Setting prohibited 11: TIC5W input (MTU2) 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 880 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 9, 8 Bit Name Initial Value R/W R/W Description PA22 Mode Select the function of the PA22/WE2/DQMUL/ICIORD/TIC5V pin. 00: PA22 I/O (port) 01: WE2/DQMUL/ICIORD output (BSC) 10: Setting prohibited 11: TIC5V input (MTU2) PA22MD[1:0] 00 7 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PA21MD[2:0] 000 R/W PA21 Mode Select the function of the PA21/CS5/CE1A/CASU/TIC5U/PINT5 pin. 000: PA21 I/O (port) 001: CS5/CE1A output (BSC) 010: CASU output (BSC) 011: TIC5U input (MTU2) 100: PINT5 input (INTC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 881 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 2 to 0 Bit Name Initial Value R/W R/W Description PA20 Mode Select the function of the PA20/CS4/RASU/PINT4 pin. 000: PA20 I/O (port) 001: CS4 output (BSC) 010: RASU output (BSC) 011: Setting prohibited 100: PINT4 input (INTC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PA20MD[2:0] 000 (3) Port A Control Register H1 (PACRH1) Bit: 15 - 14 13 PA19MD[2:0] 12 11 - 10 9 PA18MD[2:0] 8 7 - 6 - 5 4 3 - 2 1 PA16MD[2:0] 0 PA17MD[1:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PA19MD[2:0] 000 R/W PA19 Mode Select the function of the PA19/BACK/TEND1/PINT3 pin. 000: PA19 I/O (port) 001: BACK output (BSC) 010: TEND1 output (DMAC) 011: Setting prohibited 100: PINT3 input (INTC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 882 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 11 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PA18MD[2:0] 000 R/W PA18 Mode Select the function of the PA18/BREQ/TEND0/PINT2 pin. 000: PA18 I/O (port) 001: BREQ input (BSC) 010: TEND0 output (DMAC) 011: Setting prohibited 100: PINT2 input (INTC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PA17MD[1:0] 00 R/W PA17 Mode Select the function of the PA17/WAIT/DACK2 pin. 00: PA17 I/O (port) 01: WAIT input (BSC) 10: DACK2 output (DMAC) 11: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 883 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 2 to 0 Bit Name Initial Value R/W R/W Description PA16 Mode Select the function of the PA16/WE3/DQMUU/ICIOWR/AH/DREQ2/CKE pin. 000: PA16 I/O (port) 001: WE3/DQMUU/ICIOWR/AH output (BSC) 010: DREQ2 input (DMAC) 011: Setting prohibited 100: Setting prohibited 101: CKE output (BSC) 110: Setting prohibited 111: Setting prohibited PA16MD[2:0] 000 (4) Port A Control Register L4 (PACRL4) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 4 3 - 2 - 1 0 PA13MD[1:0] PA12MD[1:0] Initial value: R/W: 0 R 0 R 0 R 1 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 13 12 1 R Reserved This bit is always read as 1. The write value should always be 1. 11 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 1 R Reserved This bit is always read as 1. The write value should always be 1. Rev. 3.00 Jun. 18, 2008 Page 884 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 7, 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PA13MD[1:0] 00 R/W PA13 Mode Select the function of the PA13/WE1/DQMLU/WE/POE7 pin. 00: PA13 I/O (port) 01: WE1/DQMLU/WE output (BSC) 10: Setting prohibited 11: POE7 input (POE2) 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PA12MD[1:0] 00 R/W PA12 Mode Select the function of the PA12/WE0/DQMLL/POE6 pin. 00: PA12 I/O (port) 01: WE0/DQMLL output (BSC) 10: Setting prohibited 11: POE6 input (POE2) Rev. 3.00 Jun. 18, 2008 Page 885 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (5) Port A Control Register L3 (PACRL3) Bit: 15 - 14 - 13 12 11 - 10 - 9 - 8 - 7 - 6 5 PA9MD[2:0] 4 3 - 2 1 PA8MD[2:0] 0 PA11MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 1 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PA11MD[1:0] 00 R/W PA11 Mode Select the function of the PA11/CS1/POE5 pin. 00: PA11 I/O (port) 01: CS1 output (BSC) 10: Setting prohibited 11: POE5 input (POE2) 11 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 1 R Reserved This bit is always read as 1. The write value should always be 1. 7 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 886 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 6 to 4 Bit Name PA9MD[2:0] Initial Value 000 R/W R/W Description PA9 Mode Select the function of the PA9/TCLKD/IRQ3/FRAME/CKE pin. 000: PA9 I/O (port) 001: TCLKD input (MTU2) 010: IRQ3 input (INTC) 011: FRAME output (BSC) 100: Setting prohibited 101: CKE output (BSC) 110: Setting prohibited 111: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PA8MD[2:0] 000 R/W PA8 Mode Select the function of the PA8/TCLKC/IRQ2/RD/WR pin. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 010: IRQ2 input (INTC) 011: Setting prohibited 100: Setting prohibited 101: RD/WR output (BSC) 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 887 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (6) Port A Control Register L2 (PACRL2) Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 5 PA5MD[2:0] 4 3 - 2 1 PA4MD[2:0] 0 PA7MD[1:0] PA6MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PA7MD[1:0] 00 R/W PA7 Mode Select the function of the PA7/TCLKB/CS3 pin. 00: PA7 I/O (port) 01: TCLKB input (MTU2) 10: CS3 output (BSC) 11: Setting prohibited 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PA6MD[1:0] 00 R/W PA6 Mode Select the function of the PA6/TCLKA/CS2 pin. 00: PA6 I/O (port) 01: TCLKA input (MTU2) 10: CS2 output (BSC) 11: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 888 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 6 to 4 Bit Name Initial Value R/W R/W Description PA5 Mode Select the function of the PA5/SCK1/DREQ1/IRQ1/A22 pin. 000: PA5 I/O (port) 001: SCK1 I/O (SCIF1) 010: DREQ1 input (DMAC) 011: IRQ1 input (INTC) 100: Setting prohibited 101: A22 output (address) 110: Setting prohibited 111: Setting prohibited PA5MD[2:0] 000 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PA4MD[2:0] 000 R/W PA4 Mode Select the function of the PA4/TxD1/A23 pin. 000: PA4 I/O (port) 001: TxD1 output (SCIF1) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: A23 output (address) 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 889 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (7) Port A Control Register L1 (PACRL1) Bit: 15 - 14 13 PA3MD[2:0] 12 11 - 10 9 PA2MD[2:0] 8 7 - 6 5 PA1MD[2:0] 4 3 - 2 1 PA0MD[2:0] 0 Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PA3MD[2:0] 000 R/W PA3 Mode Select the function of the PA3/RxD1/A24 pin. 000: PA3 I/O (port) 001: RxD1 input (SCIF1) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: A24 output (address) 110: Setting prohibited 111: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PA2MD[2:0] 000 R/W PA2 Mode Select the function of the PA2/SCK0/DREQ0/IRQ0/A25 pin. 000: PA2 I/O (port) 001: SCK0 I/O (SCIF0) 010: DREQ0 input (DMAC) 011: IRQ0 input (INTC) 100: Setting prohibited 101: A25 output (address) 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 890 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PA1MD[2:0] 000 R/W PA1 Mode Select the function of the PA1/TxD0/PINT1/CS5/CE1A pin. 000: PA1 I/O (port) 001: TxD0 output (SCIF0) 010: Setting prohibited 011: PINT1 input (INTC) 100: Setting prohibited 101: CS5/CE1A output (BSC) 110: Setting prohibited 111: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PA0MD[2:0] 000 R/W PA0 Mode Select the function of the PA0/RxD0/PINT0/CS4 pin. 000: PA0 I/O (port) 001: RxD0 input (SCIF0) 010: Setting prohibited 011: PINT0 input (INTC) 100: Setting prohibited 101: CS4 output (BSC) 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 891 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2.3 Port B I/O Register (PBIOR) PBIOR is a 16-bit readable/writable register that is used to set the pins on port B as inputs or outputs. Bits PB9IOR, PB5IOR, and PB4IOR correspond to pins PB9/IRQ7/A21/ADTRG, PB5/IRQ3/POE3/CASL, and PB4/IRQ2/POE2/RASL, respectively. PBIOR is enabled when the port B pins are functioning as general-purpose inputs/outputs (PB9, PB5, and PB4). In other states, PBIOR is disabled. A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 10, 8 to 6, and 3 to 0 of PBIOR are reserved. These bits are always read as 0. The write value should always be 0. PBIOR is initialized to H'0000 by a power-on reset; however, the register is not initialized by a manual reset or in sleep mode or software standby mode. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PB9 IOR 8 - 7 - 6 - 5 PB5 IOR 4 PB4 IOR 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 19.2.4 Port B Control Registers 1 to 3 (PBCR1 to PBCR3) PBCR1 to PBCR3 are 16-bit readable/writable registers that are used to select the function of the multiplexed pins on port B. PBCR1 to PBCR3 are initialized to the values shown in table 19.7 by a power-on reset; however, the registers are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port B Control Register 3 (PBCR3) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 PB9MD[2:0] 4 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 1 R 0 R Rev. 3.00 Jun. 18, 2008 Page 892 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 15 to 7 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 6 to 4 PB9MD[2:0] 000 R/W PB9 Mode Select the function of the PB9/IRQ7/A21/ADTRG/POE8 pin. 000: PB9 I/O (port) 001: IRQ7 input (INTC) 010: A21 output (address) 011: ADTRG input (ADC) 100: Setting prohibited 101: Setting prohibited 110: POE8 input (POE2) 111: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 1 R Reserved This bit is always read as 1. The write value should always be 1. 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 893 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (2) Port B Control Register 2 (PBCR2) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 PB5MD[2:0] 4 3 - 2 1 PB4MD[2:0] 0 Initial value: R/W: 0 R 0 R 1 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 1 R Reserved This bit is always read as 1. The write value should always be 1. 12 to 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 1 R Reserved This bit is always read as 1. The write value should always be 1. 8, 7 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 to 4 PB5MD[2:0] 000 R/W PB5 Mode Select the function of the PB5/IRQ3/POE3/CASL pin. 000: PB5 I/O (port) 001: IRQ3 input (INTC) 010: POE3 input (POE2) 011: Setting prohibited 100: CASL output (BSC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 894 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 2 to 0 Bit Name Initial Value R/W R/W Description PB4 Mode Select the function of the PB4/IRQ2/POE2/RASL pin. 000: PB4 I/O (port) 001: IRQ2 input (INTC) 010: POE2 input (POE2) 011: Setting prohibited 100: RASL output (BSC) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PB4MD[2:0] 000 (3) Port B Control Register 1 (PBCR1) Bit: 15 - 14 13 PB3MD[2:0] 12 11 - 10 9 PB2MD[2:0] 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 1 R 0 R 0 R 0 R 1 R Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PB3MD[2:0] 000 R/W PB3 Mode Select the function of the PB3/IRQ1/POE1/SDA pin. 000: PB3 input (port) 001: IRQ1 input (INTC) 010: POE1 input (POE2) 011: Setting prohibited 100: SDA I/O (IIC3) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 895 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 11 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PB2MD[2:0] 000 R/W PB2 Mode Select the function of the PB2/IRQ0/POE0/SCL pin. 000: PB2 input (port) 001: IRQ0 input (INTC) 010: POE0 input (POE2) 011: Setting prohibited 100: SCL I/O (IIC3) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 1 R Reserved This bit is always read as 1. The write value should always be 1. 3 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 1 R Reserved This bit is always read as 1. The write value should always be 1. Rev. 3.00 Jun. 18, 2008 Page 896 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2.5 Port C I/O Register L (PCIORL) PCIORL is a 16-bit readable/writable register that is used to set the pins on port C as inputs or outputs. Bits PC1IOR and PC0IOR correspond to pins PC1/A1 and PC0/A0, respectively. PCIORL is enabled when the port C pins are functioning as general-purpose inputs/outputs (PC1 and PC0). In other states, PCIORL is disabled. A given pin on port C will be an output pin if the corresponding bit in PCIORL is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 2 of PCIORL are reserved. These bits are always read as 0. The write value should always be 0. PCIORL is initialized to H'0000 by a power-on reset; however, the register is not initialized by a manual reset or in sleep mode or software standby mode. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 PC1 IOR 0 PC0 IOR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 19.2.6 Port C Control Register L1 (PCCRL1) PCCRL1 is a 16-bit readable/writable register that is used to select the functions of the multiplexed pins on port C. PCCRL1 is initialized to the value shown in table 19.8 by a power-on reset; however, the register is not initialized by a manual reset or in sleep mode or software standby mode. Table 19.8 Initial Value of Port C Control Register Initial Value Register Name PCCRL1 Area 0: 32-Bit Mode H'1100 Area 0: 16-Bit Mode H'1110 Area 0: 8-Bit Mode H'1111 Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 PC1 MD 3 - 2 - 1 - 0 PC0 MD Initial value: R/W: 0 R 0 R 0 R 1 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0/1* R/W 0 R 0 R 0 R 0/1* R/W Note: * The initial value depends on the operating mode of the LSI. Rev. 3.00 Jun. 18, 2008 Page 897 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 15 to 13 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 1 R Reserved This bit is always read as 1. The write value should always be 1. 11 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 1 R Reserved This bit is always read as 1. The write value should always be 1. 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 PC1MD 0/1* R/W PC1 Mode Select the function of the PC1/A1 pin. * Area 0: 32-bit mode 0: PC1 I/O (port) (initial value) 1: A1 output (address) * Area 0: 16-bit mode 0: Setting prohibited 1: A1 output (address) (initial value) * Area 0: 8-bit mode 0: Setting prohibited 1: A1 output (address) (initial value) 3 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 898 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 0 Bit Name PC0MD Initial Value 0/1* R/W R/W Description PC0 Mode Select the function of the PC0/A0 pin. * Area 0: 32-bit mode 0: PC0 I/O (port) (initial value) 1: A0 output (address) * Area 0: 16-bit mode 0: PC0 I/O (port) (initial value) 1: A0 output (address) * Area 0: 8-bit mode 0: Setting prohibited 1: A0 output (address) (initial value) Note: * The initial value depends on the operating mode of the LSI. 19.2.7 Port D I/O Registers H, L (PDIORH, PDIORL) PDIORH and PDIORL are 16-bit readable/writable registers that are used to set the pins on port D as inputs or outputs. Bits PD31IOR to PD8IOR correspond to pins PD31/D31/ADTRG/TIOC3AS to PD8/D8/TIOC3AS. PDIORH and PDIORL are enabled when the port D pins are functioning as general-purpose inputs/outputs (PD31 to PD8) or the TIOC pin is functioning as inputs/outputs of MTU2S. In other states, they are disabled. A given pin on port D will be an output pin if the corresponding bit in PDIORH or PDIORL is set to 1, and an input pin if the bit is cleared to 0. Bits 7 and 0 of PDIORL are reserved. These bits are always read as 0. The write value should always be 0. PDIORH and PDIORL are initialized to H'0000 by a power-on; however, the registers are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port D I/O Register H (PDIORH) Bit: 15 PD31 IOR 14 PD30 IOR 13 PD29 IOR 12 PD28 IOR 11 PD27 IOR 10 PD26 IOR 9 PD25 IOR 8 PD24 IOR 7 PD23 IOR 6 PD22 IOR 5 PD21 IOR 4 PD20 IOR 3 PD19 IOR 2 PD18 IOR 1 PD17 IOR 0 PD16 IOR Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 899 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (2) Port D I/O Register L (PDIORL) Bit: 15 PD15 IOR 14 PD14 IOR 13 PD13 IOR 12 PD12 IOR 11 PD11 IOR 10 PD10 IOR 9 PD9 IOR 8 PD8 IOR 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 19.2.8 Port D Control Registers H1 to H4, L3, L4 (PDCRH1 to PDCRH4, PDCRL3, PDCRL4) PDCRH1 to PDCRH4, PDCRL3, and PDCRL4 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port D. PDCRH1 to PDCRH4, PDCRL3, and PDCRL4 are initialized to the values shown in table 19.9 by a power-on reset; however, the registers are not initialized by a manual reset or in sleep mode or software standby mode. Table 19.9 Initial Values of Port D Control Registers Initial Value Register Name PDCRH4 PDCRH3 PDCRH2 PDCRH1 PDCRL4 PDCRL3 Area 0: 32-Bit Mode H'1111 H'1111 H'1111 H'1111 H'1111 H'1111 Area 0: 16-Bit Mode H'0000 H'0000 H'0000 H'0000 H'1111 H'1111 Area 0: 8-Bit Mode H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Rev. 3.00 Jun. 18, 2008 Page 900 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (1) Port D Control Register H4 (PDCRH4) Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 - 5 4 3 - 2 - 1 0 PD31MD[1:0] PD30MD[1:0] PD29MD[1:0] PD28MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W Note: * The initial value depends on the operating mode of the LSI. Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PD31MD[1:0] 00*, 01* R/W PD31 Mode Select the function of the PD31/D31/ADTRG/TIOC3AS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D31 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD31 I/O (port) (initial value) 01: D31 I/O (data) 10: ADTRG input (ADC) 11: TIOC3AS I/O (MTU2S) * Area 0: 8-bit mode 00: PD31 I/O (port) (initial value) 01: D31 I/O (data) 10: ADTRG input (ADC) 11: TIOC3AS I/O (MTU2S) 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 901 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 9, 8 Bit Name Initial Value R/W Description Select the function of the PD30/D30/IRQOUT/REFOUT/TIOC3CS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D30 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD30 I/O (port) (initial value) 01: D30 I/O (data) 10: IRQOUT/REFOUT output (INTC/BSC) 11: TIOC3CS I/O (MTU2S) * Area 0: 8-bit mode 00: PD30 I/O (port) (initial value) 01: D30 I/O (data) 10: IRQOUT/REFOUT output (INTC/BSC) 11: TIOC3CS I/O (MTU2S) PD30MD[1:0] 00*, 01* R/W PD30 Mode 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 902 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 5, 4 Bit Name Initial Value R/W Description Select the function of the PD29/D29/CS3/TIOC3BS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D29 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD29 I/O (port) (initial value) 01: D29 I/O (data) 10: CS3 output (BSC) 11: TIOC3BS I/O (MTU2S) * Area 0: 8-bit mode 00: PD29 I/O (port) (initial value) 01: D29 I/O (data) 10: CS3 output (BSC) 11: TIOC3BS I/O (MTU2S) PD29MD[1:0] 00*, 01* R/W PD29 Mode 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 903 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 1, 0 Bit Name Initial Value R/W Description PD28MD[1:0] 00*, 01* R/W PD28 Mode Select the function of the PD28/D28/CS2/TIOC3DS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D28 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD28 I/O (port) (initial value) 01: D28 I/O (data) 10: CS2 output (BSC) 11: TIOC3DS I/O (MTU2S) * Area 0: 8-bit mode 00: PD28 I/O (port) (initial value) 01: D28 I/O (data) 10: CS2 output (BSC) 11: TIOC3DS I/O (MTU2S) Note: * The initial value depends on the operating mode of the LSI. Rev. 3.00 Jun. 18, 2008 Page 904 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (2) Port D Control Register H3 (PDCRH3) Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 - 5 4 3 - 2 - 1 0 PD27MD[1:0] PD26MD[1:0] PD25MD[1:0] PD24MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W Note: * The initial value depends on the operating mode of the LSI. Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PD27MD[1:0] 00*, 01* R/W PD27 Mode Select the function of the PD27/D27/DACK1/TIOC4AS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D27 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD27 I/O (port) (initial value) 01: D27 I/O (data) 10: DACK1 output (DMAC) 11: TIOC4AS I/O (MTU2S) * Area 0: 8-bit mode 00: PD27 I/O (port) (initial value) 01: D27 I/O (data) 10: DACK1 output (DMAC) 11: TIOC4AS I/O (MTU2S) 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 905 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 9, 8 Bit Name Initial Value R/W Description PD26 Mode Select the function of the PD26/D26/DACK0/TIOC4BS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D26 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD26 I/O (port) (initial value) 01: D26 I/O (data) 10: DACK0 output (DMAC) 11: TIOC4BS I/O (MTU2S) * Area 0: 8-bit mode 00: PD26 I/O (port) (initial value) 01: D26 I/O (data) 10: DACK0 output (DMAC) 11: TIOC4BS I/O (MTU2S) PD26MD[1:0] 00*, 01* R/W 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 906 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 5, 4 Bit Name Initial Value R/W Description PD25 Mode Select the function of the PD25/D25/DREQ1/TIOC4CS pin. * Area 0: 32-bit mode 00: PD25 I/O (port) 01: D25 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD25 I/O (port) (initial value) 01: D25 I/O (data) 10: DREQ1 input (DMAC) 11: TIOC4CS I/O (MTU2S) * Area 0: 8-bit mode 00: PD25 I/O (port) (initial value) 01: D25 I/O (data) 10: DREQ1 input (DMAC) 11: TIOC4CS I/O (MTU2S) PD25MD[1:0] 00*, 01* R/W 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 907 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 1, 0 Bit Name Initial Value R/W Description PD24 Mode Select the function of the PD24/D24/DREQ0/TIOC4DS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D24 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD24 I/O (port) (initial value) 01: D24 I/O (data) 10: DREQ0 input (DMAC) 11: TIOC4DS I/O (MTU2S) * Area 0: 8-bit mode 00: PD24 I/O (port) (initial value) 01: D24 I/O (data) 10: DREQ0 input (DMAC) 11: TIOC4DS I/O (MTU2S) PD24MD[1:0] 00*, 01* R/W Note: * The initial value depends on the operating mode of the LSI. Rev. 3.00 Jun. 18, 2008 Page 908 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (3) Port D Control Register H2 (PDCRH2) Bit: 15 - 14 - 13 12 11 - 10 9 PD22MD[2:0] 8 7 - 6 5 PD21MD[2:0] 4 3 - 2 1 PD20MD[2:0] 0 PD23MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R/W 0 R/W 0/1* R/W 0 R 0 R/W 0 R/W 0/1* R/W 0 R 0 R/W 0 R/W 0/1* R/W Note: * The initial value depends on the operating mode of the LSI. Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PD23MD[1:0] 00*, 01* R/W PD23 Mode Select the function of the PD23/D23/IRQ7 pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D23 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: PD23 I/O (port) (initial value) 01: D23 I/O (data) 10: IRQ7 input (INTC) 11: Setting prohibited * Area 0: 8-bit mode 00: PD23 I/O (port) (initial value) 01: D23 I/O (data) 10: IRQ7 input (INTC) 11: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 909 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 10 to 8 Bit Name Initial Value R/W R/W Description PD22 Mode Select the function of the PD22/D22/IRQ6/TIC5US pin. * Area 0: 32-bit mode 000: Setting prohibited 001: D22 I/O (data) (initial value) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 16-bit mode 000: PD22 I/O (port) (initial value) 001: D22 I/O (data) 010: IRQ6 input (INTC) 011: Setting prohibited 100: TIC5US input (MTU2S) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 8-bit mode 000: PD22 I/O (port) (initial value) 001: D22 I/O (data) 010: IRQ6 input (INTC) 011: Setting prohibited 100: TIC5US input (MTU2S) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PD22MD[2:0] 000*, 001* 7 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 910 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 6 to 4 Bit Name Initial Value R/W R/W Description PD21 Mode Select the function of the PD21/D21/IRQ5/TIC5VS pin. * Area 0: 32-bit mode 000: Setting prohibited 001: D21 I/O (data) (initial value) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 16-bit mode 000: PD21 I/O (port) (initial value) 001: D21 I/O (data) 010: IRQ5 input (INTC) 011: Setting prohibited 100: TIC5VS input (MTU2S) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 8-bit mode 000: PD21 I/O (port) (initial value) 001: D21 I/O (data) 010: IRQ5 input (INTC) 011: Setting prohibited 100: TIC5VS input (MTU2S) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PD21MD[2:0] 000*, 001* 3 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 911 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 2 to 0 Bit Name Initial Value R/W R/W Description PD20 Mode Select the function of the PD20/D20/IRQ4/TIC5WS pin. * Area 0: 32-bit mode 000: Setting prohibited 001: D20 I/O (data) (initial value) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 16-bit mode 000: PD20 I/O (port) (initial value) 001: D20 I/O (data) 010: IRQ4 input (INTC) 011: Setting prohibited 100: TIC5WS input (MTU2S) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 8-bit mode 000: PD20 I/O (port) (initial value) 001: D20 I/O (data) 010: IRQ4 input (INTC) 011: Setting prohibited 100: TIC5WS input (MTU2S) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PD20MD[2:0] 000*, 001* Note: * The initial value depends on the operating mode of the LSI. Rev. 3.00 Jun. 18, 2008 Page 912 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (4) Port D Control Register H1 (PDCRH1) Bit: 15 - 14 13 PD19MD[2:0] 12 11 - 10 9 PD18MD[2:0] 8 7 - 6 5 PD17MD[2:0] 4 3 - 2 1 PD16MD[2:0] 0 Initial value: R/W: 0 R 0 R/W 0 R/W 0/1* R/W 0 R 0 R/W 0 R/W 0/1* R/W 0 R 0 R/W 0 R/W 0/1* R/W 0 R 0 R/W 0 R/W 0/1* R/W Note: * The initial value depends on the operating mode of the LSI. Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 913 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit Bit Name Initial Value R/W R/W Description PD19 Mode Select the function of the PD19/D19/IRQ3/POE7 pin. * Area 0: 32-bit mode 000: Setting prohibited 001: D19 I/O (data) (initial value) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 16-bit mode 000: PD19 I/O (port) (initial value) 001: D19 I/O (data) 010: IRQ3 input (INTC) 011: Setting prohibited 100: POE7 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 8-bit mode 000: PD19 I/O (port) (initial value) 001: D19 I/O (data) 010: IRQ3 input (INTC) 011: Setting prohibited 100: POE7 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 14 to 12 PD19MD[2:0] 000*, 001* 11 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 914 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 10 to 8 Bit Name Initial Value R/W R/W Description PD18 Mode Select the function of the PD18/D18/IRQ2/POE6 pin. * Area 0: 32-bit mode 000: Setting prohibited 001: D18 I/O (data) (initial value) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 16-bit mode 000: PD18 I/O (port) (initial value) 001: D18 I/O (data) 010: IRQ2 input (INTC) 011: Setting prohibited 100: POE6 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 8-bit mode 000: PD18 I/O (port) (initial value) 001: D18 I/O (data) 010: IRQ2 input (INTC) 011: Setting prohibited 100: POE6 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PD18MD[2:0] 000*, 001* 7 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 915 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 6 to 4 Bit Name Initial Value R/W R/W Description PD17 Mode Select the function of the PD17/D17/IRQ1/POE5 pin. * Area 0: 32-bit mode 000: Setting prohibited 001: D17 I/O (data) (initial value) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 16-bit mode 000: PD17 I/O (port) (initial value) 001: D17 I/O (data) 010: IRQ1 input (INTC) 011: Setting prohibited 100: POE5 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 8-bit mode 000: PD17 I/O (port) (initial value) 001: D17 I/O (data) 010: IRQ1 input (INTC) 011: Setting prohibited 100: POE5 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PD17MD[2:0] 000*, 001* 3 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 916 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 2 to 0 Bit Name Initial Value R/W R/W Description PD16 Mode Select the function of the PD16/D16/IRQ0/POE4 pin. * Area 0: 32-bit mode 000: Setting prohibited 001: D16 I/O (data) (initial value) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 16-bit mode 000: PD16 I/O (port) (initial value) 001: D16 I/O (data) 010: IRQ0 input (INTC) 011: Setting prohibited 100: POE4 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited * Area 0: 8-bit mode 000: PD16 I/O (port) (initial value) 001: D16 I/O (data) 010: IRQ0 input (INTC) 011: Setting prohibited 100: POE4 input (POE2) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited PD16MD[2:0] 000*, 001* Note: * The initial value depends on the operating mode of the LSI. Rev. 3.00 Jun. 18, 2008 Page 917 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (5) Port D Control Register L4 (PDCRL4) Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 - 5 4 3 - 2 - 1 0 PD15MD[1:0] PD14MD[1:0] PD13MD[1:0] PD12MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W Note: * The initial value depends on the operating mode of the LSI. Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PD15MD[1:0] 00*, 01* R/W PD15 Mode Select the function of the PD15/D15/TIOC4DS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D15 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D15 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD15 I/O (port) (initial value) 01: D15 I/O (data) 10: Setting prohibited 11: TIOC4DS I/O (MTU2S) 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 918 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 9, 8 Bit Name Initial Value R/W Description PD14 Mode Select the function of the PD14/D14/TIOC4CS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D14 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D14 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD14 I/O (port) (initial value) 01: D14 I/O (data) 10: Setting prohibited 11: TIOC4CS I/O (MTU2S) PD14MD[1:0] 00*, 01* R/W 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 919 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 5, 4 Bit Name Initial Value R/W Description PD13 Mode Select the function of the PD13/D13/TIOC4BS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D13 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D13 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD13 I/O (port) (initial value) 01: D13 I/O (data) 10: Setting prohibited 11: TIOC4BS I/O (MTU2S) PD13MD[1:0] 00*, 01* R/W 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 920 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 1, 0 Bit Name Initial Value R/W Description PD12 Mode Select the function of the PD12/D12/TIOC4AS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D12 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D12 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD12 I/O (port) (initial value) 01: D12 I/O (data) 10: Setting prohibited 11: TIOC4AS I/O (MTU2S) PD12MD[1:0] 00*, 01* R/W Note: * The initial value depends on the operating mode of the LSI. Rev. 3.00 Jun. 18, 2008 Page 921 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (6) Port D Control Register L3 (PDCRL3) Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 - 5 4 3 - 2 - 1 0 PD11MD[1:0] PD10MD[1:0] PD9MD[1:0] PD8MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W 0 R 0 R 0 R/W 0/1* R/W Note: * The initial value depends on the operating mode of the LSI. Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PD11MD[1:0] 00*, 01* R/W PD11 Mode Select the function of the PD11/D11/TIOC3DS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D11 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D11 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD11 I/O (port) (initial value) 01: D11 I/O (data) 10: Setting prohibited 11: TIOC3DS I/O (MTU2S) 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 922 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 9, 8 Bit Name Initial Value R/W Description PD10 Mode Select the function of the PD10/D10/TIOC3CS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D10 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D10 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD10 I/O (port) (initial value) 01: D10 I/O (data) 10: Setting prohibited 11: TIOC3CS I/O (MTU2S) PD10MD[1:0] 00*, 01* R/W 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 923 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 5, 4 Bit Name PD9MD[1:0] Initial Value R/W Description PD9 Mode Select the function of the PD9/D9/TIOC3BS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D9 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D9 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD9 I/O (port) (initial value) 01: D9 I/O (data) 10: Setting prohibited 11: TIOC3BS I/O (MTU2S) 00*, 01* R/W 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 924 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 1, 0 Bit Name PD8MD[1:0] Initial Value R/W Description PD8 Mode Select the function of the PD8/D8/TIOC3AS pin. * Area 0: 32-bit mode 00: Setting prohibited 01: D8 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 16-bit mode 00: Setting prohibited 01: D8 I/O (data) (initial value) 10: Setting prohibited 11: Setting prohibited * Area 0: 8-bit mode 00: PD8 I/O (port) (initial value) 01: D8 I/O (data) 10: Setting prohibited 11: TIOC3AS I/O (MTU2S) 00*, 01* R/W Note: * The initial value depends on the operating mode of the LSI. Rev. 3.00 Jun. 18, 2008 Page 925 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2.9 Port E I/O Registers H, L (PEIORH, PEIORL) PEIORH and PEIORL are 16-bit readable/writable registers that are used to set the pins on port E as inputs or outputs. PE16IOR to PE0IOR correspond to pins PE16/CS8 to PE0/TIOC0A/DREQ0. PEIORH and PEIORL are enabled when the port E pins are functioning as general-purpose inputs/outputs (PE16 to PE0) or the TIOC pin is functioning as inputs/outputs of MTU2. In other states, they are disabled. A given pin on port E will be an output pin if the corresponding bit in PEIORH or PEIORL is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 1 of PEIORH are reserved. These bits are always read as 0. The write value should always be 0. PEIORH and PEIORL are initialized to H'0000 by a power-on reset; however, the registers are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port E I/O Register H (PEIORH) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PE16 IOR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W (2) Port E I/O Register L (PEIORL) Bit: 15 PE15 IOR 14 PE14 IOR 13 PE13 IOR 12 PE12 IOR 11 PE11 IOR 10 PE10 IOR 9 PE9 IOR 8 PE8 IOR 7 PE7 IOR 6 PE6 IOR 5 PE5 IOR 4 PE4 IOR 3 PE3 IOR 2 PE2 IOR 1 PE1 IOR 0 PE0 IOR Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.00 Jun. 18, 2008 Page 926 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2.10 Port E Control Registers H1, L1 to L4 (PECRH1, PECRL1 to PECRL4) PECRH1 and PECRL1 to PECRL4 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port E. PECRH1 and PECRL1 to PECRL4 are initialized to H'0000 by a power-on reset; however, the registers are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port E Control Register H1 (PECRH1) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 PE16MD[2:0] 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 15 to 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 PE16MD[2:0] 000 R/W PE16 Mode Select the function of the PE16/CS8 pin. 000: PE16 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: CS8 output (BSC) 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 927 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (2) Port E Control Register L4 (PECRL4) Bit: 15 - 14 13 PE15MD[2:0] 12 11 - 10 9 PE14MD[2:0] 8 7 - 6 - 5 4 3 - 2 - 1 0 PE13MD[1:0] PE12MD[1:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PE15MD[2:0] 000 R/W PE15 Mode Select the function of the PE15/TIOC4D/DACK1/IRQOUT/REFOUT/CKE pin. 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 010: DACK1 output (DMAC) 011: IRQOUT/REFOUT output (INTC/BSC) 100: Setting prohibited 101: CKE output (BSC) 110: Setting prohibited 111: Setting prohibited 11 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 928 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 10 to 8 Bit Name Initial Value R/W R/W Description PE14 Mode Select the function of the PE14/TIOC4C/DACK0/WE3/DQMUU/ICIOWR/AH pin. 000: PE14 I/O (port) 001: TIOC4C I/O (MTU2) 010: DACK0 output (DMAC) 011: Setting prohibited 100: Setting prohibited 101: WE3/DQMUU/ICIOWR/AH output (BSC) 110: Setting prohibited 111: Setting prohibited PE14MD[2:0] 000 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PE13MD[1:0] 00 R/W PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU2) 10: MRES input (system control) 11: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PE12MD[1:0] 00 R/W PE12 Mode Select the function of the PE12/TIOC4A/TxD3 pin. 00: PE12 I/O (port) 01: TIOC4A I/O (MTU2) 10: Setting prohibited 11: TxD3 output (SCIF3) Rev. 3.00 Jun. 18, 2008 Page 929 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (3) Port E Control Register L3 (PECRL3) Bit: 15 - 14 13 PE11MD[2:0] 12 11 - 10 - 9 8 7 - 6 5 PE9MD[2:0] 4 3 - 2 - 1 0 PE10MD[1:0] PE8MD[1:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PE11MD[2:0] 000 R/W PE11 Mode Select the function of the PE11/TIOC3D/RxD3/CTS3 pin. 000: PE11 I/O (port) 001: TIOC3D I/O (MTU2) 010: Setting prohibited 011: RxD3 input (SCIF3) 100: CTS3 I/O (SCIF3) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PE10MD[1:0] 00 R/W PE10 Mode Select the function of the PE10/TIOC3C/TxD2 pin. 00: PE10 I/O (port) 01: TIOC3C I/O (MTU2) 10: TxD2 output (SCIF2) 11: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 930 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 6 to 4 Bit Name PE9MD[2:0] Initial Value 000 R/W R/W Description PE9 Mode Select the function of the PE9/TIOC3B/SCK3/RTS3 pin. 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) 010: Setting prohibited 011: SCK3 I/O (SCIF3) 100: RTS3 I/O (SCIF3) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PE8MD[1:0] 00 R/W PE8 Mode Select the function of the PE8/TIOC3A/SCK2 pin. 00: PE8 I/O (port) 01: TIOC3A I/O (MTU2) 10: SCK2 I/O (SCIF2) 11: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 931 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (4) Port E Control Register L2 (PECRL2) Bit: 15 - 14 13 PE7MD[2:0] 12 11 - 10 9 PE6MD[2:0] 8 7 - 6 5 PE5MD[2:0] 4 3 - 2 1 PE4MD[2:0] 0 Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PE7MD[2:0] 000 R/W PE7 Mode Select the function of the PE7/TIOC2B/RxD2/BS/UBCTRG pin. 000: PE7 I/O (port) 001: TIOC2B I/O (MTU2) 010: RxD2 input (SCIF2) 011: BS output (BSC) 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: UBCTRG output (UBC) 11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PE6MD[2:0] 000 R/W PE6 Mode Select the function of the PE6/TIOC2A/SCK3/CS7 pin. 000: PE6 I/O (port) 001: TIOC2A I/O (MTU2) 010: SCK3 I/O (SCIF3) 011: Setting prohibited 100: Setting prohibited 101: CS7 output (BSC) 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 932 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PE5MD[2:0] 000 R/W PE5 Mode Select the function of the PE5/TIOC1B/TxD3/CS6/CE1B pin. 000: PE5 I/O (port) 001: TIOC1B I/O (MTU2) 010: TxD3 output (SCIF3) 011: Setting prohibited 100: Setting prohibited 101: CS6/CE1B output (BSC) 110: Setting prohibited 111: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PE4MD[2:0] 000 R/W PE4 Mode Select the function of the PE4/TIOC1A/RxD3/IOIS16 pin. 000: PE4 I/O (port) 001: TIOC1A I/O (MTU2) 010: RxD3 input (SCIF3) 011: Setting prohibited 100: Setting prohibited 101: IOIS16 input (BSC) 110: Setting prohibited 111: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 933 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) (5) Port E Control Register L1 (PECRL1) Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 - 5 4 3 - 2 - 1 0 PE3MD[1:0] PE2MD[1:0] PE1MD[1:0] PE0MD[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PE3MD[1:0] 00 R/W PE3 Mode Select the function of the PE3/TIOC0D/TEND1 pin. 00: PE3 I/O (port) 01: TIOC0D I/O (MTU2) 10: TEND1 output (DMAC) 11: Setting prohibited 11, 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PE2MD[1:0] 00 R/W PE2 Mode Select the function of the PE2/TIOC0C/DREQ1 pin. 00: PE2 I/O (port) 01: TIOC0C I/O (MTU2) 10: DREQ1 input (DMAC) 11: Setting prohibited 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PE1MD[1:0] 00 R/W PE1 Mode Select the function of the PE1/TIOC0B/TEND0 pin. 00: PE1 I/O (port) 01: TIOC0B I/O (MTU2) 10: TEND0 output (DMAC) 11: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 934 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Bit 3, 2 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PE0MD[1:0] 00 R/W PE0 Mode Select the function of the PE0/TIOC0A/DREQ0 pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) 10: DREQ0 input (DMAC) 11: Setting prohibited Rev. 3.00 Jun. 18, 2008 Page 935 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.2.11 IRQOUT Function Control Register (IFCR) IFCR is a 16-bit readable/writable register that is used to control the IRQOUT/REFOUT pin output when it is selected as the multiplexed pin function by port D control register H4 (PDCRH4) and port E control register L4 (PECRL4). When PDCRH4 or PECRL4 selects another function, the IFCR setting does not affect the pin function. IFCR is initialized to H'0000 by a power-on reset; however, the register is not initialized by a manual reset or in sleep mode or software standby mode. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 1 0 IRQMD[3:2] IRQMD[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3, 2 IRQMD[3:2] 00 R/W IRQOUT Mode 3, 2 Select the function of the IRQOUT/REFOUT pin when bits 9 and 8 (PD30MD[1:0]) in PDCRH4 are set to (1, 0). 00: Interrupt request accept signal output 01: Refresh signal output 10: Interrupt request accept signal output or refresh signal output (depends on the operating state) 11: Always high-level output 1, 0 IRQMD[1:0] 00 R/W IRQOUT Mode 1, 0 Select the function of the IRQOUT/REFOUT pin when bits 14 to 12 (PE15MD[2:0]) in PECRL4 are set to (0, 1, 1). 00: Interrupt request accept signal output 01: Refresh signal output 10: Interrupt request accept signal output or refresh signal output (depends on the operating state) 11: Always high-level output Rev. 3.00 Jun. 18, 2008 Page 936 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.3 19.3.1 Switching of Functions in Each Pin Ports A, B, C, D, and E Pin functions of ports A, B, C, D and E are switched by the settings of the port control registers. Tables 19.10 to 19.14 show the relationships between the settings of the port control registers and the pin functions specified. Rev. 3.00 Jun. 18, 2008 Page 937 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Table 19.10 Relationships between Register Settings and Pin Functions (Port A) Function 1 PAnMD[2:0] = Setting Port A register PACRH3 000 (Related Module) PA25 I/O (port) Function 2 PAnMD[2:0] = 001 (Related Module) CE2B output (BSC) PA24 I/O (port) CE2A output (BSC) PA23 I/O (port) WE3/DQMUU/ ICIOWR/ AH output (BSC) PA22 I/O (port) WE2/DQMUL/ ICIORD output (BSC) PA21 I/O (port) CS5/CE1A output (BSC) PA20 I/O (port) CS4 output (BSC) PACRH2 PA19 I/O (port) BACK output (BSC) PA18 I/O (port) BREQ input (BSC) PA17 I/O (port) WAIT input (BSC) PA16 I/O (port) WE3/DQMUU/ ICIOWR/ AH output (BSC) PACRL4 PA13 I/O (port) WE1/DQMLU/W E output (BSC) PA12 I/O (port) WE0/DQMLL output (BSC) PACRL3 PA11 I/O (port) CS1 output (BSC) PA9 I/O (port) TCLKD input (MTU2) PA8 I/O (port) TCLKC input (MTU2) IRQ3 input (INTC) IRQ2 input (INTC) POE7 input (POE2) POE6 input (POE2) POE5 input (POE2) FRAME output (BSC) CKE output (BSC) RD/WR output (BSC) CASU output (BSC) RASU output (BSC) TEND1 output (DMAC) TEND0 output (DMAC) DACK2 output (DMAC) DREQ2 input (DMAC) CKE output (BSC) TIC5U input (MTU2) PINT5 input (INTC) PINT4 input (INTC) PINT3 input (INTC) PINT2 input (INTC) TIC5V input (MTU2) Function 3 PAnMD[2:0] = 010 (Related Module) DACK3 output (DMAC) DREQ3 input (DMAC) TIC5W input (MTU2) Function 4 PAnMD[2:0] = 011 (Related Module) POE8 input (POE2) Function 5 PAnMD[2:0] = 100 (Related Module) PINT7 input (INTC) PINT6 input (INTC) Function 6 PAnMD[2:0] = 101 (Related Module) Function 7 Function 8 Rev. 3.00 Jun. 18, 2008 Page 938 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Function 1 PAnMD[2:0] = Setting Port A register PACRL2 000 (Related Module) PA7 I/O (port) Function 2 PAnMD[2:0] = 001 (Related Module) TCLKB input (MTU2) Function 3 PAnMD[2:0] = 010 (Related Module) CS3 output (BSC) CS2 output (BSC) DREQ1 input (DMAC) Function 4 PAnMD[2:0] = 011 (Related Module) Function 5 PAnMD[2:0] = 100 (Related Module) Function 6 PAnMD[2:0] = 101 (Related Module) Function 7 Function 8 PA6 I/O (port) TCLKA input (MTU2) PA5 I/O (port) SCK1 I/O (SCIF1) IRQ1 input (INTC) A22 output (BSC) PA4 I/O (port) TxD1 output (SCIF1) A23 output (BSC) PACRL1 PA3 I/O (port) RxD1 input (SCIF1) A24 output (BSC) PA2 I/O (port) SCK0 I/O (SCIF0) DREQ0 input (DMAC) IRQ0 input (INTC) PINT1 input (INTC) A25 output (BSC) PA1 I/O (port) TxD0 output (SCIF0) CS5/CE1A output (BSC) PA0 I/O (port) RxD0 input (SCIF0) PINT0 input (INTC) CS4 output (BSC) Table 19.11 Relationships between Register Settings and Pin Functions (Port B) Function 1 PBnMD[2:0] = Setting Port B register PBCR3 000 (Related Module) PB9 I/O (port) Function 2 PBnMD[2:0] = 001 (Related Module) IRQ7 input (INTC) PBCR2 PB5 I/O (port) IRQ3 input (INTC) PB4 I/O (port) IRQ2 input (INTC) PBCR1 PB3 input (port) IRQ1 input (INTC) PB2 input (port) IRQ0 input (INTC) Function 3 PBnMD[2:0] = 010 (Related Module) A21 output (address) POE3 input (POE2) POE2 input (POE2) POE1 input (POE2) POE0 input (POE2) SCL I/O (IIC3) Function 4 PBnMD[2:0] = 011 (Related Module) ADTRG input (ADC) CASL output (BSC) RASL output (BSC) SDA I/O (IIC3) Function 5 PBnMD[2:0] = 100 (Related Module) Function 7 PBnMD[2:0] = Function 110 (Related 6 Module) POE8 input (POE2) Function 8 Rev. 3.00 Jun. 18, 2008 Page 939 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Table 19.12 Relationships between Register Settings and Pin Functions (Port C) Function 1 Setting Port C register PCnMD = 0 (Related Module) Function 2 PCnMD = 1 (Related Module) Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 PCCRL1 PC1 I/O (port) PC0 I/O (port) A1 output (address) A0 output (address) Table 19.13 Relationships between Register Settings and Pin Functions (Port D) Function 1 PDnMD[2:0] = Setting Port D register 000 (Related Module) Function 2 PDnMD[2:0] = 001 (Related Module) D31 I/O (data) Function 3 PDnMD[2:0] = 010 (Related Module) ADTRG input (ADC) PD30 I/O (port) D30 I/O (data) IRQOUT/ REFOUT output (INTC/BSC) PD29 I/O (port) D29 I/O (data) CS3 output (BSC) PD28 I/O (port) D28 I/O (data) CS2 output (BSC) PDCRH3 PD27 I/O (port) D27 I/O (data) DACK1 output (DMAC) PD26 I/O (port) D26 I/O (data) DACK0 output (DMAC) PD25 I/O (port) D25 I/O (data) DREQ1 input (DMAC) PD24 I/O (port) D24 I/O (data) DREQ0 input (DMAC) PDCRH2 PD23 I/O (port) D23 I/O (data) IRQ7 input (INTC) PD22 I/O (port) D22 I/O (data) IRQ6 input (INTC) PD21 I/O (port) D21 I/O (data) IRQ5 input (INTC) TIC5US input (MTU2S) TIC5VS input (MTU2S) TIOC3BS I/O (MTU2S) TIOC3DS I/O (MTU2S) TIOC4AS I/O (MTU2S) TIOC4BS I/O (MTU2S) TIOC4CS I/O (MTU2S) TIOC4DS I/O (MTU2S) Function 4 PDnMD[2:0] = 011 (Related Module) TIOC3AS I/O (MTU2S) TIOC3CS I/O (MTU2S) Function 5 PDnMD[2:0] = 100 (Related Module) Function 6 Function 7 Function 8 PDCRH4 PD31 I/O (port) Rev. 3.00 Jun. 18, 2008 Page 940 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Function 1 PDnMD[2:0] = Setting Port D register PDCRH2 000 (Related Module) PD20 I/O (port) Function 2 PDnMD[2:0] = 001 (Related Module) D20 I/O (data) Function 3 PDnMD[2:0] = 010 (Related Module) IRQ4 input (INTC) Function 4 PDnMD[2:0] = 011 (Related Module) Function 5 PDnMD[2:0] = 100 (Related Module) TIC5WS input (MTU2S) Function 6 Function 7 Function 8 PDCRH1 PD19 I/O (port) D19 I/O (data) IRQ3 input (INTC) POE7 input (POE2) PD18 I/O (port) D18 I/O (data) IRQ2 input (INTC) POE6 input (POE2) PD17 I/O (port) D17 I/O (data) IRQ1 input (INTC) POE5 input (POE2) PD16 I/O (port) D16 I/O (data) IRQ0 input (INTC) POE4 input (POE2) PDCRL4 PD15 I/O (port) D15 I/O (data) TIOC4DS I/O (MTU2S) PD14 I/O (port) D14 I/O (data) TIOC4CS I/O (MTU2S) PD13 I/O (port) D13 I/O (data) TIOC4BS I/O (MTU2S) PD12 I/O (port) D12 I/O (data) TIOC4AS I/O (MTU2S) PDCRL3 PD11 I/O (port) D11 I/O (data) TIOC3DS I/O (MTU2S) PD10 I/O (port) D10 I/O (data) TIOC3CS I/O (MTU2S) PD9 I/O (port) D9 I/O (data) TIOC3BS I/O (MTU2S) PD8 I/O (port) D8 I/O (data) TIOC3AS I/O (MTU2S) Rev. 3.00 Jun. 18, 2008 Page 941 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Table 19.14 Relationships between Register Settings and Pin Functions (Port E) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 8 PEnMD[2:0] = 111 (Related Function 7 Module) PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = Setting Port E register PECRH1 000 (Related Module) 001 (Related Module) 010 (Related Module) 011 (Related Module) 100 (Related Module) 101 (Related Module) CS8 output (BSC) PECRL4 PE15 I/O (port) TIOC4D I/O (MTU2) DACK1 output IRQOUT/ (DMAC) REFOUT output (INTC/BSC) PE14 I/O (port) TIOC4C I/O (MTU2) DACK0 output (DMAC) WE3/DQMUU/ ICIOWR/AH output (BSC) PE13 I/O (port) TIOC4B I/O (MTU2) MRES input (system control) PE12 I/O (port) TIOC4A I/O (MTU2) PECRL3 PE11 I/O (port) TIOC3D I/O (MTU2) PE10 I/O (port) TIOC3C I/O (MTU2) PE9 I/O (port) TIOC3B I/O (MTU2) PE8 I/O (port) TIOC3A I/O (MTU2) PECRL2 PE7 I/O (port) TIOC2B I/O (MTU2) PE6 I/O (port) TIOC2A I/O (MTU2) PE5 I/O (port) TIOC1B I/O (MTU2) PE4 I/O (port) TIOC1A I/O (MTU2) PECRL1 PE3 I/O (port) TIOC0D I/O (MTU2) PE2 I/O (port) TIOC0C I/O (MTU2) SCK2 I/O (SCIF2) RxD2 input (SCIF2) SCK3 I/O (SCIF3) TxD3 output (SCIF3) RxD3 input (SCIF3) TEND1 output (DMAC) DREQ1 input (DMAC) BS output (BSC) CS7 output (BSC) CS6/CE1B output (BSC) IOIS16 input (BSC) UBCTRG output (UBC) TxD2 output (SCIF2) SCK3 I/O (SCIF3) RTS3 I/O (SCIF3) TxD3 output (SCIF3) RxD3 input (SCIF3) CTS3 I/O (SCIF3) CKE output (BSC) PE16 I/O (port) Rev. 3.00 Jun. 18, 2008 Page 942 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 8 PEnMD[2:0] = 111 (Related Function 7 Module) PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = PEnMD[2:0] = Setting Port E register PECRL1 000 (Related Module) PE1 I/O (port) 001 (Related Module) TIOC0B I/O (MTU2) PE0 I/O (port) TIOC0A I/O (MTU2) 010 (Related Module) 011 (Related Module) 100 (Related Module) 101 (Related Module) TEND0 output (DMAC) DREQ0 input (DMAC) 19.3.2 Port F In port F, the analog input pins of A/D converter and the analog output pins of D/A converter are multiplexed. Pin functions are automatically changed by the settings of the A/D control register in A/D converter and D/A control register in D/A converter. (See section 17, A/D Converter (ADC), and section 18, D/A Converter (DAC).) Table 19.15 Switching Pin Function of PF6/AN6/DA0 and PF7/AN7/DA1 DACR Setting Value [DAE, DAOE0, DAE1] (x, 0, 0) ADCSR Setting Value CH[2:0] 110 111 MDS[2] x 0 1 (0, 1, 0) 110 111 x 0 1 (0, 0, 1) 110 111 x 0 1 (x, 1, 1)/(1, 0, 1)/(1, 1, 0) 110 111 x 0 1 Pin Function PF6/AN6/DA0 PF7/AN7/DA1 Remarks AN6 PF6 AN6 AN6/DA0 DA0 AN6/DA0 AN6 PF6 AN6 AN6/DA0 DA0 AN6/DA0 PF7 AN7 AN7 PF7 AN7 AN7 DA1 AN7/DA1 AN7/DA1 DA1 AN7/DA1 AN7/DA1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited [Legend] x: Don't care Note: * Settings marked "setting prohibited" are not allowed because they would result in simultaneous selection of the A/D and D/A conversion functions for the PF6 or PF7 pin. Rev. 3.00 Jun. 18, 2008 Page 943 of 1160 REJ09B0191-0300 Section 19 Pin Function Controller (PFC) 19.4 Usage Notes The multiplexed pins listed in tables 19.1 to 19.6 except pins PB2, PB3, PE7, and PF0 to PF7 include weak keepers in their I/O buffers to prevent the pins from floating into intermediate voltage levels. However, note that the voltage retained in the high-impedance state may fluctuate due to noise. Rev. 3.00 Jun. 18, 2008 Page 944 of 1160 REJ09B0191-0300 Section 20 I/O Ports Section 20 I/O Ports This LSI has six ports: A to F. All port pins are multiplexed with other pin functions. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with data registers for storing the pin data and port registers for reading the states of the pins. 20.1 1. * * * * * * Features Total port number: 79 ports (I/O: 69 ports, Output: 10 ports) Port A: (I/O: 23 ports) Port B: (I/O: 3 ports, Input: 2 ports) Port C: (I/O: 2 ports) Port D: (I/O: 24 ports) Port E: (I/O: 17 ports) Port F: (Input: 8 ports) 2. The following pins in this LSI have weak keeper circuits that prevent the pins from floating into intermediate voltage levels. * Port A: PA0 to PA9, PA11 to PA13, and PA16 to PA25 * Port B: PB4, PB5, and PB9 * Port C: PC0 and PC1 * Port D: PD8 to PD31 * Port E: PE0 to PE6 and PE8 to PE16 The I/O pins include weak keeper circuits that fix the input level high or low when the I/O pins are not driven from outside. Generally in the CMOS products, input levels in unused input pins must be fixed by way of external pull-up or pull-down resistors. However, the I/O pins having weak keeper circuits in this LSI can eliminate these outer circuits and reduce parts number of the system. If the pull-up or pull-down resistors become necessary to fix the pin level, use the resistor of 10 k or smaller. 3. Pin possessing pull-up resistor * The PE7 pin in this LSI possesses a pull-up resistor Rev. 3.00 Jun. 18, 2008 Page 945 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.2 Port A Port A is an input/output port with the 23 pins shown in figure 20.1. PA25 (I/O) / CE2B (output) / DACK3 (output) / PINT7 (input) / POE8 (output) PA24 (I/O) / CE2A (input) / DREQ3 (input) / PINT6 (input) PA23 (I/O) / WE3 (output) / DQMUU (output) / ICIOWR (output) / AH (output) / TIC5W (input) PA22 (I/O) / WE2 (output) / DQMUL (output) / ICIORD (output) / TIC5V (input) PA21 (I/O) / CS5 (output) / CE1A (output) / CASU (output) / TIC5U (input) / PINT5 (input) PA20 (I/O) / CS4 (output) / RASU (output) / PINT4 (input) PA19 (I/O) / BACK (output) / TEND1 (output) / PINT3 (input) PA18 (I/O) / BREQ (input) / TEND0 (output) / PINT2 (input) PA17 (I/O) / WAIT (input) / DACK2 (output) PA16 (I/O) / WE3 (output) / DQMUU (output) / ICIOWR (output) / AH (output) / DREQ2 (input) / CKE (output) PA13 (I/O) / WE1 (output) / DQMLU (output) / WE (output) / POE7 (input) PA12 (I/O) / WE0 (output) / DQMLL (output) / POE6 (input) PA11 (I/O) / CS1 (output) / POE5 (input) PA9 (I/O) / TCLKD (input) / IRQ3 (input) / FRAME (output) / CKE (output) PA8 (I/O) / TCLKC (input) / IRQ2 (input) / RDWR (output) PA7 (I/O) / TCLKB (input) / CS3 (output) PA6 (I/O) / TCLKA (input) / CS2 (output) PA5 (I/O) / SCK1 (I/O) / DREQ1 (input) / IRQ1 (input) / A22 (output) PA4 (I/O) / TxD1 (output) / A23 (output) PA3 (I/O) / RxD1 (input) / A24 (output) PA2 (I/O) / SCK0 (I/O) / DREQ0 (input) / IRQ0 (input) / A25 (output) PA1 (I/O) / TxD0 (output) / PINT1 (input) / CS5 (output) / CE1A (output) PA0 (I/O) / RxD0 (input) / PINT0 (input) / CS4 (output) Port A Figure 20.1 Port A Rev. 3.00 Jun. 18, 2008 Page 946 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.2.1 Register Descriptions Table 20.1 lists the port A registers. Table 20.1 Register Configuration Register Name Port A data register H Port A data register L Port A port register H Port A port register L Abbreviation PADRH PADRL PAPRH PAPRL R/W R/W R/W R R Initial Value H'3C00 H'xx00 H'3xxx H'xxxx Address H'FFFE3800 H'FFFE3802 H'FFFE381C H'FFFE381E Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 20.2.2 Port A Data Registers H, L (PADRH, PADRL) PADRH and PADRL are 16-bit readable/writable registers that store port A data. Bits PA25DR to PA16DR, PA13DR to PA11DR, and PA9DR to PA0DR correspond to pins PA25/CE2B/DACK3/POE8/PINT7 to PA16/WE3/DQMUU/ICIOWR/AH/DREQ2/CKE, PA13/WE1/DQMLU/WE/POE7 to PA11/CS1/POE5, and PA9/TCLKD/IRQ3/FRAME/CKE to PA0/RxD0/PINT0/CS4, respectively. When a pin function is general output, if a value is written to PADRH or PADRL, that value is output directly from the pin, and if PADRH or PADRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PADRH or PADRL is read, the pin state, not the register value, is returned directly. If a value is written to PADRH or PADRL, although that value is written into PADRH or PADRL, it does not affect the pin state. Table 20.2 summarizes PADRH and PADRL read/write operations. PADRH and PADRL are initialized to the respective values shown in table 20.1 by a power-on reset. PADRH and PADRL are not initialized by a manual reset or in sleep mode or software standby mode. Rev. 3.00 Jun. 18, 2008 Page 947 of 1160 REJ09B0191-0300 Section 20 I/O Ports (1) Port A Data Register H (PADRH) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PA25 DR 8 PA24 DR 7 PA23 DR 6 PA22 DR 5 PA21 DR 4 PA20 DR 3 PA19 DR 2 PA18 DR 1 PA17 DR 0 PA16 DR Initial value: R/W: 0 R 0 R 1 R 1 R 1 R 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 to 10 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 9 8 7 6 5 4 3 2 1 0 PA25DR PA24DR PA23DR PA22DR PA21DR PA20DR PA19DR PA18DR PA17DR PA16DR 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W See table 20.2 Rev. 3.00 Jun. 18, 2008 Page 948 of 1160 REJ09B0191-0300 Section 20 I/O Ports (2) Port A Data Register L (PADRL) Bit: 15 - 14 - 13 PA13 DR 12 PA12 DR 11 PA11 DR 10 - 9 PA9 DR 8 PA8 DR 7 PA7 DR 6 PA6 DR 5 PA5 DR 4 PA4 DR 3 PA3 DR 2 PA2 DR 1 PA1 DR 0 PA0 DR Initial value: R/W: R R 0 R/W 0 R/W 0 R/W R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15, 14 Bit Name Initial Value R/W R Description Reserved These bits are always read as undefined values. The write value should always be 0. 13 12 11 10 PA13DR PA12DR PA11DR 0 0 0 R/W R/W R/W R See table 20.2 Reserved This bit is always read as an undefined value. The write value should always be 0. 9 8 7 6 5 4 3 2 1 0 PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W See table 20.2 Rev. 3.00 Jun. 18, 2008 Page 949 of 1160 REJ09B0191-0300 Section 20 I/O Ports Table 20.2 Port A Data Registers H and L (PADRH and PADRL) Read/Write Operations * PADRH bits 9 to 0 and PADRL bits 13 to 11 and 9 to 0 PAIORH, PAIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADRH or PADRL value PADRH or PADRL value Write Can write to PADRH and PADRL, but it has no effect on pin state Can write to PADRH and PADRL, but it has no effect on pin state Value written is output from pin Can write to PADRH and PADRL, but it has no effect on pin state Rev. 3.00 Jun. 18, 2008 Page 950 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.2.3 Port A Port Registers H, L (PAPRH, PAPRL) PAPRH and PAPRL are 16-bit read-only registers, in which bits PA25PR to PA16PR, PA13PR to PA11PR, and PA9PR to PA0PR correspond to pins PA25/CE2B/DACK3/POE8/PINT7 to PA16/WE3/DQMUU/ICIOWR/AH/DREQ2/CKE, PA13/WE1/DQMLU/WE/POE7 to PA11/CS1/POE5, and PA9/TCLKD/IRQ3/FRAME/CKE to PA0/RxD0/PINT0/CS4, respectively. PAPRH and PAPRL always return the states of the pins regardless of the PFC setting. (1) Port A Port Register H (PAPRH) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PA25 PR 8 PA24 PR 7 PA23 PR 6 PA22 PR 5 PA21 PR 4 PA20 PR 3 PA19 PR 2 PA18 PR 1 PA17 PR 0 PA16 PR Initial value: R/W: 0 R 0 R 1 R 1 R 1 R 1 R PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 R R R R R R R R R R Bit 15, 14 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. 13 to 10 All 1 R Reserved These bits are always read as 1 and cannot be modified. 9 8 7 6 5 4 3 2 1 0 PA25PR PA24PR PA23PR PA22PR PA21PR PA20PR PA19PR PA18PR PA17PR PA16PR Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 951 of 1160 REJ09B0191-0300 Section 20 I/O Ports (2) Port A Port Register L (PAPRL) Bit: 15 - 14 - 13 PA13 PR 12 PA12 PR 11 PA11 PR 10 - 9 PA9 PR 8 PA8 PR 7 PA7 PR 6 PA6 PR 5 PA5 PR 4 PA4 PR 3 PA3 PR 2 PA2 PR 1 PA1 PR 0 PA0 PR Initial value: R/W: R R PA13 PA12 PA11 R R R R PA9 R PA8 R PA7 R PA6 R PA5 R PA4 R PA3 R PA2 R PA1 R PA0 R Bit 15, 14 Bit Name Initial Value R/W R Description Reserved These bits are always read as undefined values and cannot be modified. 13 12 11 10 PA13PR PA12PR PA11PR Pin state R Pin state R Pin state R R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Reserved This bit is always read as an undefined value and cannot be modified. 9 8 7 6 5 4 3 2 1 0 PA9PR PA8PR PA7PR PA6PR PA5PR PA4PR PA3PR PA2PR PA1PR PA0PR Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 952 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.3 Port B Port B is an input/output port with the five pins shown in figure 20.2. Port B PB9 (I/O) / IRQ7 (input) / A21 (output) / ADTRG (input) / POE8 (input) PB5 (I/O) / IRQ3 (input) / POE3 (input) / CASL (output) PB4 (I/O) / IRQ2 (input) / POE2 (input) / RASL (output) PB3 (input) / IRQ1 (input) / POE1 (input) / SDA (I/O) PB2 (input) / IRQ0 (input) / POE0 (input) / SCL (I/O) Figure 20.2 Port B 20.3.1 Register Descriptions Table 20.3 lists the port B registers. Table 20.3 Register Configuration Register Name Port B data register Port B port register Abbreviation PBDR PBPR R/W R/W R Initial Value H'0xxx H'0xxx Address H'FFFE3882 H'FFFE389E Access Size 8, 16 8, 16 Rev. 3.00 Jun. 18, 2008 Page 953 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.3.2 Port B Data Register (PBDR) PBDR is a 16-bit readable/writable register that stores port B data. Bits PB9DR and PB5DR to PB2DR correspond to pins PB9/IRQ7/A21/ADTRG/POE8 and PB5/IRQ3/POE3/CASL to PB2/IRQ0/POE0/SCL, respectively. When a pin function is general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PBDR is read, the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR, it does not affect the pin state. Table 20.4 summarizes PBDR read/write operations. PBDR is initialized to the value shown in table 20.3 by a power-on reset. PBDR is not initialized by a manual reset or in sleep mode or software standby mode. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PB9 DR 8 - 7 - 6 - 5 PB5 DR 4 PB4 DR 3 PB3 DR 2 PB2 DR 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W R R R 0 R/W 0 R/W * R * R R R Note: * Depends on the external pin state. Bit 15 to 10 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 to 6 PB9DR 0 R/W R See table 20.4 Reserved These bits are always read as undefined values. The write value should always be 0. 5 4 3 2 1, 0 PB5DR PB4DR PB3DR PB2DR 0 0 R/W R/W See table 20.4 Pin state R Pin state R R Reserved These bits are always read as undefined values. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 954 of 1160 REJ09B0191-0300 Section 20 I/O Ports Table 20.4 Port B Data Register (PBDR) Read/Write Operations * PBDR bits 9, 5, and 4 PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDR value PBDR value Write Can write to PBDR, but it has no effect on pin state Can write to PBDR, but it has no effect on pin state Value written is output from pin Can write to PBDR, but it has no effect on pin state * PBDR bits 3 and 2 Pin Function General input Other than general input Read Pin state Pin state Write Disabled Disabled Rev. 3.00 Jun. 18, 2008 Page 955 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.3.3 Port B Port Register (PBPR) PBPR is a 16-bit read-only register, in which bits PB9PR, PB5PR to PB2PR correspond to pins PB9/IRQ7/A21/ADTRG and PB5/IRQ3/POE3/CASL to PB2/IRQ0/POE0/SCL, respectively. PBPR always returns the states of the pins regardless of the PFC setting. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PB9 PR 8 - 7 - 6 - 5 PB5 PR 4 PB4 PR 3 PB3 PR 2 PB2 PR 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R PB9 R R R R PB5 R PB4 R PB3 R PB2 R R R Bit 15 to 10 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. 9 8 to 6 PB9PR Pin state R R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Reserved These bits are always read as undefined values and cannot be modified. 5 4 3 2 1, 0 PB5PR PB4PR PB3PR PB2PR Pin state R Pin state R Pin state R Pin state R R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Reserved These bits are always read as undefined values and cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 956 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.4 Port C Port C is an input/output port with the two pins shown in figure 20.3. Port C PC1 (I/O) / A1 (output) PC0 (I/O) / A0 (output) Figure 20.3 Port C 20.4.1 Register Descriptions Table 20.5 lists the port C registers. Table 20.5 Register Configuration Register Name Port C data register L Port C port register L Abbreviation PCDRL PCPRL R/W R/W R Initial Value H'xxxx H'xxxx Address H'FFFE3902 H'FFFE391E Access Size 8, 16 8, 16 Rev. 3.00 Jun. 18, 2008 Page 957 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.4.2 Port C Data Register L (PCDRL) PCDRL is a 16-bit readable/writable register that stores port C data. Bits PC1DR and PC0DR correspond to pins PC1/A1 and PC0/A0, respectively. When a pin function is general output, if a value is written to PCDRL, that value is output directly from the pin, and if PCDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PCDRL is read, the pin state, not the register value, is returned directly. If a value is written to PCDRL, although that value is written into PCDRL, it does not affect the pin state. Table 20.6 summarizes PCDRL read/write operations. PCDRL is initialized to the value shown in table 20.5 by a power-on reset. PCDRL is not initialized by a manual reset or in sleep mode or software standby mode. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 PC1 DR 0 PC0 DR Initial value: R/W: R R R R R R R R R R R R R R 0 R/W 0 R/W Bit 15 to 2 Bit Name Initial Value R/W R Description Reserved These bits are always read as undefined values. The write value should always be 0. 1 0 PC1DR PC0DR 0 0 R/W R/W See table 20.6 Rev. 3.00 Jun. 18, 2008 Page 958 of 1160 REJ09B0191-0300 Section 20 I/O Ports Table 20.6 Port C Data Register L (PCDRL) Read/Write Operations * PCDRL bits 1 and 0 PCIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PCDRL value PCDRL value Write Can write to PCDRL, but it has no effect on pin state Can write to PCDRL, but it has no effect on pin state Value written is output from pin Can write to PCDRL, but it has no effect on pin state 20.4.3 Port C Port Register L (PCPRL) PCPRL is a 16-bit read-only register, in which bits PC1PR and PC0PR correspond to pins PC1/A1 and PC0/A0, respectively. PCPRL always returns the states of the pins regardless of the PFC setting. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 PC1 PR 0 PC0 PR Initial value: R/W: R R R R R R R R R R R R R R PC1 R PC0 R Bit 15 to 2 Bit Name Initial Value R/W R Description Reserved These bits are always read as undefined values and cannot be modified. 1 0 PC1PR PC0PR Pin state R Pin state R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 959 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.5 Port D Port D is an input/output port with the 24 pins shown in figure 20.4. Port D PD31 (I/O) / D31 (I/O) / ADTRG (input) / TIOC3AS (I/O) PD30 (I/O) / D30 (I/O) / IRQOUT (output) / REFOUT (output) / TIOC3CS (I/O) PD29 (I/O) / D29 (I/O) / CS3 (output) / TIOC3BS (I/O) PD28 (I/O) / D28 (I/O) / CS2 (output) / TIOC3DS (I/O) PD27 (I/O) / D27 (I/O) / DACK1 (output) / TIOC4AS (I/O) PD26 (I/O) / D26 (I/O) / DACK0 (output) / TIOC4BS (I/O) PD25 (I/O) / D25 (I/O) / DREQ1 (input) / TIOC4CS (I/O) PD24 (I/O) / D24 (I/O) / DREQ0 (input) / TIOC4DS (I/O) PD23 (I/O) / D23 (I/O) / IRQ7 (input) PD22 (I/O) / D22 (I/O) / IRQ6 (input) / TIC5US (input) PD21 (I/O) / D21 (I/O) / IRQ5 (input) / TIC5VS (input) PD20 (I/O) / D20 (I/O) / IRQ4 (input) / TIC5WS (input) PD19 (I/O) / D19 (I/O) / IRQ3 (input) / POE7 (input) PD18 (I/O) / D18 (I/O) / IRQ2 (input) / POE6 (input) PD17 (I/O) / D17 (I/O) / IRQ1 (input) / POE5 (input) PD16 (I/O) / D16 (I/O) / IRQ0 (input) / POE4 (input) PD15 (I/O) / D15 (I/O) / TIOC4DS (I/O) PD14 (I/O) / D14 (I/O) / TIOC4CS (I/O) PD13 (I/O) / D13 (I/O) / TIOC4BS (I/O) PD12 (I/O) / D12 (I/O) / TIOC4AS (I/O) PD11 (I/O) / D11 (I/O) / TIOC3DS (I/O) PD10 (I/O) / D10 (I/O) / TIOC3CS (I/O) PD9 (I/O) / D9 (I/O) / TIOC3BS (I/O) PD8 (I/O) / D8 (I/O) / TIOC3AS (I/O) Figure 20.4 Port D 20.5.1 Register Descriptions Table 20.7 lists the port D registers. Table 20.7 Register Configuration Register Name Port D data register H Port D data register L Port D port register H Port D port register L Abbreviation PDDRH PDDRL PDPRH PDPRL R/W R/W R/W R R Initial Value H'0000 H'00xx H'xxxx H'xxxx Address H'FFFE3980 H'FFFE3982 H'FFFE399C H'FFFE399E Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 Rev. 3.00 Jun. 18, 2008 Page 960 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.5.2 Port D Data Registers H, L (PDDRH, PDDRL) PDDRH and PDDRL are 16-bit readable/writable registers that store port D data. Bits PD31DR to PD8DR correspond to pins PD31/D31/ADTRG/TIOC3AS to PD8/D8/TIOC3AS, respectively. When a pin function is general output, if a value is written to PDDRH or PDDRL, that value is output directly from the pin, and if PDDRH or PDDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PDDRH or PDDRL is read, the pin state, not the register value, is returned directly. If a value is written to PDDRH or PDDRL, although that value is written into PDDRH or PDDRL, it does not affect the pin state. Table 20.8 summarizes PDDRH and PDDRL read/write operations. PDDRH and PDDRL are initialized to the respective values shown in table 20.7 by a power-on reset. PDDRH and PDDRL are not initialized by a manual reset or in sleep mode or software standby mode. Rev. 3.00 Jun. 18, 2008 Page 961 of 1160 REJ09B0191-0300 Section 20 I/O Ports (1) Port D Data Register H (PDDRH) Bit: 15 PD31 DR 14 PD30 DR 13 PD29 DR 12 PD28 DR 11 PD27 DR 10 PD26 DR 9 PD25 DR 8 PD24 DR 7 PD23 DR 6 PD22 DR 5 PD21 DR 4 PD20 DR 3 PD19 DR 2 PD18 DR 1 PD17 DR 0 PD16 DR Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PD31DR PD30DR PD29DR PD28DR PD27DR PD26DR PD25DR PD24DR PD23DR PD22DR PD21DR PD20DR PD19DR PD18DR PD17DR PD16DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 20.8 Rev. 3.00 Jun. 18, 2008 Page 962 of 1160 REJ09B0191-0300 Section 20 I/O Ports (2) Port D Data Register L (PDDRL) Bit: 15 PD15 DR 14 PD14 DR 13 PD13 DR 12 PD12 DR 11 PD11 DR 10 PD10 DR 9 PD9 DR 8 PD8 DR 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 to 0 Bit Name PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R Description See table 20.8 Reserved These bits are always read as undefined values. The write value should always be 0. Table 20.8 Port D Data Registers H and L (PDDRH and PDDRL) Read/Write Operations * PDDRH bits 15 to 0 and PDDRL bits 15 to 8 PDIORH, PDIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PDDRH or PDDRL value PDDRH or PDDRL value Write Can write to PDDRH or PDDRL, but it has no effect on pin state Can write to PDDRH or PDDRL, but it has no effect on pin state Value written is output from pin Can write to PDDRH or PDDRL, but it has no effect on pin state Rev. 3.00 Jun. 18, 2008 Page 963 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.5.3 Port D Port Registers H, L (PDPRH, PDPRL) PDPRH and PDPRL are 16-bit read-only registers, in which bits PD31PR to PD8PR correspond to pins PD31/D31/ADTRG/TIOC3AS to PD8/D8/TIOC3AS, respectively. PDPRH and PDPRL always return the states of the pins regardless of the PFC setting. (1) Port D Port Register H (PDPRH) Bit: 15 PD31 PR 14 PD30 PR 13 PD29 PR 12 PD28 PR 11 PD27 PR 10 PD26 PR 9 PD25 PR 8 PD24 PR 7 PD23 PR 6 PD22 PR 5 PD21 PR 4 PD20 PR 3 PD19 PR 2 PD18 PR 1 PD17 PR 0 PD16 PR Initial value: PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 R R R R R R R R R R R R R R R R R/W: Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PD31PR PD30PR PD29PR PD28PR PD27PR PD26PR PD25PR PD24PR PD23PR PD22PR PD21PR PD20PR PD19PR PD18PR PD17PR PD16PR Initial Value R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Rev. 3.00 Jun. 18, 2008 Page 964 of 1160 REJ09B0191-0300 Section 20 I/O Ports (2) Port D Port Register L (PDPRL) Bit: 15 PD15 PR 14 PD14 PR 13 PD13 PR 12 PD12 PR 11 PD11 PR 10 PD10 PR 9 PD9 PR 8 PD8 PR 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: PD15 PD14 PD13 PD12 PD11 PD10 R R R R R R R/W: PD9 R PD8 R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 to 0 Bit Name PD15PR PD14PR PD13PR PD12PR PD11PR PD10PR PD9PR PD8PR Initial Value R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R R Reserved These bits are always read as undefined values and cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 965 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.6 Port E Port E is an input/output port with the 17 pins shown in figure 20.5. Port E PE16 (I/O) / CS8 (output) PE15 (I/O) / TIOC4D (I/O)/ DACK1 (output) / IRQOUT (output) / REFOUT (output) / CKE (output) PE14 (I/O) / TIOC4C (I/O)/ DACK0 (output) / WE3 (output) / DQMUU (output) / ICIOWR (output)/ AH (output) PE13 (I/O) / TIOC4B (I/O) / MRES (input) PE12 (I/O) / TIOC4A (I/O) / TxD3 (output) PE11 (I/O) / TIOC3D (I/O) / RxD3 (input) / CTS3 (I/O) PE10 (I/O) / TIOC3C (I/O) / TxD2 (output) PE9 (I/O) / TIOC3B (I/O) / SCK3 (I/O) / RTS3 (I/O) PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O) PE7 (I/O) / TIOC2B (I/O) / RxD2 (input) / BS (output) / UBCTRG (output) PE6 (I/O) / TIOC2A (I/O) / SCK3 (I/O) / CS7 (output) PE5 (I/O) / TIOC1B (I/O) / TxD3 (output) / CS6 (output) / CE1B (output) PE4 (I/O) / TIOC1A (I/O) / RxD3 (input) / IOIS16 (input) PE3 (I/O) / TIOC0D (I/O) / TEND1 (output) PE2 (I/O) / TIOC0C (I/O) / DREQ1 (input) PE1 (I/O) / TIOC0B (I/O) / TEND0 (output) PE0 (I/O) / TIOC0A (I/O) / DREQ0 (input) Figure 20.5 Port E 20.6.1 Register Descriptions Table 20.9 lists the port E registers. Table 20.9 Register Configuration Register Name Port E data register H Port E data register L Port E port register H Port E port register L Abbreviation PEDRH PEDRL PEPRH PEPRL R/W R/W R/W R R Initial Value H'003E H'0000 H'003x H'xxxx Address H'FFFE3A00 H'FFFE3A02 H'FFFE3A1C H'FFFE3A1E Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 Rev. 3.00 Jun. 18, 2008 Page 966 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.6.2 Port E Data Registers H, L (PEDRH, PEDRL) PEDRH and PEDRL are 16-bit readable/writable registers that store port E data. Bits PE16DR to PE0DR correspond to pins PE16/CS8 to PE0/TIOC0A/DREQ0, respectively. When a pin function is general output, if a value is written to PEDRH or PEDRL, that value is output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PEDRH or PEDRL is read, the pin state, not the register value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is written into PEDRH or PEDRL, it does not affect the pin state. Table 20.10 summarizes PEDRH and PEDRL read/write operations. PEDRH and PEDRL are initialized to the respective values shown in table 20.9 by a power-on reset. PEDRH and PEDRL are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port E Data Register H (PEDRH) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PE16 DR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 1 R 1 R 1 R 1 R 0 R/W Bit 15 to 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 to 1 All 1 R Reserved These bits are always read as 1. The write value should always be 1. 0 PE16DR 0 R/W See table 20.10 Rev. 3.00 Jun. 18, 2008 Page 967 of 1160 REJ09B0191-0300 Section 20 I/O Ports (2) Port E Data Register L (PEDRL) Bit: 15 PE15 DR 14 PE14 DR 13 PE13 DR 12 PE12 DR 11 PE11 DR 10 PE10 DR 9 PE9 DR 8 PE8 DR 7 PE7 DR 6 PE6 DR 5 PE5 DR 4 PE4 DR 3 PE3 DR 2 PE2 DR 1 PE1 DR 0 PE0 DR Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 20.10 Rev. 3.00 Jun. 18, 2008 Page 968 of 1160 REJ09B0191-0300 Section 20 I/O Ports Table 20.10 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations * PEDRH bit 0 and PEDRL bits 15 to 0 PEIORH, PEIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PEDRH or PEDRL value PEDRH or PEDRL value Write Can write to PEDRH and PEDRL, but it has no effect on pin state Can write to PEDRH and PEDRL, but it has no effect on pin state Value written is output from pin Can write to PEDRH and PEDRL, but it has no effect on pin state 20.6.3 Port E Port Registers H, L (PEPRH, PEPRL) PEPRH and PEPRL are 16-bit read-only registers, in which bits PE16PR to PE0PR correspond to pins PE16/CS8 to PE0/TIOC0A/DREQ0, respectively. PEPRH and PEPRL always return the states of the pins regardless of the PFC setting. (1) Port E Port Register H (PEPRH) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PE16 PR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 1 R 1 R 1 R 1 R PE16 R Bit 15 to 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. 5 to 1 All 1 R Reserved These bits are always read as 1 and cannot be modified. 0 PE16PR Pin state R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Rev. 3.00 Jun. 18, 2008 Page 969 of 1160 REJ09B0191-0300 Section 20 I/O Ports (2) Port E Port Register L (PEPRL) Bit: 15 PE15 PR 14 PE14 PR 13 PE13 PR 12 PE12 PR 11 PE11 PR 10 PE10 PR 9 PE9 PR 8 PE8 PR 7 PE7 PR 6 PE6 PR 5 PE5 PR 4 PE4 PR 3 PE3 PR 2 PE2 PR 1 PE1 PR 0 PE0 PR Initial value: PE15 PE14 PE13 PE12 PE11 PE10 R R R R R R R/W: PE9 R PE8 R PE7 R PE6 R PE5 R PE4 R PE3 R PE2 R PE1 R PE0 R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15PR PE14PR PE13PR PE12PR PE11PR PE10PR PE9PR PE8PR PE7PR PE6PR PE5PR PE4PR PE3PR PE2PR PE1PR PE0PR Initial Value R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Rev. 3.00 Jun. 18, 2008 Page 970 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.7 Port F Port F is an input/output port with the eight pins shown in figure 20.6. Port F PF7 (input) / AN7 (input) / DA1 (output) PF6 (input) / AN6 (input) / DA0 (output) PF5 (input) / AN5 (input) PF4 (input) / AN4 (input) PF3 (input) / AN3 (input) PF2 (input) / AN2 (input) PF1 (input) / AN1 (input) PF0 (input) / AN0 (input) Figure 20.6 Port F 20.7.1 Register Descriptions Table 20.11 lists the port F register. Table 20.11 Register Configuration Register Name Port F data register Abbreviation PFDR R/W R Initial Value H'00xx Address H'FFFE3A82 Access Size 8, 16 Rev. 3.00 Jun. 18, 2008 Page 971 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.7.2 Port F Data Register (PFDR) PFDR is a 16-bit read-only register that stores port F data. Bits PF7DR to PF0DR correspond to pins PF7/AN7/DA1 to PF0/AN0, respectively. The general input function of pins PF7 to PF0 is enabled only when the A/D converter and D/A converter are halted. Even if a value is written to PFDR, that value is not written into PFDR, and it does not affect the pin state. If PFDR is read, the pin state, not the register value, is returned directly. However, PFDR should not be read when the A/D converter and D/A converter are operating. Table 20.12 summarizes PFDR read/write operations. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 PF7 DR 6 PF6 DR 5 PF5 DR 4 PF4 DR 3 PF3 DR 2 PF2 DR 1 PF1 DR 0 PF0 DR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R * R * R * R * R * R * R * R Note: * Depends on the external pin state. Bit 15 to 8 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R See table 20.12 Rev. 3.00 Jun. 18, 2008 Page 972 of 1160 REJ09B0191-0300 Section 20 I/O Ports Table 20.12 Port F Data Register (PFDR) Read/Write Operations * PFDR bits 7 to 0 Pin Function General input ANn input/DAn output Read Pin state Prohibited Write Ignored (no effect on pin state) Ignored (no effect on pin state) [Legend] n = 7 to 0. However, only pins DA0 and DA1 are available for DA output. Rev. 3.00 Jun. 18, 2008 Page 973 of 1160 REJ09B0191-0300 Section 20 I/O Ports 20.8 Usage Notes When the PFC selects the following pin functions, the pin state cannot be read by accessing data registers or port registers. * * * * * * * * * * * * * * A25 to A21, A1, and A0 (address bus) D31 to D8 (data bus) BS CS8, CS7, CS4 to CS1, CS5/CE1A, CS6/CE1B, CE2A, and CE2B RD/WR WE3/DQMUU/ICIOWR/AH, WE2/DQMUL/ICIORD, WE1/DQMLU/WE, and WE0/DQMLL RASU, RASL, CASU, and CASL CKE FRAME WAIT BREQ BACK IOIS16 MRES Rev. 3.00 Jun. 18, 2008 Page 974 of 1160 REJ09B0191-0300 Section 21 On-Chip RAM Section 21 On-Chip RAM This LSI has an on-chip RAM module which can be used to store instructions or data. On-chip RAM operation and write access to the RAM can be enabled or disabled through the RAM enable bits and RAM write enable bits. 21.1 Features * Pages The on-chip RAM is divided into four pages (pages 0 to 3). * Memory map The on-chip RAM is located in the address spaces shown in table 21.1. Table 21.1 On-Chip RAM Address Spaces Page Page 0 Page 1 Page 2 Page 3 Address H'FFF80000 to H'FFF87FFF H'FFF88000 to H'FFF8FFFF H'FFF90000 to H'FFF97FFF H'FFF98000 to H'FFF9FFFF * Ports Each page has two independent read and write ports and is connected to the internal bus (I bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F bus is connected only to the read ports.) The F bus and M bus are used for access by the CPU, and the I bus is used for access by the DMAC. * Priority When the same page is accessed from different buses simultaneously, the access is processed according to the priority. The priority is I bus > M bus > F bus. Rev. 3.00 Jun. 18, 2008 Page 975 of 1160 REJ09B0191-0300 Section 21 On-Chip RAM 21.2 21.2.1 Usage Notes Page Conflict When the same page is accessed from different buses simultaneously, a conflict on the page occurs. Although each access is completed correctly, this kind of conflict degrades the memory access speed. Therefore, it is advisable to provide software measures to prevent such conflicts as far as possible. For example, no conflict will arise if different pages are accessed by each bus. 21.2.2 RAME and RAMWE Bits Before disabling memory operation or write access through the RAME or RAMWE bit, be sure to read from any address and then write to the same address in each page; otherwise, the last written data in each page may not be actually written to the RAM. // For page 0 MOV.L MOV.L MOV.L #H'FFF80000,R0 @R0,R1 R1,@R0 // For page 1 MOV.L MOV.L MOV.L #H'FFF88000,R0 @R0,R1 R1,@R0 // For page 2 MOV.L MOV.L MOV.L #H'FFF90000,R0 @R0,R1 R1,@R0 // For page 3 MOV.L MOV.L MOV.L #H'FFF98000,R0 @R0,R1 R1,@R0 Figure 21.1 Examples of Read/Write before Disabling RAM Rev. 3.00 Jun. 18, 2008 Page 976 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes Section 22 Power-Down Modes In power-down modes, operation of some of the internal peripheral modules and of the CPU stops. This leads to reduced power consumption. These modes are canceled by a reset or interrupt. 22.1 22.1.1 Features Power-Down Modes This LSI has the following power-down modes and function: 1. Sleep mode 2. Software standby mode 3. Module standby function Table 22.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. Rev. 3.00 Jun. 18, 2008 Page 977 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes Table 22.1 States of Power-Down Modes State* On-Chip Power-Down Mode Sleep mode Transition Conditions Execute SLEEP instruction with STBY bit cleared to 0 in STBCR * * Power-on reset DMA address error Software standby mode Execute SLEEP instruction with STBY bit set to 1 in STBCR Halts Halts Held Halts (contents are held) Halts Selfrefreshing * * * * Module standby Set the MSTP bits in function STBCR2, STBCR3, and STBCR4 to 1 Runs Runs Held Specified module halts (contents are held) Specified module halts Autorefreshing * * NMI interrupt IRQ interrupt Manual reset Power-on reset Clear MSTP bit to 0 Power-on reset (only for H-UDI, UBC, and DMAC) CPG Runs CPU Halts CPU On-Chip Peripheral Modules Runs External Memory Autorefreshing Canceling Procedure * * Interrupt Manual reset Register Memory Held Runs Note: * The pin state is retained or set to high impedance. For details, see appendix A, Pin States. Rev. 3.00 Jun. 18, 2008 Page 978 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.2 Register Descriptions The following registers are used in power-down modes. Table 22.2 Register Configuration Register Name Standby control register Standby control register 2 Standby control register 3 Standby control register 4 System control register 1 System control register 2 Abbreviation STBCR STBCR2 STBCR3 STBCR4 SYSCR1 SYSCR2 R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'7E H'F4 H'FF H'FF Address H'FFFE0014 H'FFFE0018 H'FFFE0408 H'FFFE040C H'FFFE0402 H'FFFE0404 Access Size 8 8 8 8 8 8 Rev. 3.00 Jun. 18, 2008 Page 979 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.2.1 Standby Control Register (STBCR) STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This register is initialized to H'00 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 22.4, Usage Notes, when writing data to this register. Bit: 7 STBY 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 7 Bit Name STBY Initial Value 0 R/W R/W Description Software Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts chip into sleep mode. 1: Executing SLEEP instruction puts chip into software standby mode. 6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 980 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.2.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR2 is initialized to H'00 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 22.4, Usage Notes, when writing data to this register. Bit: 7 MSTP 10 6 5 4 - 3 - 2 - 1 - 0 - MSTP MSTP 9 8 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R Bit 7 Bit Name MSTP10 Initial Value 0 R/W R/W Description Module Stop 10 When the MSTP10 bit is set to 1, the supply of the clock to the H-UDI is halted. 0: H-UDI runs. 1: Clock supply to H-UDI halted. 6 MSTP9 0 R/W Module Stop 9 When the MSTP9 bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC runs. 1: Clock supply to UBC halted. 5 MSTP8 0 R/W Module Stop 8 When the MSTP8 bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC runs. 1: Clock supply to DMAC halted. 4 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 981 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.2.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR3 is initialized to H'7E by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 22.4, Usage Notes, when writing data to this register. Bit: 7 HIZ 6 5 4 3 2 MSTP 32 1 MSTP 31 0 - MSTP MSTP 36 35 MSTP MSTP 34 33 Initial value: R/W: 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R Bit 7 Bit Name HIZ Initial Value 0 R/W R/W Description Port High Impedance Selects whether the state of a specified pin is retained or the pin is placed in the high-impedance state in software standby mode. See appendix A, Pin States, to determine the pin to which this control is applied. Do not set this bit when the TME bit of WTSCR of the WDT is 1. When setting the output pin to the highimpedance state, set the HIZ bit with the TME bit being 0. 0: The pin state is held in software standby mode. 1: The pin state is set to the high-impedance state in software standby mode. 6 MSTP36 1 R/W Module Stop 36 When the MSTP36 bit is set to 1, the supply of the clock to the MTU2S is halted. 0: MTU2S runs. 1: Clock supply to MTU2S halted. 5 MSTP35 1 R/W Module Stop 35 When the MSTP35 bit is set to 1, the supply of the clock to the MTU2 is halted. 0: MTU2 runs. 1: Clock supply to MTU2 halted. Rev. 3.00 Jun. 18, 2008 Page 982 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes Bit 4 Bit Name MSTP34 Initial Value 1 R/W R/W Description Module Stop 34 When the MSTP34 bit is set to 1, the supply of the clock to the POE2 is halted. 0: POE2 runs. 1: Clock supply to POE2 halted. 3 MSTP33 1 R/W Module Stop 33 When the MSTP33 bit is set to 1, the supply of the clock to the IIC3 is halted. 0: IIC3 runs. 1: Clock supply to IIC3 halted. 2 MSTP32 1 R/W Module Stop 32 When the MSTP32 bit is set to 1, the supply of the clock to the ADC is halted. 0: ADC runs. 1: Clock supply to ADC halted. 1 MSTP31 1 R/W Module Stop 31 When the MSTP31 bit is set to 1, the supply of the clock to the DAC is halted. 0: DAC runs. 1: Clock supply to DAC halted. 0 0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 983 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.2.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR4 is initialized to H'F4 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 22.4, Usage Notes, when writing data to this register. Bit: 7 MSTP 47 6 5 4 MSTP 44 3 - 2 MSTP 42 1 - 0 - MSTP MSTP 46 45 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 0 R 1 R/W 0 R 0 R Bit 7 Bit Name MSTP47 Initial Value 1 R/W R/W Description Module Stop 47 When the MSTP47 bit is set to 1, the supply of the clock to the SCIF0 is halted. 0: SCIF0 runs. 1: Clock supply to SCIF0 halted. 6 MSTP46 1 R/W Module Stop 46 When the MSTP46 bit is set to 1, the supply of the clock to the SCIF1 is halted. 0: SCIF1 runs. 1: Clock supply to SCIF1 halted. 5 MSTP45 1 R/W Module Stop 45 When the MSTP45 bit is set to 1, the supply of the clock to the SCIF2 is halted. 0: SCIF2 runs. 1: Clock supply to SCIF2 halted. 4 MSTP44 1 R/W Module Stop 44 When the MSTP44 bit is set to 1, the supply of the clock to the SCIF3 is halted. 0: SCIF3 runs. 1: Clock supply to SCIF3 halted. Rev. 3.00 Jun. 18, 2008 Page 984 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes Bit 3 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 2 MSTP42 1 R/W Module Stop 42 When the MSTP42 bit is set to 1, the supply of the clock to the CMT is halted. 0: CMT runs. 1: Clock supply to CMT halted. 1, 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 3.00 Jun. 18, 2008 Page 985 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.2.5 System Control Register 1 (SYSCR1) SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM. SYSCR1 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. When an RAME bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAME bit is cleared to 0, the corresponding on-chip RAM area cannot be accessed. In this case, an undefined value is returned when reading data or fetching an instruction from the on-chip RAM, and writing to the on-chip RAM is ignored. The initial value of an RAME bit is 1. Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAME bit. If such an instruction is not executed, the data last written to each page may not be written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be located immediately after the instruction to write to SYSCR1. If an on-chip RAM access instruction is set, normal access is not guaranteed. Note: See section 22.4, Usage Notes, when writing data to this register. Bit: 7 - 6 - 5 - 4 - 3 2 1 0 RAME3 RAME2 RAME1 RAME0 Initial value: R/W: 1 R 1 R 1 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W Bit 7 to 4 Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 3 RAME3 1 R/W RAM Enable 3 (corresponding RAM addresses: Page 3 in on-chip RAM*) 0: On-chip RAM disabled 1: On-chip RAM enabled 2 RAME2 1 R/W RAM Enable 2 (corresponding RAM addresses: Page 2 in on-chip RAM*) 0: On-chip RAM disabled 1: On-chip RAM enabled Rev. 3.00 Jun. 18, 2008 Page 986 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes Bit 1 Bit Name RAME1 Initial Value 1 R/W R/W Description RAM Enable 1 (corresponding RAM addresses: Page 1 in on-chip RAM*) 0: On-chip RAM disabled 1: On-chip RAM enabled 0 RAME0 1 R/W RAM Enable 0 (corresponding RAM addresses: Page 0 in on-chip RAM*) 0: On-chip RAM disabled 1: On-chip RAM enabled Note: * For specific address for each page, see section 21, On-Chip RAM. Rev. 3.00 Jun. 18, 2008 Page 987 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.2.6 System Control Register 2 (SYSCR2) SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM. SYSCR2 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. When an RAMWE bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAMWE bit is cleared to 0, the corresponding on-chip RAM area cannot be written to. In this case, writing to the on-chip RAM is ignored. The initial value of an RAMWE bit is 1. Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAMWE bit. If such an instruction is not executed, the data last written to each page may not be written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be located immediately after the instruction to write to SYSCR2. If an on-chip RAM access instruction is set, normal access is not guaranteed. Note: See section 22.4, Usage Notes, when writing data to this register. Bit: 7 - 6 - 5 - 4 - 3 RAM WE3 2 RAM WE2 1 RAM WE1 0 RAM WE0 Initial value: R/W: 1 R 1 R 1 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W Bit 7 to 4 Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 3 RAMWE3 1 R/W RAM Write Enable 3 (corresponding RAM addresses: Page 3 in on-chip RAM*) 0: On-chip RAM write disabled 1: On-chip RAM write enabled 2 RAMWE2 1 R/W RAM Write Enable 2 (corresponding RAM addresses: Page 2 in on-chip RAM*) 0: On-chip RAM write disabled 1: On-chip RAM write enabled Rev. 3.00 Jun. 18, 2008 Page 988 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes Bit 1 Bit Name RAMWE1 Initial Value 1 R/W R/W Description RAM Write Enable 1 (corresponding RAM addresses: Page 1 in on-chip RAM*) 0: On-chip RAM write disabled 1: On-chip RAM write enabled 0 RAMWE0 1 R/W RAM Write Enable 0 (corresponding RAM addresses: Page 0 in on-chip RAM*) 0: On-chip RAM write disabled 1: On-chip RAM write enabled Note: * For specific address for each page, see section 21, On-Chip RAM. Rev. 3.00 Jun. 18, 2008 Page 989 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.3 22.3.1 (1) Operation Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules continue to run in sleep mode. Clock pulses continue to be output on the CKIO pin in clock mode 2. (2) Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), DMA address error, or reset (manual reset or power-on reset). * Canceling with an interrupt When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the priority level of the generated interrupt is equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU, or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt request is not accepted and sleep mode is not canceled. * Canceling with a DMA address error When a DMA address error occurs, sleep mode is canceled and DMA address error exception handling is executed. * Canceling with a reset Sleep mode is canceled by a power-on reset or a manual reset. 22.3.2 (1) Software Standby Mode Transition to Software Standby Mode The LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also halts in clock mode 2. Rev. 3.00 Jun. 18, 2008 Page 990 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes The contents of the CPU remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. Regarding the states of on-chip peripheral module registers in software standby mode, see section 24.3, Register States in Each Operating Mode. The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely reflected in the SLEEP instruction. The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. 2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After setting the STBY bit in STBCR to 1, read STBCR. Then, execute a SLEEP instruction. (2) Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (manual reset or poweron reset). The CKIO pin starts outputting the clock in clock mode 2. * Canceling with an interrupt When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC)) is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation settling counter (WDT) used to count the oscillation settling time. After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer control/status register (WTCSR) of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in the case of IRQ) starts. However, if the priority level of IRQ interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, the interrupt request is not accepted and thus the software standby mode is not released. When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation settling time. Rev. 3.00 Jun. 18, 2008 Page 991 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes The clock output phase of the CKIO pin may be unstable immediately after detecting an interrupt and until software standby mode is canceled. When software standby mode is canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from software standby mode (when the clock is initiated after the oscillation settling). When software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation settling) (This is the same with the IRQ pin.) * Canceling with a reset When the RES pin is driven low, software standby mode is released and this LSI enters the power-on reset state. And if the RES pin is driven high after that, the power-on reset exception handling starts. When the MRES pin is driven low followed by being driven high, software standby mode is released the manual reset exception handling starts on the condition that the frequency ratio of the internal clock (I) to the peripheral clock (P) is 6:1, 8:1, or 12:1. If the ratio is either 1:1, 2:1, 3:1, or 4:1, the manual reset exception handling is not generated and the instruction next to the SLEEP instruction is executed. To generate the manual reset exception handling, set the frequency ratio of (I) to (P) to 6:1, 8:1, or 12:1 before transferring to software standby mode. Keep the RES or MRES pin low until the clock oscillation settles. (3) Note on Release from Software Standby Mode Release from software standby mode is triggered by interrupts (NMI and IRQ) or resets (manual reset and power-on reset). If, however, a SLEEP instruction and an interrupt other than NMI and IRQ are generated at the same time, cancellation of software standby mode may occur due to acceptance of the interrupt. When initiating a transition to software standby mode, make settings so that interrupts are not generated before execution of the SLEEP instruction. Rev. 3.00 Jun. 18, 2008 Page 992 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.3.3 Software Standby Mode Application Example This example describes a transition to software standby mode on the falling edge of the NMI signal, and cancellation on the rising edge of the NMI signal. The timing is shown in figure 22.1. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) in ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by the NMI exception service routine, the STBY bit in STBCR is set to 1, and a SLEEP instruction is executed, software standby mode is entered. Thereafter, software standby mode is canceled when the NMI pin is changed from low to high level. Oscillator CK NMI pin NMIE bit STBY bit LSI state Program execution NMI exception handling Exception service routine Software standby mode Oscillation settling time NMI exception handling Figure 22.1 NMI Timing in Software Standby Mode (Application Example) Rev. 3.00 Jun. 18, 2008 Page 993 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.3.4 (1) Module Standby Function Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode and sleep mode. Disable a module before placing it in the module standby mode. In addition, do not access the module's registers while it is in the module standby state. The register states are the same as those in software standby mode. For details, see section 24.3, Register States in Each Operating Mode. However, the states of the CMT and DAC registers are exceptional. In the CMT, all registers are initialized in software standby mode, but retain their previous values in module standby mode. In the DAC, all registers retain their previous values in software standby mode, but are initialized in module standby mode. (2) Canceling Module Standby Function The module standby function can be canceled by clearing the MSTP bits to 0, or by a power-on reset (only possible for H-UDI, UBC, and DMAC). When taking a module out of the module standby state by clearing the corresponding MSTP bit to 0, read the MSTP bit to confirm that it has been cleared to 0. Rev. 3.00 Jun. 18, 2008 Page 994 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes 22.4 22.4.1 Usage Notes Note on Writing to Registers When writing data to registers related to power-down modes, note the following suggestion. In a case where the CPU writes data to the registers related to power-down modes, if the CPU once starts executing the write instruction, the CPU keeps on executing the succeeding instructions without waiting for the completion of writing data to the registers. If reflecting a change of writing data to registers becomes necessary while the CPU is performing the succeeding instructions, execute a dummy read for the same register between the write instruction to the register and the succeeding instructions. Rev. 3.00 Jun. 18, 2008 Page 995 of 1160 REJ09B0191-0300 Section 22 Power-Down Modes Rev. 3.00 Jun. 18, 2008 Page 996 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) Section 23 High-Performance User Debugging Interface (H-UDI) This LSI incorporates a high-performance user debugging interface (H-UDI) for emulator support. 23.1 Features The high-performance user debugging interface (H-UDI) has reset and interrupt request functions. The H-UDI in this LSI is used for emulator connection. Refer to the emulator manual for the method of connecting the emulator. Figure 23.1 shows a block diagram of the H-UDI. TDI SDBPR Shift register SDIR TDO MUX TCK TMS TRST TAP control circuit Decoder Local bus [Legend] SDBPR: SDIR: Bypass register Instruction register Figure 23.1 Block Diagram of H-UDI Rev. 3.00 Jun. 18, 2008 Page 997 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) 23.2 Input/Output Pins Table 23.1 Pin Configuration Pin Name Symbol I/O Input Function Data is serially supplied to the H-UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. For the protocol, see figure 23.2. Input is accepted asynchronously with respect to TCK, and when low, the H-UDI is reset. TRST must be low for a constant period when power is turned on regardless of using the H-UDI function. See section 23.4.2, Reset Configuration, for more information. Data transfer to the H-UDI is executed by changing this signal in synchronization with TCK. Data read from the H-UDI is executed by reading this pin in synchronization with TCK. The initial value of the data output timing is the TCK falling edge. This can be changed to the TCK rising edge by inputting the TDO change timing switch command to SDIR. See section 23.4.3, TDO Output Timing, for more information. If a low level is input at the ASEMD pin while the RES pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered. In ASE mode, dedicated emulator function can be used. The input level at the ASEMD pin should be held for at least one cycle after RES negation. H-UDI serial data input/output TCK clock pin Mode select input pin TMS Input H-UDI reset input pin TRST Input H-UDI serial data input pin TDI Input H-UDI serial data output pin TDO Output ASE mode select pin ASEMD* Input Note: * When the emulator is not in use, fix this pin to the high level. Rev. 3.00 Jun. 18, 2008 Page 998 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) 23.3 Register Descriptions The H-UDI has the following registers. Table 23.2 Register Configuration Register Name Bypass register Instruction register Abbreviation SDBPR SDIR R/W R Initial Value H'EFFD Address H'FFFE2000 Access Size 16 23.3.1 Bypass Register (SDBPR) SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined. 23.3.2 Instruction Register (SDIR) SDIR is a 16-bit read-only register. It is initialized by TRST assertion or in the TAP test-logicreset state, and can be written to by the H-UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in this register. The initial value is H'EFFD. Bit: 15 14 13 12 11 10 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - TI[7:0] Initial value: R/W: 1* R 1* R 1* R 0* R 1* R 1* R 1* R 1* R 1 R 1 R 1 R 1 R 1 R 1 R 0 R 1 R Note: * The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value. Rev. 3.00 Jun. 18, 2008 Page 999 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) Bit 15 to 8 Bit Name TI[7:0] Initial Value 11101111* R/W R Description Test Instruction The H-UDI instruction is transferred to SDIR by a serial input from TDI. For commands, see table 23.3. 7 to 2 1 0 All 1 0 1 R R R Reserved These bits are always read as 1. Reserved This bit is always read as 0. Reserved This bit is always read as 1. Table 23.3 H-UDI Commands Bits 15 to 8 TI7 0 0 1 1 1 TI6 1 1 0 0 1 TI5 1 1 0 1 1 TI4 0 1 1 1 1 TI3 -- -- 1 -- -- TI2 -- -- 1 -- -- TI1 -- -- 0 -- -- TI0 -- -- 0 -- -- Description H-UDI reset negate H-UDI reset assert TDO change timing switch H-UDI interrupt BYPASS mode Reserved Other than above Rev. 3.00 Jun. 18, 2008 Page 1000 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) 23.4 23.4.1 Operation TAP Controller Figure 23.2 shows the internal states of the TAP controller. 1 Test -logic-reset 0 1 1 1 Select-IR 0 0 Run-test/idle Select-DR 0 1 1 Capture-DR 0 Capture-IR 0 Shift-DR 1 0 Shift-IR 1 0 1 1 Exit1-IR 0 Exit1-DR 0 Pause-DR 1 0 0 0 Pause-IR 1 Exit2-IR 1 0 Exit2-DR 1 Update-DR 1 0 Update-IR 1 0 Figure 23.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. For details on change timing of the TDO value, see section 23.4.3, TDO Output Timing. The TDO is at high impedance, except with shift-DR and shift-IR states. During the change to TRST = 0, there is a transition to test-logic-reset asynchronously with TCK. Rev. 3.00 Jun. 18, 2008 Page 1001 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) 23.4.2 Reset Configuration Table 23.4 Reset Configuration ASEMD*1 H RES L TRST L H H L H L L L H H L H Chip State Power-on reset and H-UDI reset Power-on reset H-UDI reset only Normal operation Reset hold*2 Power-on reset H-UDI reset only Normal operation Notes: 1. Performs normal mode and ASE mode settings ASEMD = H, normal mode ASEMD = L, ASE mode 2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RES pin is negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI operation is enabled, but the CPU does not start up. The reset hold state is cancelled by a power-on reset. 23.4.3 TDO Output Timing The initial value of the TDO change timing is to perform data output from the TDO pin on the TCK falling edge. However, setting a TDO change timing switch command in SDIR via the HUDI pin and passing the Update-IR state synchronizes the TDO change timing to the TCK rising edge. Hereafter, to synchronize the change timing of TD0 to the falling edge of TCK, the TRST pin must be simultaneously asserted with the power-on reset. In a case of power-on reset by the RES pin, the sync reset is still in operation for a certain period in the LSI even after the RES pin is negated. Thus, if the TRST pin is asserted immediately after the negate of the RES pin, the TD0 change timing switch command is cleared, resulting the TD0 change timing synchronized with the falling edge of TCK. To prevent this, make sure to put a period of 20 times of tcyc or longer between the signal change timing of the RES and TRST pins. Rev. 3.00 Jun. 18, 2008 Page 1002 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) TCK TDO (after execution of TDO change timing switch command) tTDOD TDO (initial value) tTDOD Figure 23.3 H-UDI Data Transfer Timing 23.4.4 H-UDI Reset An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by setting an H-UDI reset negate command. The required time between the H-UDI reset assert command and H-UDI reset negate command is the same as time for keeping the RES pin low to apply a power-on reset. SDIR H-UDI reset assert H-UDI reset negate Chip internal reset CPU state Fetch the initial values of PC and SR from the exception handling vector table Figure 23.4 H-UDI Reset 23.4.5 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in fetching the exception service routine start address from the exception handling vector table, jumping to that address, and starting program execution from that address. This interrupt request has a fixed priority level of 15. H-UDI interrupts are accepted in sleep mode, but not in software standby mode. Rev. 3.00 Jun. 18, 2008 Page 1003 of 1160 REJ09B0191-0300 Section 23 High-Performance User Debugging Interface (H-UDI) 23.5 Usage Notes 1. An H-UDI command, once set, will not be modified as long as another command is not set again from the H-UDI. If the same command is to be set continuously, the command must be set after a command (BYPASS mode, etc.) that does not affect chip operations is once set. 2. In software standby mode and H-UDI module standby state, all of the functions in the H-UDI cannot be used. To retain the TAP status before and after standby mode, keep TCK high before entering standby mode. 3. Regardless of whether the H-UDI is used, make sure to keep the TRST pin low at power-on to initialize the H-UDI. 4. When the TDO change timing switch command is set and the TRST pin is asserted immediately after and the RES pin is negated, the TDO change timing switch command may be cleared. To prevent this, make sure to put 20 tcyc or more between the signal change timing of the RES and TRST pins when the TDO change timing switch command is set. For details, see section 23.4.3, TDO Output Timing. 5. When starting the TAP controller after the negation of the TRST pin, make sure to allow 200 ns or more after the negation. Rev. 3.00 Jun. 18, 2008 Page 1004 of 1160 REJ09B0191-0300 Section 24 List of Registers Section 24 List of Registers This section gives information on the on-chip I/O registers of this LSI in the following structures. 1. * * * Register Addresses (by functional module, in order of the corresponding section numbers) Registers are described by functional module, in order of the corresponding section numbers. Access to reserved addresses which are not described in this register address list is prohibited. When registers consist of 16 or 32 bits, the addresses of the MSBs are given when big-endian mode is selected. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * Reserved bits are indicated by -- in the bit name. * No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * For the initial state of each bit, refer to the description of the register in the corresponding section. * The register states described are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. 4. Notes when Writing to the On-Chip Peripheral Modules * To access an on-chip module register, two or more peripheral module clock (Pf) cycles are required. Care must be taken in system design. When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without waiting for the completion of writing to registers. For example, a case is described here in which the system is transferring to the software standby mode for power savings. To make this transition, the SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy read of registers to which write instruction is given and then perform the succeeding instructions. Rev. 3.00 Jun. 18, 2008 Page 1005 of 1160 REJ09B0191-0300 Section 24 List of Registers 24.1 Module Name CPG Register Addresses (by functional module, in order of the corresponding section numbers) Register Name Frequency control register MTU clock frequency control register INTC Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 IRQ interrupt request register PINT interrupt enable register PINT interrupt request register Bank control register Bank number register Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 05 Interrupt priority register 06 Interrupt priority register 07 Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt priority register 14 UBC Break address register_0 Break address mask register_0 Break bus cycle register_0 Break data register_0 Break data mask register_0 Break address register_1 Abbreviation FRQCR MCLKCR ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR IPR01 IPR02 IPR05 IPR06 IPR07 IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 BAR_0 BAMR_0 BBR_0 BDR_0 BDMR_0 BAR_1 Number of Bits Address 16 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 32 32 16 32 32 32 H'FFFE0010 H'FFFE0410 H'FFFE0800 H'FFFE0802 H'FFFE0804 H'FFFE0806 H'FFFE0808 H'FFFE080A H'FFFE080C H'FFFE080E H'FFFE0818 H'FFFE081A H'FFFE0820 H'FFFE0C00 H'FFFE0C02 H'FFFE0C04 H'FFFE0C06 H'FFFE0C08 H'FFFE0C0A H'FFFE0C0C H'FFFE0C0E H'FFFE0C10 H'FFFC0400 H'FFFC0404 H'FFFC04A0 H'FFFC0408 H'FFFC040C H'FFFC0410 Access Size 16 8 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 32 32 16 32 32 32 Rev. 3.00 Jun. 18, 2008 Page 1006 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name UBC Register Name Break address mask register_1 Break bus cycle register_1 Break data register_1 Break data mask register_1 Break control register Abbreviation BAMR_1 BBR_1 BDR_1 BDMR_1 BRCR CCR1 CCR2 CMNCR CS0BCR CS1BCR CS2BCR CS3BCR CS4BCR CS5BCR CS6BCR CS7BCR CS8BCR CS0WCR CS1WCR CS2WCR CS3WCR CS4WCR CS5WCR CS6WCR CS7WCR CS8WCR SDCR RTCSR RTCNT RTCOR Number of Bits Address 32 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 H'FFFC0414 H'FFFC04B0 H'FFFC0418 H'FFFC041C H'FFFC04C0 H'FFFC1000 H'FFFC1004 H'FFFC0000 H'FFFC0004 H'FFFC0008 H'FFFC000C H'FFFC0010 H'FFFC0014 H'FFFC0018 H'FFFC001C H'FFFC0020 H'FFFC0024 H'FFFC0028 H'FFFC002C H'FFFC0030 H'FFFC0034 H'FFFC0038 H'FFFC003C H'FFFC0040 H'FFFC0044 H'FFFC0048 H'FFFC004C H'FFFC0050 H'FFFC0054 H'FFFC0058 Access Size 32 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Cache Cache control register 1 Cache control register 2 BSC Common control register CS0 space bus control register CS1 space bus control register CS2 space bus control register CS3 space bus control register CS4 space bus control register CS5 space bus control register CS6 space bus control register CS7 space bus control register CS8 space bus control register CS0 space wait control register CS1 space wait control register CS2 space wait control register CS3 space wait control register CS4 space wait control register CS5 space wait control register CS6 space wait control register CS7 space wait control register CS8 space wait control register SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register Rev. 3.00 Jun. 18, 2008 Page 1007 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name BSC Register Name AC characteristics switching register AC characteristics switching key register Abbreviation ACSWR ACKYER SAR_0 DAR_0 DMATCR_0 CHCR_0 RSAR_0 RDAR_0 RDMATCR_0 SAR_1 DAR_1 DMATCR_1 CHCR_1 RSAR_1 RDAR_1 RDMATCR_1 SAR_2 DAR_2 DMATCR_2 CHCR_2 RSAR_2 RDAR_2 RDMATCR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 RSAR_3 Number of Bits Address 32 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 H'FFFC180C H'FFFC1BFC H'FFFE1000 H'FFFE1004 H'FFFE1008 H'FFFE100C H'FFFE1100 H'FFFE1104 H'FFFE1108 H'FFFE1010 H'FFFE1014 H'FFFE1018 H'FFFE101C H'FFFE1110 H'FFFE1114 H'FFFE1118 H'FFFE1020 H'FFFE1024 H'FFFE1028 H'FFFE102C H'FFFE1120 H'FFFE1124 H'FFFE1128 H'FFFE1030 H'FFFE1034 H'FFFE1038 H'FFFE103C H'FFFE1130 Access Size 32 8 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 DMAC DMA source address register_0 DMA destination address register_0 DMA transfer count register_0 DMA channel control register_0 DMA reload source address register_0 DMA reload destination address register_0 DMA reload transfer count register_0 DMA source address register_1 DMA destination address register_1 DMA transfer count register_1 DMA channel control register_1 DMA reload source address register_1 DMA reload destination address register_1 DMA reload transfer count register_1 DMA source address register_2 DMA destination address register_2 DMA transfer count register_2 DMA channel control register_2 DMA reload source address register_2 DMA reload destination address register_2 DMA reload transfer count register_2 DMA source address register_3 DMA destination address register_3 DMA transfer count register_3 DMA channel control register_3 DMA reload source address register_3 Rev. 3.00 Jun. 18, 2008 Page 1008 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Name DMA reload destination address register_3 DMA reload transfer count register_3 DMA source address register_4 DMA destination address register_4 DMA transfer count register_4 DMA channel control register_4 DMA reload source address register_4 DMA reload destination address register_4 DMA reload transfer count register_4 DMA source address register_5 DMA destination address register_5 DMA transfer count register_5 DMA channel control register_5 DMA reload source address register_5 DMA reload destination address register_5 DMA reload transfer count register_5 DMA source address register_6 DMA destination address register_6 DMA transfer count register_6 DMA channel control register_6 DMA reload source address register_6 DMA reload destination address register_6 DMA reload transfer count register_6 DMA source address register_7 DMA destination address register_7 DMA transfer count register_7 DMA channel control register_7 DMA reload source address register_7 Abbreviation RDAR_3 RDMATCR_3 SAR_4 DAR_4 DMATCR_4 CHCR_4 RSAR_4 RDAR_4 RDMATCR_4 SAR_5 DAR_5 DMATCR_5 CHCR_5 RSAR_5 RDAR_5 RDMATCR_5 SAR_6 DAR_6 DMATCR_6 CHCR_6 RSAR_6 RDAR_6 RDMATCR_6 SAR_7 DAR_7 DMATCR_7 CHCR_7 RSAR_7 Number of Bits Address 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 H'FFFE1134 H'FFFE1138 H'FFFE1040 H'FFFE1044 H'FFFE1048 H'FFFE104C H'FFFE1140 H'FFFE1144 H'FFFE1148 H'FFFE1050 H'FFFE1054 H'FFFE1058 H'FFFE105C H'FFFE1150 H'FFFE1154 H'FFFE1158 H'FFFE1060 H'FFFE1064 H'FFFE1068 H'FFFE106C H'FFFE1160 H'FFFE1164 H'FFFE1168 H'FFFE1070 H'FFFE1074 H'FFFE1078 H'FFFE107C H'FFFE1170 Access Size 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 Rev. 3.00 Jun. 18, 2008 Page 1009 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Name DMA reload destination address register_7 DMA reload transfer count register_7 DMA operation register DMA extension resource selector 0 DMA extension resource selector 1 DMA extension resource selector 2 DMA extension resource selector 3 Abbreviation RDAR_7 RDMATCR_7 DMAOR DMARS0 DMARS1 DMARS2 DMARS3 TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 Number of Bits Address 32 32 16 16 16 16 16 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 16 H'FFFE1174 H'FFFE1178 H'FFFE1200 H'FFFE1300 H'FFFE1304 H'FFFE1308 H'FFFE130C H'FFFE4300 H'FFFE4301 H'FFFE4302 H'FFFE4303 H'FFFE4304 H'FFFE4305 H'FFFE4306 H'FFFE4308 H'FFFE430A H'FFFE430C H'FFFE430E H'FFFE4320 H'FFFE4322 H'FFFE4324 H'FFFE4325 H'FFFE4326 H'FFFE4380 H'FFFE4381 H'FFFE4382 H'FFFE4384 H'FFFE4385 H'FFFE4386 Access Size 16, 32 16, 32 8, 16 16 16 16 16 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 16 MTU2 Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer general register E_0 Timer general register F_0 Timer interrupt enable register2_0 Timer status register2_0 Timer buffer operation transfer mode register_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Rev. 3.00 Jun. 18, 2008 Page 1010 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Name Timer general register A_1 Timer general register B_1 Timer input capture control register Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Timer buffer operation transfer mode register_3 Timer control register_4 Timer mode register_4 Timer I/O control register H_4 Timer I/O control register L_4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Abbreviation TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TBTM_3 TCR_4 TMDR_4 TIORH_4 TIORL_4 TIER_4 TSR_4 TCNT_4 Number of Bits Address 16 16 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 16 H'FFFE4388 H'FFFE438A H'FFFE4390 H'FFFE4000 H'FFFE4001 H'FFFE4002 H'FFFE4004 H'FFFE4005 H'FFFE4006 H'FFFE4008 H'FFFE400A H'FFFE4200 H'FFFE4202 H'FFFE4204 H'FFFE4205 H'FFFE4208 H'FFFE422C H'FFFE4210 H'FFFE4218 H'FFFE421A H'FFFE4224 H'FFFE4226 H'FFFE4238 H'FFFE4201 H'FFFE4203 H'FFFE4206 H'FFFE4207 H'FFFE4209 H'FFFE422D H'FFFE4212 Access Size 16 16 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 16 Rev. 3.00 Jun. 18, 2008 Page 1011 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Name Timer general register A_4 Timer general register B_4 Timer general register C_4 Timer general register D_4 Timer buffer operation transfer mode register_4 Timer A/D converter start request control register Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4 Timer A/D converter start request cycle set buffer register A_4 Timer A/D converter start request cycle set buffer register B_4 Timer control register U_5 Timer control register V_5 Timer control register W_5 Timer I/O control register U_5 Timer I/O control register V_5 Timer I/O control register W_5 Timer interrupt enable register_5 Timer status register_5 Timer start register_5 Timer counter U_5 Timer counter V_5 Timer counter W_5 Timer general register U_5 Timer general register V_5 Timer general register W_5 Timer compare match clear register Timer start register Abbreviation TGRA_4 TGRB_4 TGRC_4 TGRD_4 TBTM_4 TADCR TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 TCRU_5 TCRV_5 TCRW_5 TIORU_5 TIORV_5 TIORW_5 TIER_5 TSR_5 TSTR_5 TCNTU_5 TCNTV_5 TCNTW_5 TGRU_5 TGRV_5 TGRW_5 TCNTCMPCLR TSTR Number of Bits Address 16 16 16 16 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 8 8 H'FFFE421C H'FFFE421E H'FFFE4228 H'FFFE422A H'FFFE4239 H'FFFE4240 H'FFFE4244 H'FFFE4246 H'FFFE4248 H'FFFE424A H'FFFE4084 H'FFFE4094 H'FFFE40A4 H'FFFE4086 H'FFFE4096 H'FFFE40A6 H'FFFE40B2 H'FFFE40B0 H'FFFE40B4 H'FFFE4080 H'FFFE4090 H'FFFE40A0 H'FFFE4082 H'FFFE4092 H'FFFE40A2 H'FFFE40B6 H'FFFE4280 Access Size 16 16 16 16 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 8 8 Rev. 3.00 Jun. 18, 2008 Page 1012 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Name Timer synchronous register Timer counter synchronous start register Timer read/write enable register Timer output master enable register Timer output control register 1 Timer output control register 2 Timer gate control register Timer cycle control register Timer dead time data register Timer subcounter Timer cycle buffer register Timer interrupt skipping set register Timer interrupt skipping counter Timer buffer transfer set register Timer dead time enable register Timer synchronous clear register Timer waveform control register Timer output level buffer register Abbreviation TSYR TCSYSTR TRWER TOER TOCR1 TOCR2 TGCR TCDR TDDR TCNTS TCBR TITCR TITCNT TBTER TDER TSYCR TWCR TOLBR TCR_3S TMDR_3S TIORH_3S TIORL_3S TIER_3S TSR_3S TCNT_3S TGRA_3S TGRB_3S TGRC_3S TGRD_3S TBTM_3S Number of Bits Address 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 H'FFFE4281 H'FFFE4282 H'FFFE4284 H'FFFE420A H'FFFE420E H'FFFE420F H'FFFE420D H'FFFE4214 H'FFFE4216 H'FFFE4220 H'FFFE4222 H'FFFE4230 H'FFFE4231 H'FFFE4232 H'FFFE4234 H'FFFE4250 H'FFFE4260 H'FFFE4236 H'FFFE4A00 H'FFFE4A02 H'FFFE4A04 H'FFFE4A05 H'FFFE4A08 H'FFFE4A2C H'FFFE4A10 H'FFFE4A18 H'FFFE4A1A H'FFFE4A24 H'FFFE4A26 H'FFFE4A38 Access Size 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 MTU2S Timer control register_3S Timer mode register_3S Timer I/O control register H_3S Timer I/O control register L_3S Timer interrupt enable register_3S Timer status register_3S Timer counter_3S Timer general register A_3S Timer general register B_3S Timer general register C_3S Timer general register D_3S Timer buffer operation transfer mode register_3S Rev. 3.00 Jun. 18, 2008 Page 1013 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2S Register Name Timer control register_4S Timer mode register_4S Timer I/O control register H_4S Timer I/O control register L_4S Timer interrupt enable register_4S Timer status register_4S Timer counter_4S Timer general register A_4S Timer general register B_4S Timer general register C_4S Timer general register D_4S Timer buffer operation transfer mode register_4S Timer A/D converter start request control register S Timer A/D converter start request cycle set register A_4S Timer A/D converter start request cycle set register B_4S Timer A/D converter start request cycle set buffer register A_4S Timer A/D converter start request cycle set buffer register B_4S Timer control register U_5S Timer control register V_5S Timer control register W_5S Timer I/O control register U_5S Timer I/O control register V_5S Timer I/O control register W_5S Timer interrupt enable register_5S Timer status register_5S Timer start register_5S Timer counter U_5S Abbreviation TCR_4S TMDR_4S TIORH_4S TIORL_4S TIER_4S TSR_4S TCNT_4S TGRA_4S TGRB_4S TGRC_4S TGRD_4S TBTM_4S TADCRS TADCORA_4S TADCORB_4S Number of Bits Address 8 8 8 8 8 8 16 16 16 16 16 8 16 16 16 H'FFFE4A01 H'FFFE4A03 H'FFFE4A06 H'FFFE4A07 H'FFFE4A09 H'FFFE4A2D H'FFFE4A12 H'FFFE4A1C H'FFFE4A1E H'FFFE4A28 H'FFFE4A2A H'FFFE4A39 H'FFFE4A40 H'FFFE4A44 H'FFFE4A46 H'FFFE4A48 H'FFFE4A4A H'FFFE4884 H'FFFE4894 H'FFFE48A4 H'FFFE4886 H'FFFE4896 H'FFFE48A6 H'FFFE48B2 H'FFFE48B0 H'FFFE48B4 H'FFFE4880 Access Size 8 8 8 8 8 8 16 16 16 16 16 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 16 TADCOBRA_4S 16 TADCOBRB_4S 16 TCRU_5S TCRV_5S TCRW_5S TIORU_5S TIORV_5S TIORW_5S TIER_5S TSR_5S TSTR_5S TCNTU_5S 8 8 8 8 8 8 8 8 8 16 Rev. 3.00 Jun. 18, 2008 Page 1014 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2S Register Name Timer counter V_5S Timer counter W_5S Timer general register U_5S Timer general register V_5S Timer general register W_5S Timer compare match clear register S Timer start register S Timer synchronous register S Timer counter synchronous start register S Timer read/write enable register S Timer output control register 1S Timer output control register 2S Timer gate control register S Timer cycle control register S Timer dead time data register S Timer subcounter S Timer cycle buffer register S Timer interrupt skipping set register S Timer interrupt skipping counter S Timer buffer transfer set register S Timer dead time enable register S Timer synchronous clear register S Timer waveform control register S Timer output level buffer register S Abbreviation TCNTV_5S TCNTW_5S TGRU_5S TGRV_5S TGRW_5S Number of Bits Address 16 16 16 16 16 H'FFFE4890 H'FFFE48A0 H'FFFE4882 H'FFFE4892 H'FFFE48A2 H'FFFE48B6 H'FFFE4A80 H'FFFE4A81 H'FFFE4A84 H'FFFE4A0A H'FFFE4A0E H'FFFE4A0F H'FFFE4A0D H'FFFE4A14 H'FFFE4A16 H'FFFE4A20 H'FFFE4A22 H'FFFE4A30 H'FFFE4A31 H'FFFE4A32 H'FFFE4A34 H'FFFE4A50 H'FFFE4A60 H'FFFE4A36 H'FFFE5000 H'FFFE5002 H'FFFE5004 H'FFFE5006 H'FFFE5008 H'FFFE500A Access Size 16 16 16 16 16 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 16 16 16 16 16 8 TCNTCMPCLRS 8 TSTRS TSYRS TRWERS TOERS TOCR1S TOCR2S TGCRS TCDRS TDDRS TCNTSS TCBRS TITCRS TITCNTS TBTERS TDERS TSYCRS TWCRS TOLBRS ICSR1 OCSR1 ICSR2 OCSR2 ICSR3 SPOER 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 16 16 16 16 16 8 POE2 Input level control/status register 1 Output level control/status register 1 Input level control/status register 2 Output level control/status register 2 Input level control/status register 3 Software port output enable register Rev. 3.00 Jun. 18, 2008 Page 1015 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name POE2 Register Name Port output enable control register 1 Port output enable control register 2 Abbreviation POECR1 POECR2 CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 WTCSR WTCNT WRCSR SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 Number of Bits Address 8 16 16 16 16 16 16 16 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 H'FFFE500B H'FFFE500C H'FFFEC000 H'FFFEC002 H'FFFEC004 H'FFFEC006 H'FFFEC008 H'FFFEC00A H'FFFEC00C H'FFFE0000 H'FFFE0002 H'FFFE0004 H'FFFE8000 H'FFFE8004 H'FFFE8008 H'FFFE800C H'FFFE8010 H'FFFE8014 H'FFFE8018 H'FFFE801C H'FFFE8020 H'FFFE8024 H'FFFE8800 H'FFFE8804 H'FFFE8808 H'FFFE880C H'FFFE8810 H'FFFE8814 H'FFFE8818 H'FFFE881C Access Size 8 16 16 16 8, 16 8, 16 16 8, 16 8, 16 16* 16* 16* 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 CMT Compare match timer start register Compare match timer control/status register_0 Compare match counter_0 Compare match constant register_0 Compare match timer control/status register_1 Compare match counter_1 Compare match constant register_1 WDT Watchdog timer control/status register Watchdog timer counter Watchdog reset control/status register SCIF Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit FIFO data register_0 Serial status register_0 Receive FIFO data register_0 FIFO control register_0 FIFO data count register_0 Serial port register_0 Line status register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit FIFO data register_1 Serial status register_1 Receive FIFO data register_1 FIFO control register_1 FIFO data count register_1 Rev. 3.00 Jun. 18, 2008 Page 1016 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name SCIF Register Name Serial port register_1 Line status register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit FIFO data register_2 Serial status register_2 Receive FIFO data register_2 FIFO control register_2 FIFO data count register_2 Serial port register_2 Line status register_2 Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit FIFO data register_3 Serial status register_3 Receive FIFO data register_3 FIFO control register_3 FIFO data count register_3 Serial port register_3 Line status register_3 Abbreviation SCSPTR_1 SCLSR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 SCSMR_3 SCBRR_3 SCSCR_3 SCFTDR_3 SCFSR_3 SCFRDR_3 SCFCR_3 SCFDR_3 SCSPTR_3 SCLSR_3 ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR NF2CYC Number of Bits Address 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 8 8 8 8 8 8 8 8 8 H'FFFE8820 H'FFFE8824 H'FFFE9000 H'FFFE9004 H'FFFE9008 H'FFFE900C H'FFFE9010 H'FFFE9014 H'FFFE9018 H'FFFE901C H'FFFE9020 H'FFFE9024 H'FFFE9800 H'FFFE9804 H'FFFE9808 H'FFFE980C H'FFFE9810 H'FFFE9814 H'FFFE9818 H'FFFE981C H'FFFE9820 H'FFFE9824 H'FFFEE000 H'FFFEE001 H'FFFEE002 H'FFFEE003 H'FFFEE004 H'FFFEE005 H'FFFEE006 H'FFFEE007 H'FFFEE008 Access Size 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 8 8 8 8 8 8 8 8 8 IIC3 I C bus control register 1 I C bus control register 2 I C bus mode register I C bus interrupt enable register I C bus status register Slave address register I C bus transmit data register I C bus receive data register NF2CYC register 2 2 2 2 2 2 2 Rev. 3.00 Jun. 18, 2008 Page 1017 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name ADC Register Name A/D data register A_0 A/D data register B_0 A/D data register C_0 A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 A/D data register A_1 A/D data register B_1 A/D data register C_1 A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 A/D control/status register_0 A/D control/status register_1 A/D0, A/D1 control register Abbreviation ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_0 ADCSR_1 ADCR DADR0 DADR1 DACR PAIORH PAIORL PACRH3 PACRH2 PACRH1 PACRL4 PACRL3 PACRL2 PACRL1 Number of Bits Address 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 16 16 16 16 16 16 16 16 16 H'FFFE5800 H'FFFE5802 H'FFFE5804 H'FFFE5806 H'FFFE5808 H'FFFE580A H'FFFE580C H'FFFE580E H'FFFE5810 H'FFFE5812 H'FFFE5814 H'FFFE5816 H'FFFE5818 H'FFFE581A H'FFFE581C H'FFFE581E H'FFFE5820 H'FFFE5822 H'FFFE5824 H'FFFE6800 H'FFFE6801 H'FFFE6802 H'FFFE3804 H'FFFE3806 H'FFFE380A H'FFFE380C H'FFFE380E H'FFFE3810 H'FFFE3812 H'FFFE3814 H'FFFE3816 Access Size 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8, 16 8, 16 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 DAC D/A data register 0 D/A data register 1 D/A control register PFC Port A I/O register H Port A I/O register L Port A control register H3 Port A control register H2 Port A control register H1 Port A control register L4 Port A control register L3 Port A control register L2 Port A control register L1 Rev. 3.00 Jun. 18, 2008 Page 1018 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name PFC Register Name Port B I/O register Port B control register 3 Port B control register 2 Port B control register 1 Port C I/O register L Port C control register L1 Port D I/O register H Port D I/O register L Port D control register H4 Port D control register H3 Port D control register H2 Port D control register H1 Port D control register L4 Port D control register L3 Port E I/O register H Port E I/O register L Port E control register H1 Port E control register L4 Port E control register L3 Port E control register L2 Port E control register L1 IRQOUT function control register Abbreviation PBIOR PBCR3 PBCR2 PBCR1 PCIORL PCCRL1 PDIORH PDIORL PDCRH4 PDCRH3 PDCRH2 PDCRH1 PDCRL4 PDCRL3 PEIORH PEIORL PECRH1 PECRL4 PECRL3 PECRL2 PECRL1 IFCR PADRH PADRL PAPRH PAPRL PBDR PBPR PCDRL PCPRL Number of Bits Address 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 H'FFFE3886 H'FFFE3892 H'FFFE3894 H'FFFE3896 H'FFFE3906 H'FFFE3916 H'FFFE3984 H'FFFE3986 H'FFFE3988 H'FFFE398A H'FFFE398C H'FFFE398E H'FFFE3990 H'FFFE3992 H'FFFE3A04 H'FFFE3A06 H'FFFE3A0E H'FFFE3A10 H'FFFE3A12 H'FFFE3A14 H'FFFE3A16 H'FFFE3A22 H'FFFE3800 H'FFFE3802 H'FFFE381C H'FFFE381E H'FFFE3882 H'FFFE389E H'FFFE3902 H'FFFE391E Access Size 8, 16 8, 16 8, 16, 32 8, 16 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16 8, 16 8, 16 I/O port Port A data register H Port A data register L Port A port register H Port A port register L Port B data register Port B port register Port C data register L Port C port register L Rev. 3.00 Jun. 18, 2008 Page 1019 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name I/O port Register Name Port D data register H Port D data register L Port D port register H Port D port register L Port E data register H Port E data register L Port E port register H Port E port register L Port F data register Abbreviation PDDRH PDDRL PDPRH PDPRL PEDRH PEDRL PEPRH PEPRL PFDR STBCR STBCR2 SYSCR1 SYSCR2 STBCR3 STBCR4 SDIR Number of Bits Address 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 16 H'FFFE3980 H'FFFE3982 H'FFFE399C H'FFFE399E H'FFFE3A00 H'FFFE3A02 H'FFFE3A1C H'FFFE3A1E H'FFFE3A82 H'FFFE0014 H'FFFE0018 H'FFFE0402 H'FFFE0404 H'FFFE0408 H'FFFE040C H'FFFE2000 Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8 8 8 8 8 8 16 Powerdown mode Standby control register Standby control register 2 System control register 1 System control register 2 Standby control register 3 Standby control register 4 H-UDI Instruction register Note: * The access sizes of the WDT registers are different between the read and write to prevent incorrect writing. For details, see section 14.3.4, Notes on Register Access. Rev. 3.00 Jun. 18, 2008 Page 1020 of 1160 REJ09B0191-0300 Section 24 List of Registers 24.2 Module Name CPG Register Bits Register Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 FRQCR MCLKCR MSSCS[1:0] NMIL ICR1 IRQ71S IRQ31S ICR2 PINT7S IRQRR IRQ7F PINTER PINT7E PIRR PINT7R IBCR E15 E7 IBNR IPR01 BE[1:0] IRQ70S IRQ30S PINT6S IRQ6F PINT6E PINT6R E14 E6 IFC[2:0] IRQ61S IRQ21S PINT5S IRQ5F PINT5E PINT5R E13 E5 BOVE IRQ60S IRQ20S PINT4S IRQ4F PINT4E PINT4R E12 E4 CKOEN RNGS IRQ51S IRQ11S PINT3S IRQ3F PINT3E PINT3R E11 E3 IRQ50S IRQ10S PINT2S IRQ2F PINT2E PINT2R E10 E2 BN[3:0] STC[2:0] PFC[2:0] MSDIVS[1:0] IRQ41S IRQ01S PINT1S IRQ1F PINT1E PINT1R E9 E1 NMIE IRQ40S IRQ00S PINT0S IRQ0F PINT0E PINT0R E8 INTC ICR0 IPR02 IPR05 IPR06 IPR07 Rev. 3.00 Jun. 18, 2008 Page 1021 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name INTC Register Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 UBC BAR_0 BA31 BA23 BA15 BA7 BA30 BA22 BA14 BA6 BAM30 BAM22 BAM14 BAM6 BA29 BA21 BA13 BA5 BAM29 BAM21 BAM13 BAM5 UBID ID[1:0] BD29 BD21 BD13 BD5 BA28 BA20 BA12 BA4 BAM28 BAM20 BAM12 BAM4 DBE BA27 BA19 BA11 BA3 BAM27 BAM19 BAM11 BAM3 BA26 BA18 BA10 BA2 BAM26 BAM18 BAM10 BAM2 BA25 BA17 BA9 BA1 BAM25 BAM17 BAM9 BAM1 BA24 BA16 BA8 BA0 BAM24 BAM16 BAM8 BAM0 BAMR_0 BAM31 BAM23 BAM15 BAM7 BBR_0 CD[1:0] CP[1:0] SZ[1:0] BD25 BD17 BD9 BD1 BD24 BD16 BD8 BD0 RW[1:0] BD28 BD20 BD12 BD4 BD27 BD19 BD11 BD3 BD26 BD18 BD10 BD2 BDR_0 BD31 BD23 BD15 BD7 BD30 BD22 BD14 BD6 Rev. 3.00 Jun. 18, 2008 Page 1022 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name UBC Register Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 BDM24 BDM16 BDM8 BDM0 BA24 BA16 BA8 BA0 BAM24 BAM16 BAM8 BAM0 Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 BDMR_0 BDM31 BDM23 BDM15 BDM7 BAR_1 BA31 BA23 BA15 BA7 BAMR_1 BAM31 BAM23 BAM15 BAM7 BBR_1 CD[1:0] BDR_1 BD31 BD23 BD15 BD7 BDMR_1 BDM31 BDM23 BDM15 BDM7 BRCR SCMFC0 BD30 BD22 BD14 BD6 BDM30 BDM22 BDM14 BDM6 SCMFC1 PCB1 BD29 BD21 BD13 BD5 BDM29 BDM21 BDM13 BDM5 SCMFD0 PCB0 BDM30 BDM22 BDM14 BDM6 BA30 BA22 BA14 BA6 BAM30 BAM22 BAM14 BAM6 BDM29 BDM21 BDM13 BDM5 BA29 BA21 BA13 BA5 BAM29 BAM21 BAM13 BAM5 UBID ID[1:0] BD28 BD20 BD12 BD4 BDM28 BDM20 BDM12 BDM4 SCMFD1 BDM28 BDM20 BDM12 BDM4 BA28 BA20 BA12 BA4 BAM28 BAM20 BAM12 BAM4 DBE BDM27 BDM19 BDM11 BDM3 BA27 BA19 BA11 BA3 BAM27 BAM19 BAM11 BAM3 RW[1:0] BD27 BD19 BD11 BD3 BDM27 BDM19 BDM11 BDM3 ICF OCF BD26 BD18 BD10 BD2 BDM26 BDM18 BDM10 BDM2 BDM26 BDM18 BDM10 BDM2 BA26 BA18 BA10 BA2 BAM26 BAM18 BAM10 BAM2 BDM25 BDM17 BDM9 BDM1 BA25 BA17 BA9 BA1 BAM25 BAM17 BAM9 BAM1 CP[1:0] SZ[1:0] BD25 BD17 BD9 BD1 BDM25 BDM17 BDM9 BDM1 CKS[1:0] WT ICE OCE BD24 BD16 BD8 BD0 BDM24 BDM16 BDM8 BDM0 Cache CCR1 Rev. 3.00 Jun. 18, 2008 Page 1023 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name Cache Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 CCR2 29/21/13/5 28/20/12/4 DMAIWA IWW[2:0] IWRRD[2:0] TYPE[2:0] 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 BLOCK W3LOAD W2LOAD LE W3LOCK W2LOCK DMAIW[2] HIZCNT IWRWS[2] IWRRS[2:0] BSZ[1:0] IWRWD[2:0] IWRWS[2] IWRRS[2:0] BSZ[1:0] IWRWD[2:0] IWRWS[2] IWRRS[2:0] BSZ[1:0] IWRWD[2:0] IWRWS[2] IWRRS[2:0] BSZ[1:0] IWRWD[2:0] IWRWS[2] IWRRS[2:0] BSZ[1:0] BSC CMNCR DPRTY[1:0] IWRWD[2:0] HIZMEM DMAIW[1:0] CS0BCR IWRWS[1:0] CS1BCR IWRWS[1:0] CS2BCR IWRWS[1:0] CS3BCR IWRWS[1:0] CS4BCR IWRWS[1:0] IWW[2:0] IWRRD[2:0] TYPE[2:0] IWW[2:0] IWRRD[2:0] TYPE[2:0] IWW[2:0] IWRRD[2:0] TYPE[2:0] IWW[2:0] IWRRD[2:0] TYPE[2:0] Rev. 3.00 Jun. 18, 2008 Page 1024 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name BSC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 CS5BCR IWRWS[1:0] CS6BCR IWRWS[1:0] CS7BCR IWRWS[1:0] CS8BCR IWRWS[1:0] CS0WCR* 1 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 IWW[2:0] IWRRD[2:0] TYPE[2:0] IWRWD[2:0] IWRRS[2:0] BSZ[1:0] IWRWD[2:0] IWRRD[2:0] TYPE[2:0] IWRRS[2:0] BSZ[1:0] IWRWD[2:0] IWRRD[2:0] TYPE[2:0] IWRRS[2:0] BSZ[1:0] IWRWD[2:0] IWRRD[2:0] TYPE[2:0] SW[1:0] BST[1:0] BW[1:0] W[3:1] BW[1:0] W[3:1] IWRRS[2:0] BSZ[1:0] WR[3:1] HW[1:0] IWRWS[2] IWRWS[2] IWRWS[2] IWRWS[2] IWW[2:0] IWW[2:0] IWW[2:0] WM WM WM WR[0] CS0WCR* 2 W[0] CS0WCR* 6 W[0] Rev. 3.00 Jun. 18, 2008 Page 1025 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name BSC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 CS1WCR*1 WR[0] CS2WCR* 1 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 BAS BAS BST[1:0] SW[1:0] TRWL[1:0] BAS SW[1:0] BW[1:0] W[3:1] HW[1:0] BAS SW[1:0] WR[3:1] WR[3:1] A3CL[1] A2CL[1] WW[2:0] WR[3:1] HW[1:0] WM WM WM WTRP[1:0] WM WM WR[0] CS2WCR* 3 A2CL[0] CS3WCR* 1 WR[0] CS3WCR* 3 A3CL[0] WTRCD[1:0] WTRC[1:0] WW[2:0] WR[3:1] HW[1:0] CS4WCR*1 WR[0] CS4WCR* 2 W[0] Rev. 3.00 Jun. 18, 2008 Page 1026 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name BSC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 CS5WCR*1 WR[0] CS5WCR* 4 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 SZSEL SA[1:0] TED[3:0] MPXW/BAS SW[1:0] PCW[3:1] BAS SW[1:0] SA[1:0] TED[3:0] PCW[3:1] MPXMD SW[1:0] BAS SW[1:0] WW[2:0] WR[3:1] HW[1:0] TEH[3:0] BW[1:0] W[3:1] WW[2:0] WR[3:1] HW[1:0] TEH[3:0] WR[3:1] HW[1:0] WW[2:0] WR[3:1] HW[1:0] WM PCW[0] WM WM CS6WCR* 1 WR[0] CS6WCR* 4 PCW[0] WM WM WM WM CS6WCR* 5 W[0] MPXAW[1:0] BAS CS7WCR* 1 WR[0] CS8WCR* 1 WR[0] Rev. 3.00 Jun. 18, 2008 Page 1027 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name BSC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 SDCR RTCSR CMF RTCNT CMIE 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 DEEP RMODE A2ROW[1:0] SLOW RFSH A2COL[1:0] PDOWN BACTV A3ROW[1:0] CKS[2:0] A3COL[1:0] RRC[2:0] RTCOR ACSWR ACKEY[7:0] ACOSW[3:0] ACKEYR DMAC SAR_0 DAR_0 Rev. 3.00 Jun. 18, 2008 Page 1028 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 DMATCR_0 CHCR_0 TC DO DM[1:0] DL RSAR_0 RDAR_0 RDMATCR_0 SAR_1 DAR1 DS TL 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 SM[1:0] TB TS[1:0] IE RLD HE HIE RS[3:0] TE DE AM AL Rev. 3.00 Jun. 18, 2008 Page 1029 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 DMATCR_1 CHCR_1 TC DO DM[1:0] DL RSAR_1 RDAR_1 RDMATCR_1 SAR_2 DAR_2 DS TL 29/21/13/5 28/20/12/4 SM[1:0] TB RLD 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 HE HIE RS[3:0] AM AL TS[1:0] IE TE DE Rev. 3.00 Jun. 18, 2008 Page 1030 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 DMATCR_2 CHCR_2 TC DO DM[1:0] DL RSAR_2 RDAR_2 RDMATCR_2 SAR_3 DAR_3 DS 29/21/13/5 28/20/12/4 SM[1:0] TB RLD 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 HE HIE RS[3:0] AM AL TS[1:0] IE TE DE Rev. 3.00 Jun. 18, 2008 Page 1031 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 DMATCR_3 CHCR_3 TC DO DM[1:0] DL RSAR_3 RDAR_3 RDMATCR_3 SAR_4 DAR_4 DS 29/21/13/5 28/20/12/4 SM[1:0] TB RLD 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 HE HIE RS[3:0] AM AL TS[1:0] IE TE DE Rev. 3.00 Jun. 18, 2008 Page 1032 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 DMATCR_4 CHCR_4 TC DM[1:0] RSAR_4 RDAR_4 RDMATCR_4 SAR_5 DAR_5 29/21/13/5 28/20/12/4 SM[1:0] TB RLD 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 HE HIE RS[3:0] TS[1:0] IE TE DE Rev. 3.00 Jun. 18, 2008 Page 1033 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Abbreviation DMATCR_5 Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 DM[1:0] 29/21/13/5 28/20/12/4 SM[1:0] TB RLD 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 HE HIE RS[3:0] CHCR_5 TC TS[1:0] IE TE DE RSAR_5 RDAR_5 RDMATCR_5 SAR_6 DAR_6 Rev. 3.00 Jun. 18, 2008 Page 1034 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Abbreviation DMATCR_6 Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 DM[1:0] 29/21/13/5 28/20/12/4 SM[1:0] TB RLD 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 HE HIE RS[3:0] CHCR_6 TC TS[1:0] IE TE DE RSAR_6 RDAR_6 RDMATCR_6 SAR_7 DAR_7 Rev. 3.00 Jun. 18, 2008 Page 1035 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 DMATCR_7 CHCR_7 TC DM[1:0] RSAR_7 RDAR_7 RDMATCR_7 DMAOR DMARS0 29/21/13/5 28/20/12/4 SM[1:0] TB CMS[1:0] RLD 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 HE HIE RS[3:0] TS[1:0] IE AE TE PR[1:0] NMIF DE DME CH1 MID[5:0] CH0 MID[5:0] CH1 RID[1:0] CH0 RID[1:0] CH3 RID[1:0] CH2 RID[1:0] CH5 RID[1:0] CH4 RID[1:0] CH7 RID[1:0] CH6 RID[1:0] DMARS1 CH3 MID[5:0] CH2 MID[5:0] DMARS2 CH5 MID[5:0] CH4 MID[5:0] DMARS3 CH7 MID[5:0] CH6 MID[5:0] Rev. 3.00 Jun. 18, 2008 Page 1036 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 30/22/14/6 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 TCNT_4 TCDR TTGE TTGE TTGE2 BDC PSYE BF[1:0] CCLR[2:0] CCLR[2:0] 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TPSC[2:0] TPSC[2:0] MD[3:0] MD[3:0] IOA[3:0] IOC[3:0] IOA[3:0] IOC[3:0] CKEG[1:0] CKEG[1:0] BFB BFB BFA BFA IOB[3:0] IOD[3:0] IOB[3:0] IOD[3:0] OE4D N OLS3N TCIEV TCIEV OE4C P OLS3P TGIED TGIED OE3D FB TOCL OLS2N TGIEC TGIEC OE4B WF TOCS OLS2P TGIEB TGIEB OE4A VF OLSN OLS1N TGIEA TGIEA OE3B UF OLSP OLS1P TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 Rev. 3.00 Jun. 18, 2008 Page 1037 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Abbreviation TGRD_4 TSR_3 TSR_4 TITCR TITCNT TBTER TDER TOLBR TBTM_3 TBTM_4 TADCR Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TCFD TCFD T3AEN BF[1:0] UT4AE 3ACOR[2:0] 3ACNT[2:0] TCFV TCFV TGFD TGFD T4VEN TGFC TGFC TGFB TGFB 4VCOR[2:0] 4VCNT[2:0] TGFA TGFA OLS3N UT4BE OLS3P DT4BE OLS2N ITA3AE OLS2P ITA4VE BTE[1:0] TDER OLS1P TTSA TTSA ITB4VE OLS1N TTSB TTSB ITB3AE DT4AE TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 TSYCR TWCR TSTR TSYR TCSYSTR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TTGE CE0A CCE CST4 SYNC4 SCH0 CE0B CST3 SYNC3 SCH1 CCLR[2:0] BFE BFB IOB[3:0] IOD[3:0] TCIEV TCFV TGIED TGFD CE0C SCH2 CE0D SCH3 CKEG[1:0] BFA CE1A SCH4 CE1B CST2 SYNC2 CE2A CST1 SYNC1 SCH3S TPSC[2:0] MD[3:0] IOA[3:0] IOC[3:0] TGIEC TGFC TGIEB TGFB TGIEA TGFA CE2B WRE CST0 SYNC0 SCH4S RWE Rev. 3.00 Jun. 18, 2008 Page 1038 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Abbreviation TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 TCRV_5 Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TTGE2 CCLR[1:0] IOB[3:0] CKEG[1:0] TTSE TGIEF TGFF TTSB TPSC[2:0] MD[3:0] IOA[3:0] TGIEE TGFE TTSA TTGE TCFD TCIEU TCFU TCIEV TCFV TGIEB TGFB TGIEA TGFA CCLR[1:0] IOB[3:0] I2BE I2AE I1BE TPSC[2:0] I1AE CKEG[1:0] MD[3:0] IOA[3:0] TTGE TCFD TCIEU TCFU TCIEV TCFV TGIEB TGFB TGIEA TGFA IOC[4:0] TPSC[1:0] TPSC[1:0] Rev. 3.00 Jun. 18, 2008 Page 1039 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Abbreviation TIORV_5 TCNTW_5 TGRW_5 TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5 TCNTCMPCLR Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 IOC[4:0] IOC[4:0] TPSC[1:0] CMFU5 TGIE5U CSTU5 CMPCLR 5U CMFV5 TGIE5V CSTV5 CMFW5 TGIE5W CSTW5 CMPCLR CMPCLR 5V TPSC[2:0] TPSC[2:0] 5W MTU2S TCR_3S TCR_4S TMDR_3S TMDR_4S TIORH_3S TIORL_3S TIORH_4S TIORL_4S TIER_3S TIER_4S TOERS TGCRS TOCR1S TOCR2S TCNT_3S TCNT_4S TCDRS TDDRS TGRA_3S TGRB_3S TGRA_4S TGRB_4S TTGE TTGE CCLR[2:0] CCLR[2:0] BFB BFB IOB[3:0] IOD[3:0] IOB[3:0] IOD[3:0] TTGE2 BDC PSYE BF[1:0] OE4D N OLS3N CKEG[1:0] CKEG[1:0] BFA BFA MD[3:0] MD[3:0] IOA[3:0] IOC[3:0] IOA[3:0] IOC[3:0] TCIEV TCIEV OE4C P OLS3P TGIED TGIED OE3D FB TOCL OLS2N TGIEC TGIEC OE4B WF TOCS OLS2P TGIEB TGIEB OE4A VF OLSN OLS1N TGIEA TGIEA OE3B UF OLSP OLS1P Rev. 3.00 Jun. 18, 2008 Page 1040 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2S Register Abbreviation TCNTSS TCBRS TGRC_3S TGRD_3S TGRC_4S TGRD_4S TSR_3S TSR_4S TITCRS TITCNTS TBTERS TDERS TOLBRS TBTM_3S TBTM_4S TADCRS Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TCFD TCFD T3AEN BF[1:0] UT4AE 3ACOR[2:0] 3ACNT[2:0] TCFV TCFV TGFD TGFD T4VEN TGFC TGFC TGFB TGFB 4VCOR[2:0] 4VCNT[2:0] TGFA TGFA OLS3N UT4BE OLS3P DT4BE OLS2N ITA3AE OLS2P ITA4VE BTE[1:0] TDER OLS1P TTSA TTSA ITB4VE OLS1N TTSB TTSB ITB3AE DT4AE TADCORA_4S TADCORB_4S TADCOBRA_4S TADCOBRB_4S TSYCRS TWCRS TSTRS TSYRS TRWERS TCNTU_5S TGRU_5S TCRU_5S TIORU_5S TCNTV_5S IOC[4:0] TPSC[1:0] CE0A CCE CST4 SYNC4 CE0B CST3 SYNC3 CE0C CE0D CE1A CE1B CST2 SYNC2 CE2A CST1 SYNC1 CE2B WRE CST0 SYNC0 RWE Rev. 3.00 Jun. 18, 2008 Page 1041 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2S Register Abbreviation TGRV_5S TCRV_5S TIORV_5S TCNTW_5S TGRW_5S TCRW_5S TIORW_5S TSR_5S TIER_5S TSTR_5S TCNTCMPCLRS Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 IOC[4:0] TPSC[1:0] IOC[4:0] TPSC[1:0] CMFU5 TGIE5U CSTU5 CMPCLR 5U CMFV5 TGIE5V CSTV5 CMFW5 TGIE5W CSTW5 CMPCLR CMPCLR 5V 5W PIE1 POE2 ICSR1 POE3F POE2F POE1F POE0F POE3M[1:0] OCSR1 OSF1 ICSR2 POE7F POE6F POE2M[1:0] POE5F POE4F POE1M[1:0] POE0M[1:0] OCE1 OIE1 PIE2 POE7M[1:0] OCSR2 OSF2 ICSR3 SPOER POE6M[1:0] POE8F POE5M[1:0] MTU2S HIZ POE4M[1:0] OCE2 POE8E OIE2 PIE3 POE8M[1:0] MTU2 CH0HIZ MTU2 PE1ZE MTU2S P2CZE MTU2S P8CZE MTU2 CH34HIZ MTU2 PE0ZE MTU2S P3CZE MTU2S P9CZE POECR1 MTU2 PE3ZE MTU2 PE2ZE MTU2S P1CZE POECR2 MTU2 P1CZE MTU2S P4CZE MTU2 P2CZE MTU2S P5CZE MTU2 P3CZE MTU2S P6CZE MTU2S P7CZE Rev. 3.00 Jun. 18, 2008 Page 1042 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name CMT Register Abbreviation CMSTR Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 STR0 CKS[1:0] 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CMIE STR1 CMCSR_0 CMF CMCNT_0 CMCOR_0 CMCSR_1 CMF CMIE CKS[1:0] CMCNT_1 CMCOR_1 WDT WTCSR WTCNT WRCSR IOVF WT/IT TME CKS[2:0] WOVF C/A RSTE CHR RSTS PE O/E STOP CKS[1:0] SCIF SCSMR_0 SCBRR_0 SCSCR_0 TIE SCFTDR_0 SCFSR_0 ER SCFRDR_0 SCFCR_0 MCE TFRST T[4:0] R[4:0] RSTRG[2:0] RFRST LOOP PER[3:0] TEND TDFE BRK FER FER[3:0] PER RDF DR RIE TE RE REIE CKE[1:0] RTRG[1:0] SCFDR_0 TTRG[1:0] Rev. 3.00 Jun. 18, 2008 Page 1043 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name SCIF Register Abbreviation SCSPTR_0 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 SPB2DT ORER CKS[1:0] 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 RTSIO RTSDT CHR CTSIO PE CTSDT O/E SCKIO STOP SCKDT SPB2IO SCLSR_0 SCSMR_1 C/A SCBRR_1 SCSCR_1 TIE SCFTDR_1 SCFSR_1 ER SCFRDR_1 SCFCR_1 MCE TFRST T[4:0] R[4:0] CTSDT O/E SCKIO STOP SCKDT SPB2IO CKS[1:0] SPB2DT ORER RSTRG[2:0] RFRST LOOP PER[3:0] TEND TDFE BRK FER FER[3:0] PER RDF DR RIE TE RE REIE CKE[1:0] RTRG[1:0] SCFDR_1 SCSPTR_1 RTSIO SCLSR_1 SCSMR_2 C/A SCBRR_2 SCSCR_2 TIE SCFTDR_2 SCFSR_2 ER SCFRDR_2 PER[3:0] TEND RIE RTSDT CHR TTRG[1:0] CTSIO PE TE RE REIE CKE[1:0] FER[3:0] BRK FER PER RDF DR TDFE Rev. 3.00 Jun. 18, 2008 Page 1044 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name SCIF Register Abbreviation SCFCR_2 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MCE TFRST T[4:0] R[4:0] CTSDT O/E SCKIO STOP SCKDT SPB2IO RSTRG[2:0] RFRST RTRG[1:0] SCFDR_2 SCSPTR_2 RTSIO SCLSR_2 SCSMR_3 C/A SCBRR_3 SCSCR_3 TIE SCFTDR_3 SCFSR_3 ER SCFRDR_3 SCFCR_3 PER[3:0] TEND RIE RTSDT CHR TTRG[1:0] CTSIO PE LOOP SPB2DT ORER CKS[1:0] TE RE REIE CKE[1:0] FER[3:0] BRK FER PER RDF DR TDFE MCE TFRST T[4:0] R[4:0] RSTRG[2:0] RFRST LOOP RTRG[1:0] SCFDR_3 SCSPTR_3 RTSIO SCLSR_3 IIC3 ICCR1 ICCR2 ICMR ICIER ICSR SAR ICE BBSY MLS TIE TDRE RTSDT RCVD SCP TEIE TEND TTRG[1:0] CTSIO MST SDAO RIE RDRF CTSDT TRS SDAOP NAKIE NACKF SVA[6:0] SCKIO SCKDT CKS[3:0] SPB2IO SPB2DT ORER SCLO BCWP STIE STOP IICRST BC[2:0] ACKE AL/OVE ACKBR AAS ACKBT ADZ FS Rev. 3.00 Jun. 18, 2008 Page 1045 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name IIC3 Register Abbreviation ICDRT ICDRR NF2CYC Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 NF2CYC ADC ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 Rev. 3.00 Jun. 18, 2008 Page 1046 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name ADC Register Abbreviation ADDRG_1 Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 ADDRH_1 ADCSR_0 ADF ADIE ADST MDS[2:0] TRGS[3:0] CKS[1:0] ADCSR_1 ADF ADIE ADST CH[2:0] TRGS[3:0] CH[2:0] MDS[2:0] CKS[1:0] ADCR DSMP DAC DADR0 DADR1 DACR PFC PAIORH DAOE1 PA23IOR PAIORL PA7IOR PACRH3 PACRH2 PACRH1 PACRL4 PACRL3 PACRL2 PACRL1 DAOE0 PA22IOR PA6IOR DAE PA21IOR PA13IOR PA5IOR PA25MD[2:0] PA20IOR PA12IOR PA4IOR PA19IOR PA11IOR PA3IOR PA18IOR PA2IOR PA25IOR PA24IOR PA17IOR PA16IOR PA9IOR PA1IOR PA24MD[2:0] PA8IOR PA0IOR PA23MD[1:0] PA21MD[2:0] PA19MD[2:0] PA17MD[1:0] PA22MD[1:0] PA20MD[2:0] PA18MD[2:0] PA16MD[2:0] PA13MD[1:0] PA11MD[1:0] PA9MD[2:0] PA7MD[1:0] PA5MD[2:0] PA3MD[2:0] PA1MD[2:0] PA12MD[1:0] PA8MD[2:0] PA6MD[1:0] PA4MD[2:0] PA2MD[2:0] PA0MD[2:0] Rev. 3.00 Jun. 18, 2008 Page 1047 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name PFC Register Abbreviation PBIOR Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 PB5IOR PB9MD[2:0] PB5MD[2:0] PB3MD[2:0] PD30IOR PD22IOR PD14IOR PD29IOR PD21IOR PD13IOR 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 PB4IOR PC1MD PD28IOR PD20IOR PD12IOR PD27IOR PD19IOR PD11IOR PD26IOR PD18IOR PD10IOR PB9IOR PB4MD[2:0] PB2MD[2:0] PC1IOR PC0IOR PC0MD PBCR3 PBCR2 PBCR1 PCIORL PCCRL1 PDIORH PD31IOR PD23IOR PD25IOR PD24IOR PD17IOR PD16IOR PD9IOR PD8IOR PDIORL PD15IOR PDCRH4 PD31MD[1:0] PD29MD[1:0] PD27MD[1:0] PD25MD[1:0] PD23MD[1:0] PD21MD[2:0] PD19MD[2:0] PD17MD[2:0] PD30MD[1:0] PD28MD[1:0] PD26MD[1:0] PD24MD[1:0] PD22MD[2:0] PD20MD[2:0] PD18MD[2:0] PD16MD[2:0] PD14MD[1:0] PD12MD[1:0] PD10MD[1:0] PD8MD[1:0] PE16IOR PDCRH3 PDCRH2 PDCRH1 PDCRL4 PD15MD[1:0] PD13MD[1:0] PD11MD[1:0] PD9MD[1:0] PDCRL3 PEIORH Rev. 3.00 Jun. 18, 2008 Page 1048 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name PFC Register Abbreviation PEIORL Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 PE15IOR PE7IOR PE14IOR PE6IOR PE13IOR PE5IOR PE15MD[2:0] PE13MD[1:0] PE11MD[2:0] PE9MD[2:0] PE7MD[2:0] PE5MD[2:0] PA22DR PA6DR PA22PR PA6PR PE3MD[1:0] PE1MD[1:0] PA21DR PA13DR PA5DR PA21PR PA13PR PA5PR PB5DR PB5PR PA20DR PA12DR PA4DR PA20PR PA12PR PA4PR PB4DR PB4PR PE12IOR PE4IOR PE11IOR PE3IOR PE10IOR PE2IOR PE9IOR PE1IOR PE16MD[2:0] PE14MD[2:0] PE12MD[1:0] PE10MD[1:0] PE8MD[1:0] PE6MD[2:0] PE4MD[2:0] PE2MD[1:0] PE0MD[1:0] PE8IOR PE0IOR PECRH1 PECRL4 PECRL3 PECRL2 PECRL1 IFCR IRQMD[3:2] PA19DR PA11DR PA3DR PA19PR PA11PR PA3PR PB3DR PB3PR PA18DR PA2DR PA18PR PA2PR PB2DR PB2PR IRQMD[1:0] PA25DR PA17DR PA9DR PA1DR PA25PR PA17PR PA9PR PA1PR PB9DR PB9PR PC1DR PC1PR PA24DR PA16DR PA8DR PA0DR PA24PR PA16PR PA8PR PA0PR PC0DR PC0PR I/O port PADRH PA23DR PADRL PA7DR PAPRH PA23PR PAPRL PA7PR PBDR PBPR PCDRL PCPRL Rev. 3.00 Jun. 18, 2008 Page 1049 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name I/O port Register Bit Bit Bit Bit Bit Bit Bit Bit Abbreviation 31/23/15/7 PDDRH PD31DR PD23DR PDDRL PD15DR PDPRH PD31PR PD23PR PDPRL PD15PR PEDRH PEDRL PE15DR PE7DR PEPRH PEPRL PE15PR PE7PR PFDR PF7DR 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 PD30DR PD22DR PD14DR PD30PR PD22PR PD14PR PE14DR PE6DR PE14PR PE6PR PF6DR MSTP9 MSTP36 MSTP46 PD29DR PD21DR PD13DR PD29PR PD21PR PD13PR PE13DR PE5DR PE13PR PE5PR PF5DR MSTP8 MSTP35 MSTP45 PD28DR PD20DR PD12DR PD28PR PD20PR PD12PR PE12DR PE4DR PE12PR PE4PR PF4DR MSTP34 MSTP44 PD27DR PD19DR PD11DR PD27PR PD19PR PD11PR PE11DR PE3DR PE11PR PE3PR PF3DR RAME3 RAMWE3 MSTP33 PD26DR PD18DR PD10DR PD26PR PD18PR PD10PR PE10DR PE2DR PE10PR PE2PR PF2DR RAME2 PD25DR PD17DR PD9DR PD25PR PD17PR PD9PR PE9DR PE1DR PE9PR PE1PR PF1DR RAME1 PD24DR PD16DR PD8DR PD24PR PD16PR PD8PR PE16DR PE8DR PE0DR PE16PR PE8PR PE0PR PF0DR RAME0 Powerdown mode STBCR STBCR2 SYSCR1 SYSCR2 STBCR3 STBCR4 STBY MSTP10 HIZ MSTP47 RAMWE2 RAMWE1 RAMWE0 MSTP32 MSTP42 MSTP31 Rev. 3.00 Jun. 18, 2008 Page 1050 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name H-UDI Register Abbreviation SDIR Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TI[7:0] Notes: 1. 2. 3. 4. 5. 6. When normal memory, SRAM with byte selection, or MPX-I/O is the memory type When burst ROM (clocked asynchronous) is the memory type When SDRAM is the memory type When PCMCIA is the memory type When burst MPX-I/O is the memory type When burst ROM (clocked synchronous) is the memory type Rev. 3.00 Jun. 18, 2008 Page 1051 of 1160 REJ09B0191-0300 Section 24 List of Registers 24.3 Module Name CPG Register States in Each Operating Mode Register Abbreviation FRQCR MCLKCR Power-On Reset Initialized* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized 1 Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained* Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained 2 Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained INTC ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR IPR01 IPR02 IPR05 IPR06 IPR07 IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 UBC BAR_0 BAMR_0 BBR_0 BDR_0 BDMR_0 BAR_1 BAMR_1 Rev. 3.00 Jun. 18, 2008 Page 1052 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name UBC Register Abbreviation BBR_1 BDR_1 BDMR_1 BRCR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained (Flag processing continued) Retained (Count-up continued) Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained (Flag processing continued) Retained (Count-up continued) Cache CCR1 CCR2 BSC CMNCR CS0BCR CS1BCR CS2BCR CS3BCR CS4BCR CS5BCR CS6BCR CS7BCR CS8BCR CS0WCR CS1WCR CS2WCR CS3WCR CS4WCR CS5WCR CS6WCR CS7WCR CS8WCR SDCR RTCSR RTCNT Initialized Retained Rev. 3.00 Jun. 18, 2008 Page 1053 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name BSC Register Abbreviation RTCOR ACSWR ACKEYR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained DMAC SAR_0 DAR_0 DMATCR_0 CHCR_0 RSAR_0 RDAR_0 RDMATCR_0 SAR_1 DAR_1 DMATCR_1 CHCR_1 RSAR_1 RDAR_1 RDMATCR_1 SAR_2 DAR_2 DMATCR_2 CHCR_2 RSAR_2 RDAR_2 RDMATCR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 RSAR_3 RDAR_3 RDMATCR_3 Rev. 3.00 Jun. 18, 2008 Page 1054 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Abbreviation SAR_4 DAR_4 DMATCR_4 CHCR_4 RSAR_4 RDAR_4 RDMATCR_4 SAR_5 DAR_5 DMATCR_5 CHCR_5 RSAR_5 RDAR_5 RDMATCR_5 SAR_6 DAR_6 DMATCR_6 CHCR_6 RSAR_6 RDAR_6 RDMATCR_6 SAR_7 DAR_7 DMATCR_7 CHCR_7 RSAR_7 RDAR_7 RDMATCR_7 DMAOR DMARS0 DMARS1 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 3.00 Jun. 18, 2008 Page 1055 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name DMAC Register Abbreviation DMARS2 DMARS3 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained MTU2 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 Rev. 3.00 Jun. 18, 2008 Page 1056 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Abbreviation TSR_4 TITCR TITCNT TBTER TDER TOLBR TBTM_3 TBTM_4 TADCR TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 TSYCR TWCR TSTR TSYR TCSYSTR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 3.00 Jun. 18, 2008 Page 1057 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Abbreviation TGRF_0 TIER2_0 TSR2_0 TBTM_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 TCRV_5 TIORV_5 TCNTW_5 TGRW_5 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 3.00 Jun. 18, 2008 Page 1058 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2 Register Abbreviation TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5 TCNTCMPCLR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained MTU2S TCR_3S TCR_4S TMDR_3S TMDR_4S TIORH_3S TIORL_3S TIORH_4S TIORL_4S TIER_3S TIER_4S TOERS TGCRS TOCR1S TOCR2S TCNT_3S TCNT_4S TCDRS TDDRS TGRA_3S TGRB_3S TGRA_4S TGRB_4S TCNTSS TCBRS TGRC_3S Rev. 3.00 Jun. 18, 2008 Page 1059 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2S Register Abbreviation TGRD_3S TGRC_4S TGRD_4S TSR_3S TSR_4S TITCRS TITCNTS TBTERS TDERS TOLBRS TBTM_3S TBTM_4S TADCRS TADCORA_4S TADCORB_4S Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained TADCOBRA_4S Initialized TADCOBRB_4S Initialized TSYCRS TWCRS TSTRS TSYRS TRWERS TCNTU_5S TGRU_5S TCRU_5S TIORU_5S TCNTV_5S TGRV_5S TCRV_5S TIORV_5S TCNTW_5S Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 3.00 Jun. 18, 2008 Page 1060 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name MTU2S Register Abbreviation TGRW_5S TCRW_5S TIORW_5S TSR_5S TIER_5S TSTR_5S Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained TCNTCMPCLRS Initialized POE2 ICSR1 OCSR1 ICSR2 OCSR2 ICSR3 SPOER POECR1 POECR2 CMT CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 WDT WTCSR WTCNT WRCSR SCIF SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized* Initialized Initialized Initialized Undefined Initialized Undefined 1 Retained Retained Retained Retained Retained Retained Retained Rev. 3.00 Jun. 18, 2008 Page 1061 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name SCIF Register Abbreviation SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 SCSMR_3 SCBRR_3 SCSCR_3 SCFTDR_3 SCFSR_3 SCFRDR_3 SCFCR_3 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 3.00 Jun. 18, 2008 Page 1062 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name SCIF Register Abbreviation SCFDR_3 SCSPTR_3 SCLSR_3 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained/ Initialized (bc3-0) Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Retained Retained Retained Retained Retained Retained/ Initialized (bc3-0) Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained IIC3 ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR NF2CYC ADC ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 3.00 Jun. 18, 2008 Page 1063 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name ADC Register Abbreviation ADCSR_1 ADCR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained DAC DADR0 DADR1 DACR PFC PAIORH PAIORL PACRH3 PACRH2 PACRH1 PACRL4 PACRL3 PACRL2 PACRL1 PBIOR PBCR3 PBCR2 PBCR1 PCIORL PCCRL1 PDIORH PDIORL PDCRH4 PDCRH3 PDCRH2 PDCRH1 PDCRL4 PDCRL3 PEIORH PEIORL PECRH1 Rev. 3.00 Jun. 18, 2008 Page 1064 of 1160 REJ09B0191-0300 Section 24 List of Registers Module Name PFC Register Abbreviation PECRL4 PECRL3 PECRL2 PECRL1 IFCR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Initialized Undefined Initialized Undefined Initialized Initialized Undefined Undefined Initialized Initialized Undefined Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained I/O port PADRH PADRL PAPRH PAPRL PBDR PBPR PCDRL PCPRL PDDRH PDDRL PDPRH PDPRL PEDRH PEDRL PEPRH PEPRL PFDR Power-down STBCR mode STBCR2 SYSCR1 SYSCR2 STBCR3 STBCR4 H-UDI* 3 SDIR Notes: 1. Retains the previous value after an internal power-on reset by means of the WDT. 2. Bits BN[3:0] are initialized. 3. Initialized by TRST assertion or in the Test-Logic-Reset state of the TAP controller. Rev. 3.00 Jun. 18, 2008 Page 1065 of 1160 REJ09B0191-0300 Section 24 List of Registers Rev. 3.00 Jun. 18, 2008 Page 1066 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Section 25 Electrical Characteristics 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Power supply voltage (I/O) Power supply voltage (Internal) Symbol PVCC VCC PLLVCC Analog power supply voltage Analog reference voltage Input voltage AVCC AVref -0.3 to 4.6 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to 5.5 -0.3 to PVCC +0.3 -20 to +85 -55 to +125 V V V V V C C Value -0.3 to 4.6 -0.3 to 1.7 Unit V V Analog input voltage pin VAN PB2, PB3 Other input pins Vin Vin Topr Tstg Operating temperature Storage temperature Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Rev. 3.00 Jun. 18, 2008 Page 1067 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.2 Power-On/Power-Off Sequence Power-on/power-off sequence and their recommended values are shown below. PVcc, AVcc (3.3 V power supply) PVcc, AVcc Min. voltage (3.0 V) Vcc, PLLVcc (1.25 V power supply) Vcc, PLLVcc Min. voltage (1.15 V) GND tunc Pin status undefined Normal operation period tunc Pin status undefined Figure 25.1 Power-On/Power-Off Sequence Table 25.2 Recommended Time for Power-On/Power-Off Sequence Item Undefined time Note: Symbol tunc Maximum Allowance Value 100 Unit ms The table shown above is recommended values, so they represent guidelines rather than strict requirements. Either 3.3 V- or 1.25 V- power supply can be turned on or off first, though, an undefined period appears until the power that is turned on later rises to the Min. voltage or after the power that is turned off earlier passes the Min. voltage to 0 V. During these periods, pin or internal states become undefined. Design the system so that these undefined states do not cause an overall malfunction. Rev. 3.00 Jun. 18, 2008 Page 1068 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.3 DC Characteristics Table 25.3 lists DC characteristics. Table 25.3 DC Characteristics (1) [Common Items] Conditions: Ta = -20C to +85C Item Power supply voltage Symbol PVCC Min. 3.0 Typ. 3.3 Max. 3.6 Unit V Test Conditions VCC PLLVCC Analog power supply voltage Current Normal operation 1 consumption* Sleep mode AVCC ICC* Isleep 2 1.15 1.25 1.35 V 3.0 -- -- 3.3 150 110 3.6 300 220 V mA mA VCC = 1.25 V I = 200 MHz B = 66 MHz P = 33 MHz Standby mode Istby -- -- 80 mA Ta > 50C VCC = 1.25 V -- -- 20 mA Ta 50C VCC = 1.25 V Input leakage current Three-state leakage current All input pins |Iin | -- -- -- -- 1.0 1.0 A A Vin = 0.5 to PVCC - 0.5 V Vin = 0.5 to PVCC - 0.5 V All input/output pins, |ISTI | all output pins (except PB2, PB3, and pins with weak keeper) (off state) PB2, PB3 -- Cin AICC -- -- -- AIref -- -- -- 2 1 2 10 20 4 3 4 A pF mA A mA Input capacitance All pins Analog power During A/D or D/A supply current conversion Waiting for A/D or D/A conversion Analog reference voltage current Rev. 3.00 Jun. 18, 2008 Page 1069 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Caution: When the A/D converter or D/A converter is not in use, the AVCC and AVSS pins should not be open. Notes: 1. Current consumption values are when all output pins are unloaded. 2. ICC, Isleep, and Istby represent the total currents consumed in the Vcc and PLLVCC systems. Table 25.3 DC Characteristics (2) [Except for I2C-Related Pins] Conditions: VCC = PLLVCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PLLVSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Input high voltage RES, MRES, NMI, MD2, MD0, MD_CLK2, MD_CLK0, ASEMD, TRST, EXTAL, CKIO PF7 to PF0 Input pins other than above (excluding Schmitt pins) Input low voltage RES, MRES, NMI, MD2, MD0, MD_CLK2, MD_CLK0, ASEMD, TRST, EXTAL, CKIO Input pins other than above (excluding Schmitt pins) -0.3 -- 0.8 V VIL -0.3 -- 0.5 V 2.2 2.2 -- -- AVCC + 0.3 V PVCC + 0.3 V Symbol VIH Min. Typ. Max. Unit Test Conditions PVCC - 0.5 -- PVCC + 0.3 V Rev. 3.00 Jun. 18, 2008 Page 1070 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Item Symbol Min. PVCC - 0.5 -- Typ. -- -- -- Max. -- 0.5 -- Unit V V V Test Conditions Schmitt trigger TIOC0A to TIOC0D, VT+ input TIOC1A, TIOC1B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TIC5U to TIC5W, TCLKA to TCLKD, TIOC3AS, TIOC3BS, TIOC3CS, TIOC3DS, TIOC4AS, TIOC4BS, TIOC4CS, TIOC4DS, TIC5US, TIC5VS, TIC5WS, POE8 to POE0, SCK3 to SCK0, RxD3 to RxD0, CTS3, IRQ7 to IRQ0, PINT7 to PINT0 Output high voltage PD29 to PD24, PD15 to PD11, PD9, PE15 to PE11, PE9 All output pins except for above pins Output low voltage PD29 to PD24, PD15 to PD11, PD9, PE15 to PE11, PE9 All output pins except for above pins RAM standby voltage VRAM VOL VOH VT - + - characteristics TIOC2A, TIOC2B, VT - VT 0.2 PVCC - 0.8 -- -- V IOH = -5 mA PVCC - 0.5 -- -- V IOH = -200 A -- -- 0.9 V IOL = 15 mA -- -- 0.4 IOL = 1.6 mA 0.75 -- -- V Measured by VCC (= PLLVCC) as parameter Rev. 3.00 Jun. 18, 2008 Page 1071 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Table 25.3 DC Characteristics (3) [I2C-Related Pins*] Conditions: VCC = PLLVCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PLLVSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Input high voltage Input low voltage Schmitt trigger input characteristics Output low voltage Symbol VIH VIL VIH - VIL VOL Min. PVCC x 0.7 -0.3 Typ. -- -- Max. 5.5 Unit V Test Conditions PVCC x 0.3 V -- 0.4 V V IOL = 3.0 mA PVCC x 0.05 -- -- -- Note: * The PB2/IRQ0/POE0/SCL and PB3/IRQ1/POE1/SDA pins (open-drain pins) Table 25.4 Permissible Output Currents Conditions: VCC = PLLVCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PLLVSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Permissible output low current (per pin) PB2, PB3 PD29 to PD24, PD15 to PD11, PD9, PE15 to PE11, PE9 Output pins other than above Permissible output low current (total) Permissible output high current (per pin) PD29 to PD24, PD15 to PD11, PD9, PE15 to PE11, PE9 Output pins other than above Permissible output high current (total) Caution: -IOH IOL -IOH Symbol IOL Min. Typ. Max. 10 15 Unit mA mA 2 150 5 mA mA mA 2 50 mA mA To protect the LSI's reliability, do not exceed the output current values in table 25.4. Rev. 3.00 Jun. 18, 2008 Page 1072 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 25.5 Maximum Operating Frequency Conditions: PVCC = 3.0 V to 3.6 V, VCC = 1.15 V to 1.35 V, AVCC = 3.0 V to 3.6 V, PVSS = VSS = AVSS = 0 V, Ta = -20C to +85C Item Operating frequency CPU (I) Internal bus, external bus (B) Peripheral module (P) Symbol Min. f 20 20 1.7 Typ. -- -- -- Max. 200 66 33 Unit MHz MHz MHz Remarks Rev. 3.00 Jun. 18, 2008 Page 1073 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.1 Clock Timing Table 25.6 Clock Timing Conditions: PVCC = 3.0 V to 3.6 V, VCC = 1.15 V to 1.35 V, AVCC = 3.0 V to 3.6 V, PVSS = VSS = AVSS = 0 V, Ta = -20C to +85C Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input pulse low width EXTAL clock input pulse high width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input pulse low width CKIO clock input pulse high width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output pulse low width CKIO clock output pulse high width CKIO clock output rise time CKIO clock output fall time Power-on oscillation setting time Oscillation settling time on return from standby 1 Oscillation settling time on return from standby 2 Symbol Min. fEX tEXcyc tEXL tEXH tEXr tEXf fCK tCKcyc tCKIL tCKIH tCKIr tCKIf fOP tcyc tCKOL tCKOH tCKOr tCKOf tOSC1 tOSC2 tOSC3 10 30 7 7 20 15 4.5 4.5 20 15 4.5 4.5 10 10 10 Max. 33 100 4 4 66 50 3 3 66 50 3 3 Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms ms Figure 25.5 Figure 25.6 Figure 25.7 Figure 25.4 Figure 25.3 Figure Figure 25.2 Rev. 3.00 Jun. 18, 2008 Page 1074 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics tEXcyc EXTAL* (input) tEXH tEXL VIH 1/2 PVcc tEXr 1/2 PVcc VIH VIH VIL tEXf VIL Note: * When the clock is input on the EXTAL pin. Figure 25.2 EXTAL Clock Input Timing tCKIcyc CKIO (input) tCKIH tCKIL VIH 1/2 PVcc tCKIr 1/2 PVcc VIH VIH VIL tCKIf VIL Figure 25.3 CKIO Clock Input Timing tcyc tCKOH CKIO (output) VOH VOL tCKOf tCKOL VOH VOL 1/2 PVcc VOH 1/2 PVcc tCKOr Figure 25.4 CKIO Clock Output Timing Rev. 3.00 Jun. 18, 2008 Page 1075 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Oscillation settling time CKIO, Internal clock Vcc Vcc Min. tOSC1 RES, MRES Note: Oscillation settling time when the internal oscillator is used. Figure 25.5 Power-On Oscillation Settling Time Standby period CKIO, Internal clock Oscillation settling time tOSC2 RES, MRES Note: Oscillation settling time when the internal oscillator is used. Figure 25.6 Oscillation Settling Time on Return from Standby (Return by Reset) Standby period CKIO, Internal clock Oscillation settling time tOSC3 NMI, IRQ Note: Oscillation settling time when the internal oscillator is used. Figure 25.7 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ) Rev. 3.00 Jun. 18, 2008 Page 1076 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.2 Control Signal Timing Table 25.7 Control Signal Timing Conditions: PVCC = 3.0 V to 3.6 V, VCC = 1.15 V to 1.35 V, AVCC = 3.0 V to 3.6 V, PVSS = VSS = AVSS = 0 V, Ta = -20C to +85C B = 66.67 MHz Item RES pulse width MRES pulse width NMI pulse width IRQ pulse width PINT pulse width IRQOUT/REFOUT output delay time BREQ setup time BREQ hold time BACK delay time Bus buffer off time 1 Bus buffer off time 2 Bus buffer on time 1 Bus buffer on time 2 BACK setup time for bus buffer off Symbol tRESW tMRESW tNMIW tIRQW tPINTW tIRQOD tBREQS tBREQH tBACKD tBOFF1 tBOFF2 tBON1 tBON2 tBACKS Min. 20* 20* 20* 20* 20 -- 1/2tcyc + 7 1/2tcyc + 2 -- -- -- -- -- 0 1 Max. -- -- -- -- -- 100 -- -- Unit tcyc tcyc tcyc tcyc tcyc ns ns ns Figure Figure 25.8 2 3 Figure 25.9 3 Figure 25.10 Figure 25.11 1/2tcyc + 13 ns 15 15 15 15 -- ns ns ns ns ns Notes: 1. In standby mode or when the clock multiplication ratio is changed, tRESW = tOSC2 (10 ms). 2. In standby mode, tMRESW = tOSC2 (10 ms). 3. In standby mode, tNMIW/tIRQW = tOSC2 (10 ms). Rev. 3.00 Jun. 18, 2008 Page 1077 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics tRESW/tMRESW RES MRES Figure 25.8 Reset Input Timing tNMIW NMI tIRQW IRQ7 to IRQ0 tPINTW PINT7 to PINT0 Figure 25.9 Interrupt Signal Input Timing CKIO tIRQOD tIRQOD IRQOUT/ REFOUT Figure 25.10 Interrupt Signal Output Timing Rev. 3.00 Jun. 18, 2008 Page 1078 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics tBOFF2 CKIO (HIZCNT = 0) tBON2 CKIO (HIZCNT = 1) tBREQH tBREQS tBREQH tBREQS BREQ tBACKD tBACKD BACK tBACKS tBOFF1 tBON1 A25 to A0, D31 to D0 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, CKE tBOFF2 tBON2 When HZCNT = 0 When HZCNT = 1 Figure 25.11 Bus Release Timing Rev. 3.00 Jun. 18, 2008 Page 1079 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.3 Bus Timing Table 25.8 Bus Timing Conditions: Clock mode 2/7, PVCC = 3.0 V to 3.6 V, PVSS = 0 V, Ta = -20C to +85C B = 66.66 MHz*4 Item Address delay time 1 Symbol tAD1 Min. 0 or 1* 2 Max. 13 Unit ns Figure Figures 25.12 to 25.37, 25.40 to 25.43 Figure 25.20 Figures 25.38, 25.39 Figures 25.12 to 25.15, 25.20 Figures 25.12 to 25.15 Figures 25.12 to 25.34, 25.38, 25.40 to 25.43 Figures 25.12 to 25.37, 25.40 to 25.43 Figures 25.38, 25.39 Figures 25.12 to 25.37, 25.40 to 25.43 Figures 25.38, 25.39 Figures 25.12 to 25.16, 25.18 to 25.20, 25.40, 25.41 Figures 25.12 to 25.16, 25.18, 25.19, 25.40 to 25.43 Figures 25.17, 25.21 to 25.24, 25.29 to 25.31 Figure 25.20 Figure 25.38 Address delay time 2 Address delay time 3 Address setup time Chip enable setup time Address hold time BS delay time tAD2 tAD3 tAS tCS tAH tBSD 1/2tcyc 1/2tcyc 0 0 0 -- 1/2tcyc + 13 1/2tcyc + 13 -- -- -- 13 ns ns ns ns ns ns CS delay time 1 tCSD1 0 or 1*2 13 ns CS delay time 2 Read write delay time 1 tCSD2 tRWD1 1/2tcyc 0 or 1* 2 1/2tcyc + 13 13 ns ns Read write delay time 2 Read strobe delay time tRWD2 tRSD 1/2tcyc 1/2tcyc 1/2tcyc + 13 1/2tcyc + 13 ns ns Read data setup time 1 tRDS1 1/2tcyc+ 13 -- ns Read data setup time 2 tRDS2 8 -- ns Read data setup time 3 Read data setup time 4 tRDS3 tRDS4 1/2tcyc + 13 -- 1/2tcyc + 13 -- ns ns Rev. 3.00 Jun. 18, 2008 Page 1080 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics B = 66.66 MHz*4 Item Read data hold time 1 Symbol tRDH1 Min. 0 Max. -- Unit ns Figure Figures 25.12 to 25.16, 25.18, 25.19, 25.40 to 25.43 Figures 25.17, 25.21 to 25.24, 25.29 to 25.31 Figure 25.20 Figure 25.38 Figures 25.12 to 25.16, 25.18, 25.40, 25.41 Figure 25.19 Figures 25.12 to 25.19, 25.40 to 25.43 Figures 25.25 to 25.28, 25.32 to 25.34 Figure 25.38 Figures 25.12 to 25.19, 25.40 to 25.43 Figures 25.25 to 25.28, 25.32 to 25.34 Figure 25.38 Figures 25.12, 25.16, 25.40, 25.42 Figures 25.13 to 25.20, 25.41, 25.43 Figures 25.13 to 25.20, 25.41, 25.43 Figures 25.21 to 25.37 Figures 25.38, 25.39 Read data hold time 2 tRDH2 2 -- ns Read data hold time 3 Read data hold time 4 Write enable delay time 1 tRDH3 tRDH4 tWED1 0 1/2tcyc + 6 1/2tcyc -- -- 1/2tcyc + 13 ns ns ns Write enable delay time 2 Write data delay time 1 tWED2 tWDD1 -- -- 13 13 ns ns Write data delay time 2 tWDD2 -- 13 ns Write data delay time 3 Write data hold time 1 tWDD3 tWDH1 -- 1 1/2tcyc + 13 -- ns ns Write data hold time 2 tWDH2 1 -- ns Write data hold time 3 Write data hold time 4 WAIT setup time WAIT hold time RAS delay time 1 RAS delay time 2 tWDH3 tWDH4 tWTS tWTH tRASD1 tRASD2 1/2tcyc 0 -- -- ns ns ns ns ns ns 1/2tcyc + 7.5 -- 1/2tcyc + 3.5 -- 1*3 1/2tcyc 13 1/2tcyc + 13 Rev. 3.00 Jun. 18, 2008 Page 1081 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics B = 66.66 MHz*4 Item CAS delay time 1 CAS delay time 2 DQM delay time 1 DQM delay time 2 CKE delay time 1 CKE delay time 2 AH delay time Multiplexed address delay time Address setup time for AH DACK, TEND delay time Symbol tCASD1 tCASD2 tDQMD1 tDQMD2 tCKED1 tCKED2 tAHD tMAD Min. 1* 3 Max. 13 1/2tcyc + 13 13 1/2tcyc + 13 13 1/2tcyc + 13 1/2tcyc + 13 13 -- -- Refer to peripheral modules 13 1/2tcyc + 13 1/2tcyc + 13 Unit ns ns ns ns ns ns ns ns ns ns ns Figure Figures 25.21 to 25.37 Figures 25.38, 25.39 Figures 25.21 to 25.34 Figures 25.38, 25.39 Figure 25.36 Figure 25.39 Figure 25.16 Figure 25.16 Figure 25.16 1/2tcyc 1*3 1/2tcyc 1* 3 1/2tcyc 1/2tcyc -- 1 1/2tcyc - 2 Refer to peripheral modules 0 -- -- Multiplexed address hold time tMAH tAVVH tDACD Figures 25.12 to 25.34, 25.38, 25.40 to 25.43 Figure 25.17 Figures 25.42, 25.43 Figures 25.42, 25.43 FRAME delay time ICIORD delay time ICIOWR delay time tFMD tICRSD tICWSD ns ns ns Notes: 1. The maximum value (fmax) of B (external bus clock) depends on the number of wait cycles and the system configuration of your board. 2. Values when the SDRAM is used. Be sure to set ACSWR in clock mode 2. For details, see sections from 8.4.8, AC Characteristics Switching Register (ACSWR), to 8.4.10, Sequence to Write to ACSWR. 3. Be sure to set ACSWR in clock mode 2. For details, see sections from 8.4.8, AC Characteristics Switching Register (ACSWR), to 8.4.10, Sequence to Write to ACSWR. 4. 1/2 tcyc indicated in minimum and maximum values for the item of delay, setup, and hold times represents a half cycle from the rising edge with a clock. That is, 1/2 tcyc describes a reference of the falling edge with a clock. Rev. 3.00 Jun. 18, 2008 Page 1082 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics T1 T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tCS tRWD1 tRWD1 RD/WR tRSD tRSD tAH RD Read D31 to D0 tRDS1 tRDH1 tWED1 tWED1 tAH WEn Write D31 to D0 tWDD1 tWDH4 tWDH1 tBSD tBSD BS tDACD tDACD DACKn TENDn* Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.12 Basic Bus Timing for Normal Space (No Wait) Rev. 3.00 Jun. 18, 2008 Page 1083 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics T1 Tw T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tCS tRWD1 tRWD1 RD/WR tRSD tRSD tAH RD Read D31 to D0 tRDS1 tRDH1 tWED1 tWED1 tAH WEn Write D31 to D0 tWDD1 tWDH1 tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.13 Basic Bus Timing for Normal Space (One Software Wait Cycle) Rev. 3.00 Jun. 18, 2008 Page 1084 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics T1 TwX T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tCS tRWD1 tRWD1 RD/WR tRSD tRSD tAH RD Read D31 to D0 tRDS1 tRDH1 tWED1 tWED1 tAH WEn Write D31 to D0 tWDD1 tWDH1 tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTS tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.14 Basic Bus Timing for Normal Space (One External Wait Cycle) Rev. 3.00 Jun. 18, 2008 Page 1085 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics T1 Tw T2 Taw T1 Tw T2 Taw CKIO tAD1 tAD1 tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 tAS tCSD1 tCSD1 CSn tRWD1 tCS tRWD1 tCS tRWD1 tRWD1 RD/WR tRSD tRSD tAH tRSD tRSD tAH RD tRDH1 tRDS1 tRDS1 tRDH1 Read D15 to D0 tWED1 tWED1 tAH tWED1 tWED1 tAH WEn Write D15 to D0 tWDD1 tWDH1 tWDD1 tWDH1 tBSD tBSD tBSD tBSD BS tDACD tDACD tDACD tDACD DACKn TENDn* tWTH tWTS tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.15 Basic Bus Timing for Normal Space (One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle) Rev. 3.00 Jun. 18, 2008 Page 1086 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Ta1 Ta2 Ta3 T1 Tw Tw T2 CKIO tAD1 tAD1 A25 to A0 tCSD1 tCSD1 CS5 tRWD1 tRWD1 RD/WR tAHD tAHD tAHD AH tRSD tRSD tRDH1 tMAD tMAH Address tAVVH tRDS1 Data RD Read D15 to D0 tWED1 tWED1 WE1, WE0 Write D15 to D0 tBSD tBSD tAVVH tMAD Address tWDD1 tMAH Data tWDH4 tWDH1 BS tWTH tWTS tWTH tWTS WAIT tDACD tDACD DACKn* tDACD tDACD TENDn* Note: * Waveforms for DACKn and TENDn are when active low is specified. Figure 25.16 MPX-I/O Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) Rev. 3.00 Jun. 18, 2008 Page 1087 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tm1 Tmd1w Tmd1 CKIO tAD1 tAD1 A25 to A0 tCSD1 tCSD1 CS6 tRWD1 tRWD1 RD/WR tFMD tFMD tFMD FRAME tWDD1 tWDH1 tRDS2 Read D31 to D0 tWDD1 tWDD1 tWDH1 tWDH1 tRDH2 Write D31 to D0 tBSD tBSD BS tDACD tDACD DACKn* tDACD tDACD TENDn* tWTH WAIT tWTS RD WEn Note: * Waveforms for DACKn and TENDn are when active low is specified. Figure 25.17 Burst MPX-I/O Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait Cycle) Rev. 3.00 Jun. 18, 2008 Page 1088 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Th T1 Twx T2 Tf CKIO tAD1 tAD1 A25 to A0 tCSD1 tCSD1 CSn tWED1 tWED1 WEn tRWD1 tRWD1 RD/WR tRSD tRSD Read RD tRDS1 tRDH1 D31 to D0 tRWD1 tRWD1 RD/WR tWDD1 Write D31 to D0 tBSD tBSD tWDH1 BS tDACD tDACD DACKn TENDn* tWTH tWTH WAIT tWTS tWTS Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.18 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control)) Rev. 3.00 Jun. 18, 2008 Page 1089 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Th T1 Twx T2 Tf CKIO tAD1 tAD1 A25 to A0 tCSD1 tCSD1 CSn tWED2 tWED2 WEn tRWD1 RD/WR tRSD tRSD Read RD tRDS1 tRDH1 D31 to D0 tRWD1 tRWD1 tRWD1 RD/WR Write D31 to D0 tBSD tBSD tWDD1 tWDH1 BS tDACD tDACD DACKn TENDn* tWTH tWTH WAIT tWTS tWTS Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.19 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control)) Rev. 3.00 Jun. 18, 2008 Page 1090 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics T1 Tw Twx T2B Twb T2B CKIO tAD1 tAD2 tAD2 tAD1 A25 to A0 tCSD1 tAS tCSD1 CSn tRWD1 tRWD1 RD/WR tRSD tRSD RD tRDS3 tRDH3 tRDS3 tRDH3 D31 to D0 WEn tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTH WAIT tWTS tWTS Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.20 Burst ROM Read Cycle (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst) Rev. 3.00 Jun. 18, 2008 Page 1091 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Tc1 Tcw Td1 Tde CKIO tAD1 tAD1 Row address Column address tAD1 A25 to A0 tAD1 tAD1 tAD1 *1 A12/A11 READA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.21 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1092 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Trw Tc1 Tcw Td1 Tde Tap CKIO tAD1 tAD1 Row address Column address tAD1 A25 to A0 tAD1 tAD1 tAD1 A12/A11* 1 READA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.22 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1093 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Td1 Tr Tc1 Tc2 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 tAD1 Column address tAD1 tAD1 (1 to 4) tAD1 A25 to A0 Row address tAD1 tAD1 READ command tAD1 READA command tAD1 A12/A11 *1 tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.23 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1094 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Td1 Tr Trw Tc1 Tc2 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 Row address tAD1 Column address tAD1 tAD1 (1 to 4) tAD1 A25 to A0 tAD1 tAD1 tAD1 tAD1 A12/A11 *1 READ command READA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1095 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Tc1 Trwl CKIO tAD1 tAD1 Row address Column address tAD1 A25 to A0 tAD1 tAD1 WRITA command tAD1 *1 A12/A11 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.25 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1096 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Trw Trw Tc1 Trwl CKIO tAD1 tAD1 Row address Column address tAD1 A25 to A0 tAD1 tAD1 WRITA command tAD1 A12/A11 *1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.26 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1097 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 tAD1 Row address tAD1 Column address tAD1 tAD1 tAD1 A25 to A0 tAD1 tAD1 WRIT command tAD1 WRITA command tAD1 A12/A11 *1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.27 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1098 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 tAD1 Row address tAD1 Column address tAD1 tAD1 tAD1 A25 to A0 tAD1 tAD1 WRIT command tAD1 WRITA command tAD1 A12/A11 *1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1099 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Td1 Tr Tc1 Td2 Tc4 Td3 Td4 Tde Tc2 Tc3 CKIO tAD1 tAD1 tAD1 Column address tAD1 tAD1 tAD1 A25 to A0 Row address tAD1 tAD1 READ command tAD1 *1 A12/A11 tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.29 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1100 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Td1 Tc1 Tc2 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 tAD1 A25 to A0 Column address tAD1 tAD1 READ command A12/A11 *1 tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.30 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1101 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Td1 Tp Trw Tr Tc1 Tc2 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 Row address tAD1 Column address tAD1 tAD1 tAD1 A25 to A0 tAD1 tAD1 tAD1 READ command tAD1 *1 A12/A11 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, CAS Latency 2, WTRCD = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1102 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 Row address tAD1 Column address tAD1 tAD1 tAD1 A25 to A0 tAD1 tAD1 WRIT command tAD1 *1 A12/A11 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.32 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1103 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tnop Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 Column address tAD1 tAD1 tAD1 A25 to A0 tAD1 tAD1 WRIT command tAD1 A12/A11 *1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.33 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle, TRWL = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1104 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tp Tpw Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 Row address tAD1 tAD1 tAD1 tAD1 A25 to A0 Column address tAD1 tAD1 tAD1 WRIT command tAD1 A12/A11 *1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1105 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trc CKIO tAD1 tAD1 A25 to A0 tAD1 tAD1 A12/A11 *1 tCSD1 tCSD1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L DQMxx (Hi-Z) D31 to D0 BS (High) CKE DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.35 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle, WTRC = 3 Cycles) Rev. 3.00 Jun. 18, 2008 Page 1106 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trc CKIO tAD1 tAD1 A25 to A0 tAD1 tAD1 A12/A11 *1 tCSD1 tCSD1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 RASU/L tCASD1 tCASD1 CASU/L DQMxx (Hi-Z) D31 to D0 BS tCKED1 tCKED1 CKE DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.36 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1107 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trr Trc Trc Tmw Tde CKIO PALL tAD1 REF REF MRS tAD1 tAD1 A25 to A0 tAD1 tAD1 A12/A11 *1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 RASU/L tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 CASU/L DQMxx (Hi-Z) D31 to D0 BS CKE DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.37 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle) Rev. 3.00 Jun. 18, 2008 Page 1108 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tr Tc Td1 Tde Tap Tr Tc Tnop Trw1 Tap CKIO tAD3 tAD3 Row address tAD3 Column address tAD3 tAD3 Row address Column address tAD3 A25 to A0 tAD3 tAD3 tAD3 READA Command tAD3 tAD3 tAD3 WRITA Command tAD3 *1 A12/A11 tCSD2 tCSD2 tCSD2 tCSD2 CSn tRWD2 tRWD2 tRWD2 RD/WR tRASD2 tRASD2 tRASD2 tRASD2 RASU/L tCASD2 tCASD2 tCASD2 tCASD2 tCASD2 CASU/L tDQMD2 tDQMD2 tDQMD2 tDQMD2 DQMxx tRDS4 tRDH4 tWDD3 tWDH3 D31 to D0 tBSD tBSD tBSD tBSD BS (High) (High) CKE tDACD tDACD tDACD tDACD DACKn TENDn *2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.38 Synchronous DRAM Access Timing in Low-Frequency Mode (Auto-Precharge, TRWL = 2 Cycles) Rev. 3.00 Jun. 18, 2008 Page 1109 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tp Tpw Trr Trc Trc Trc CKIO tAD3 tAD3 A25 to A0 tAD3 tAD3 A12/A11 *1 tCSD2 tCSD2 tCSD2 tCSD2 CSn tRWD2 tRWD2 RD/WR tRASD2 tRASD2 tRASD2 tRASD2 RASU/L tCASD2 tCASD2 tCASD2 CASU/L tDQMD2 DQMxx D31 to D0 (Hi-Z) BS tCKED2 tCKED2 CKE DACKn TENDn *2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 25.39 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode (WTRP = 2 Cycles) Rev. 3.00 Jun. 18, 2008 Page 1110 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 CKIO tAD1 tAD1 A25 to A0 tCSD1 tCSD1 CExx tRWD1 tRWD1 RD/WR tRSD tRSD RD Read tRDH1 tRDS1 D15 to D0 tWED1 tWED1 WE Write tWDH4 tWDD1 tWDH1 D15 to D0 tBSD tBSD BS tDACD DACKn TENDn* tDACD Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.40 PCMCIA Memory Card Bus Cycle (TED = 0 Cycle, TEH = 0 Cycle, No Wait) Rev. 3.00 Jun. 18, 2008 Page 1111 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO tAD1 tAD1 A25 to A0 tCSD1 tCSD1 CExx tRWD1 tRWD1 RD/WR tRSD tRSD RD Read D15 to D0 tRDH1 tRDS1 tWED1 tWED1 WE Write D15 to D0 tWDD1 tWDH1 tBSD tBSD BS tDACD DACKn TENDn* tDACD tWTH tWTS tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.41 PCMCIA Memory Card Bus Cycle (TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, Hardware Wait Cycle 1) Rev. 3.00 Jun. 18, 2008 Page 1112 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tpcm1 CKIO tAD1 A25 to A0 tCSD1 CExx tRWD1 RD/WR tICRSD ICIORD Read D15 to D0 tICWSD ICIOWR Write D15 to D0 tBSD BS tDACD DACKn TENDn* tWDD1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 tAD1 tCSD1 tRWD1 tICRSD tRDH1 tRDS1 tICWSD tWDH4 tWDH1 tBSD tDACD Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.42 PCMCIA I/O Card Bus Cycle (TED = 0 Cycle, TEH = 0 Cycle, No Wait) Rev. 3.00 Jun. 18, 2008 Page 1113 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Tpcm0 CKIO tAD1 A25 to A0 tCSD1 CExx tRWD1 RD/WR Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w tAD1 tCSD1 tRWD1 tICRSD ICIORD Read D15 to D0 tICWSD ICIOWR Write D15 to D0 tBSD BS tDACD DACKn TENDn* tWTH tWTS WAIT tWTH tWTS tBSD tWDD1 tICRSD tRDH1 tRDS1 tICWSD tWDH1 tDACD Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 25.43 PCMCIA I/O Card Bus Cycle (TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, Hardware Wait Cycle 1) Rev. 3.00 Jun. 18, 2008 Page 1114 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.4 UBC Trigger Timing Table 25.9 UBC Trigger Timing Conditions: VCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item UBCTRG delay time Symbol tUBCTGD Min. -- Max. 14 Unit ns Figure Figure 25.44 CKIO tUBCTGD UBCTRG Figure 25.44 UBC Trigger Timing 25.4.5 DMAC Module Timing Table 25.10 DMAC Module Timing Conditions: VCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item DREQ setup time DREQ hold time DACK, TEND delay time Symbol tDRQS tDRQH tDACD Min. 15 15 0 Max. -- -- 13 Figure 25.46 Unit ns Figure Figure 25.45 CKIO tDRQS tDRQH DREQn Note: n = 0 to 3 Figure 25.45 DREQ Input Timing Rev. 3.00 Jun. 18, 2008 Page 1115 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics CKIO t DACD t DACD TENDn DACKm Notes: n = 0, 1 m = 0 to 3 Figure 25.46 DACK, TEND Output Timing Rev. 3.00 Jun. 18, 2008 Page 1116 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.6 MTU2, MTU2S Module Timing Table 25.11 MTU2, MTU2S Module Timing Conditions: VCC = 1.15 V to 1.35 V, PVCC = AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Output compare output delay time Input capture input setup time Timer input setup time Symbol tTOCD tTICS tTCKS tTCKWH/L tTCKWH/L Min. tcyc/2 + 20 tcyc + 20 1.5 2.5 2.5 Max. 100 Unit ns ns ns tpcyc tpcyc tpcyc Figure 25.48 Figure Figure 25.47 Timer clock pulse width (single edge) tTCKWH/L Timer clock pulse width (both edges) Timer clock pulse width (phase counting mode) Note: tpcyc indicates peripheral clock (P) cycle. CKIO tTOCD Output compare output tTICS Input capture input Figure 25.47 MTU2, MTU2S Input/Output Timing CKIO tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 25.48 MTU2, MTU2S Clock Input Timing Rev. 3.00 Jun. 18, 2008 Page 1117 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.7 POE2 Module Timing Table 25.12 POE2 Module Timing Conditions: VCC = 1.15 V to 1.35 V, PVCC = AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item POE input setup time POE input pulse width Symbol tPOES tPOEW Min. tcyc/2 + 10 1.5 Max. -- -- Unit ns tpcyc Figure Figure 25.49 Note: tpcyc indicates peripheral clock (P) cycle. CKIO tPOES POEn input tPOEW Figure 25.49 POE2 Input/Output Timing 25.4.8 Watchdog Timer Timing Table 25.13 Watchdog Timer Timing Conditions: PVCC = 3.0 V to 3.6 V, VCC = 1.15 V to 1.35 V, AVCC = 3.0 V to 3.6 V, PVSS = VSS = AVSS = 0 V, Ta = -20C to +85C Item WDTOVF delay time Symbol tWOVD Min. -- Max. 100 Unit ns Figure Figure 25.50 CKIO tWOVD tWOVD WDTOVF Figure 25.50 Watchdog Timer Timing Rev. 3.00 Jun. 18, 2008 Page 1118 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.9 SCIF Module Timing Table 25.14 SCIF Module Timing Conditions: PVCC = 3.0 V to 3.6 V, VCC = 1.15 V to 1.35 V, AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Symbol Min. 12 4 tSCKr tSCKf tSCKW tTXD tRXS tRXH -- -- 0.4 -- 4tpcyc + 15 1tpcyc + 15 Max. -- -- 1.5 1.5 0.6 3tpcyc + 15 -- -- Unit tpcyc tpcyc tpcyc tpcyc tScyc ns ns ns Figure 25.52 Figure Figure 25.51 Input clock cycle (clocked synchronous) tScyc (asynchronous) Input clock rise time Input clock fall time Input clock width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) Note: tpcyc indicates peripheral clock (P) cycle. tSCKW tSCKr tSCKf SCK tScyc Figure 25.51 SCK Input Clock Timing tScyc SCK (input/output) TxD (data transmit) tRXS tRXH tTXD RxD (data receive) Figure 25.52 SCIF Input/Output Timing in Clocked Synchronous Mode Rev. 3.00 Jun. 18, 2008 Page 1119 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.10 IIC3 Module Timing Table 25.15 I2C Bus Interface 3 Timing Conditions: VCC = 1.15 V to 1.35 V, AVCC = PVCC = 3.0 V to 3.6 V, VSS = AVSS = PVSS = 0 V, Ta = -20C to +85C Specifications Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse removal time* 2 Symbol tSCL tSCLH tSCLL tSr tSf tSP Test Conditions Min. 12tpcyc* + 600 3tpcyc*1 + 300 5tpcyc*1 + 300 -- -- -- 1 Typ. -- -- -- -- -- -- Max. -- -- -- 300 300 1, 2 Unit ns ns ns ns ns tpcyc*1 tpcyc*1 tpcyc*1 tpcyc*1 tpcyc*1 ns ns pF ns Figure Figure 25.53 SDA input bus free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load SCL, SDA output fall time*3 tBUF tSTAH tSTAS 5 3 3 -- -- -- -- -- -- tSTOS tSDAS tSDAH Cb tSf 3 1tpcyc*1 + 20 0 0 PVCC = 3.0 to 3.6 V -- -- -- -- -- -- -- -- -- 400 250 Notes: 1. tpcyc indicates peripheral clock (P) cycle. 2. Depends on the value of NF2CYC. 3. Indicates the I/O buffer characteristic. Rev. 3.00 Jun. 18, 2008 Page 1120 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics SDA tBUF VIH VIL tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf tSCLL tSCL [Legend] S: Start condition P: Stop condition Sr: Start condition for retransmission Sr* tSr tSDAH tSDAS P* Figure 25.53 I2C Bus Interface 3 Input/Output Timing 25.4.11 A/D Trigger Input Timing Table 25.16 A/D Trigger Input Timing Conditions: VCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Module A/D converter Item Trigger input setup time B:P clock ratio = 1:1 B:P clock ratio = 2:1 B:P clock ratio = 4:1 Symbol tTRGS Min. 17 tcyc + 17 3 x tcyc + 17 Max. -- -- -- Unit ns Figure Figure 25.54 CKIO tTRGS ADTRG Figure 25.54 A/D Converter External Trigger Input Timing Rev. 3.00 Jun. 18, 2008 Page 1121 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.12 I/O Port Timing Table 25.17 I/O Port Timing Conditions: VCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Output data delay time Input data setup time Input data hold time Symbol tPORTD tPORTS tPORTH Min. -- 100 100 Max. 100 -- -- Unit ns Figure Figure 25.55 CKIO tPORTS tPORTH Port (read) tPORTD Port (write) Figure 25.55 I/O Port Timing Rev. 3.00 Jun. 18, 2008 Page 1122 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.13 H-UDI Related Pin Timing Table 25.18 H-UDI Related Pin Timing Conditions: VCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item TCK cycle time TCK high pulse width TCK low pulse width TDI setup time TDI hold time TMS setup time TMS hold time TDO delay time Note: * Symbol tTCKcyc tTCKH tTCKL tTDIS tTDIH tTMSS tTMSH tTDOD Min. 50* 0.4 0.4 10 10 10 10 -- Max. -- 0.6 0.6 -- -- -- -- 16 Unit ns tTCKcyc tTCKcyc ns ns ns ns ns Figure 25.57 Figure Figure 25.56 Should be greater than the peripheral clock (P) cycle time. tTCKcyc tTCKH tTCKL VIH VIH 1/2 PVcc VIL VIL VIH 1/2 PVcc Figure 25.56 TCK Input Timing Rev. 3.00 Jun. 18, 2008 Page 1123 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics tTCKcyc TCK tTDIS tTDIH TDI tTMSS tTMSH TMS tTDOD TDO change timing after switch command setting TDO tTDOD Initial value Figure 25.57 H-UDI Data Transfer Timing Rev. 3.00 Jun. 18, 2008 Page 1124 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.4.14 AC Characteristics Measurement Conditions * I/O signal reference level: PVCC/2 (PVCC = 3.0 to 3.6 V, VCC = 1.15 to 1.35 V) * Input pulse level: PVSS to 3.0 V (where RES, MRES, NMI, MD2, MD0, MD_CLK2, MD_CLK0, ASEMD, TRST, and Schmitt trigger input pins are within PVSS to PVCC) * Input rise and fall times: 1 ns IOL LSI output pin DUT output CL VREF IOH Notes: 1. CL is the total value that includes the capacitance of measurement tools. Each pin is set as follows: 30pF: CKIO, RASU, RASL, CASU, CASL, CS0 to CS8, and BACK 50pF: All other pins IOL and IOH are shown in table 25.3. 2. Figure 25.58 Output Load Circuit Rev. 3.00 Jun. 18, 2008 Page 1125 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.5 A/D Converter Characteristics Table 25.19 lists the A/D converter characteristics. Table 25.19 A/D Converter Characteristics Conditions: VCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVcc - 0.3 V AVcc PVcc, AVref = 3.0 V to AVCC, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Reference values Min. 10 3.9 -- -- -- -- -- -- -- Typ. 10 -- -- -- -- -- -- -- -- Max. 10 -- 20 5 3.0* 2.0* 2.0* 0.5* 4.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 3.00 Jun. 18, 2008 Page 1126 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics 25.6 D/A Converter Characteristics Table 25.20 lists the D/A converter characteristics. Table 25.20 D/A Converter Characteristics Conditions: VCC = 1.15 V to 1.35 V, PVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVcc - 0.3 V AVcc PVcc, AVref = 3.0 V to AVCC, VSS = PVSS = AVSS = 0 V, Ta = -20C to +85C Item Resolution Conversion time Absolute accuracy Min. 8 10 -- -- Typ. 8 -- 2.0 -- Max. 8 -- 3.0 2.5 Unit bits s LSB LSB Load capacitance 20 pF Load resistance 2 M Load resistance 4 M Test Conditions Rev. 3.00 Jun. 18, 2008 Page 1127 of 1160 REJ09B0191-0300 Section 25 Electrical Characteristics Rev. 3.00 Jun. 18, 2008 Page 1128 of 1160 REJ09B0191-0300 Appendix Appendix A. Pin States Pin States Pin Function Reset State Power-On* 7 Table A.1 Pin State Power-Down State Bus Mastership Release O/Z* I O O I Z I I O I L I I I I I O 2 Area 0 Data Bus Width Type Clock Pin Name CKIO (clock mode 2) CKIO (clock mode 7) XTAL (clock mode 2) XTAL 6 (clock mode 7)* EXTAL (clock mode 2) EXTAL 6 (clock mode 7)* System control RES MRES WDTOVF BREQ BACK Operating mode control Interrupt MD2, MD0 MD_CLK2, MD_CLK0 NMI IRQ7 to IRQ0 PINT7 to PINT0 IRQOUT 8 Bits 16 Bits 32 Bits O I O O I Z I H I I I Manual O I O O I Z I I O I O I I I I I O Software Standby O/Z* I L L I Z I I H Z Z I I I I Z H/Z* 1 2 Sleep O I O O I Z I I O I O I I I I I O Rev. 3.00 Jun. 18, 2008 Page 1129 of 1160 REJ09B0191-0300 Appendix Pin Function Reset State Power-On* 7 Pin State Power-Down State Bus Mastership Release Z Z Z Z Z Z Z Z I Z Z Area 0 Data Bus Width Type Address bus Pin Name A25 to A21 A20 to A2 A1 A0 Data bus D31 to D16 D15 to D8 D7 to D0 Bus control WAIT IOIS16 CS0 CS8 to CS1, CE1A, CE1B, CE2A, CE2B BS RD RD/WR WE3/DQMUU/ ICIOWR/AH, WE2/DQMUL/ ICIORD, WE1/DQMLU/WE, WE0/DQMLL FRAME RASU, RASL CASU, CASL CKE REFOUT O O Z H O Z O Z 8 Bits 16 Bits 32 Bits O Manual O O O O I/O I/O I/O I I O O Software Standby O/Z* O/Z* 3 Sleep O O O O I/O I/O I/O I I 3 O/Z* O/Z* Z Z Z Z Z H/Z* H/Z* 3 3 3 O O 3 H O O O O H/Z* H/Z* H/Z* H/Z* 3 O O O O Z Z Z Z 3 3 3 O O H/Z* 3 O O Z O/Z* 2 O/Z* 2 O/Z* H/Z* 2 O O O/Z* O 2 1 Rev. 3.00 Jun. 18, 2008 Page 1130 of 1160 REJ09B0191-0300 Appendix Pin Function Reset State Power-On* 7 Pin State Power-Down State Bus Mastership Release I O O I I/O I/O I/O I/O I/O I I/O I/O Area 0 Data Bus Width Type DMAC Pin Name DREQ3 to DREQ0 DACK3 to DACK0 TEND1, TEND0 MTU2 TCLKA, TCLKB, TCLKC, TCLKD TIOC0A* , TIOC0B* , 5 5 TIOC0C* , TIOC0D* TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3B* , 5 TIOC3C, TIOC3D* TIOC4A* , TIOC4B* , 5 5 TIOC4C* , TIOC4D* TIC5U, TIC5V, TIC5W MTU2S TIOC3AS, TIOC3BS* , 5 TIOC3CS, TIOC3DS* TIOC4AS* , 5 TIOC4BS* , 5 TIOC4CS* , 5 TIOC4DS* TIC5US, TIC5VS, TIC5WS POE2 SCIF POE8 to POE0 SCK3 to SCK0 RxD3 to RxD0 TxD3 to TxD0 RTS3 CTS3 A/D converter AN7 to AN0 ADTRG 5 5 5 5 5 5 5 8 Bits 16 Bits 32 Bits Manual I O O I I/O I/O I/O I/O I/O I I/O I/O Software Standby Z O/Z* 1 Sleep I O O I O/Z* Z K/Z* 1 1 I/O I/O I/O I/O I/O I K/Z* K/Z* 1 1 K/Z* K/Z* Z K/Z* 1 1 1 I/O I/O K/Z* 1 Z I I I/O I O/Z I/O I/O I I Z Z K/Z* Z O/Z* K/Z* 1 1 I I I/O I O/Z I/O I/O I I I I I/O I O/Z I/O I/O I I 1 K/Z* Z Z 1 Rev. 3.00 Jun. 18, 2008 Page 1131 of 1160 REJ09B0191-0300 Appendix Pin Function Reset State Power-On* 7 Pin State Power-Down State Bus Mastership Release O I/O I/O I Z Z I I I 4 Area 0 Data Bus Width Type D/A converter IIC3 Pin Name DA1, DA0 SCL SDA Emulator AUDSYNC* AUDCK* 8 8 8 Bits 16 Bits 32 Bits Z I Manual O I/O I/O I Z Z I I I Software Standby O Z Z I Z Z I I I Sleep O I/O I/O I Z Z I I I AUDATA3 to 8 AUDATA0* ASEMD ASEBCK* 8 Z 8 ASEBRKAK/ASEBRK* TRST TCK TDI TDO TMS UBC I/O port UBCTRG PA25 to PA16, PA13 to PA11, PA9 to PA0 PB9, PB5, PB4 PB3, PB2 PC1 PC0 PD31, PD30, 5 PD29 to PD24* , PD23 to PD16 PD15 to PD11* , 5 PD10, PD9* , PD8 5 Z I I I O/Z* I Z 4 O/Z* I O I/O 4 O/Z* I 4 O/Z* I O/Z* I O I/O 4 O/Z* K/Z* 1 O I/O 1 Z Z Z Z Z I/O I I/O I/O I/O K/Z* Z K/Z* K/Z* K/Z* 1 I/O I I/O I I/O I/O I/O 1 I/O I/O I/O 1 1 Z I/O K/Z* 1 I/O I/O Rev. 3.00 Jun. 18, 2008 Page 1132 of 1160 REJ09B0191-0300 Appendix Pin Function Reset State Power-On* 7 Pin State Power-Down State Bus Mastership Release I/O Area 0 Data Bus Width Type I/O port Pin Name PE16, PE15 to PE11* , 5 PE10, PE9* , PE8 to PE0 PF7 to PF0 5 8 Bits 16 Bits 32 Bits Z Manual I/O Software Standby K/Z* 1 Sleep I/O Z I Z I I [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. Controlled by the HIZ bit in standby control register 3 (STBCR3) (see section 22, Power-Down Modes). 2. Controlled by the HIZCNT bit in the common control register of the BSC (see section 8, Bus State Controller (BSC)). 3. Controlled by the HIZMEM bit in the common control register of the BSC (see section 8, Bus State Controller (BSC)). 4. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state. 5. High-impedance control through POE2 (see section 12, Port Output Enable 2 (POE2)). 6. The EXTAL pin must be fixed (pulled up/pulled down/connected to power supply/connected to ground) and the XTAL pin must be open. 7. Power-on reset by low-level input to the RES pin. The pin states after a power-on reset by the H-UDI reset assert command or WDT overflow are the same as the initial pin states at normal operation (see section 19, Pin Function Controller (PFC)). 8. These are the pin states in product chip mode (ASEMD = H). See the Emulation Manual for the pin states in ASE mode (ASEMD = L). Rev. 3.00 Jun. 18, 2008 Page 1133 of 1160 REJ09B0191-0300 Appendix B. Product Lineup Product Lineup Product Code R5S72060W200FPV Package LQFP2424-176Cu (FP-176CV) Table B.1 Product Type SH7206 Rev. 3.00 Jun. 18, 2008 Page 1134 of 1160 REJ09B0191-0300 Appendix C. Package Dimensions 26.0 0.2 24 132 133 89 88 Unit: mm 26.0 0.2 176 1 *0.22 0.05 0.20 0.04 44 45 1.70 Max 0.5 0.08 M *0.17 0.05 0.15 0.04 1.40 1.25 1.0 0 - 8 0.10 0.05 0.08 0.5 0.1 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-176CV -- Conforms 1.9 g Figure C.1 Package Dimensions Rev. 3.00 Jun. 18, 2008 Page 1135 of 1160 REJ09B0191-0300 Appendix Rev. 3.00 Jun. 18, 2008 Page 1136 of 1160 REJ09B0191-0300 Main Revisions and Additions in This Edition Item 1.1 SH7206 Features Table 1.1 SH7206 Features Page Revision (See Manual for Details) 3 Specification of Cache memory amended. * 128-entry/way, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache Way lock function available (only for operand cache); ways 2 and 3 can be locked * 5 Specification of Multi-function timer pulse unit 2 (MTU2) amended. * Pulse output modes One shot, Toggle, PWM, complementary PWM, and reset-synchronized PWM modes 1.4 Pin Functions Table 1.2 Pin Functions 10 Table amended. Classification Symbol I/O I Name ASE mode Fuction If a low level is input at the ASEMD pin while the RES pin is asserted, ASE mode is entered; if a high level i s input, product chip mode is entered. In ASE mode, the emulator function is enabled. When this function is not in use, fix it high. Operating mode ASEMD control 2.1.3 System Registers 32 Description amended. PC points four bytes ahead of the current instruction and controls the flow of the processing. (3) Program Counter (PC) 32 Description amended. PC points four bytes ahead of the instruction being executed. 3.2 Input/Output Pins Table 3.1 Pin Configuration and Functions of the Clock Pulse Generator 73 Function (Clock Operating Mode 7) of Crystal input/output pins (clock input pins) amended. (Before) Pull up this pin. (After) Fix (pull up/pull down/connect to power supply/connect to ground) this pin. Rev. 3.00 Jun. 18, 2008 Page 1137 of 1160 REJ09B0191-0300 Item 3.3 Clock Operating Modes Page Revision (See Manual for Details) 74 Description amended. * Mode 7 ... For reduced current and hence power consumption, fix (pull up/pull down/connect to power supply/connect to ground) the EXTAL pin and open the XTAL pin when the LSI is used in mode 7. 3.5.1 Changing the Multiplication Rate 83 Description amended. A PLL settling time is required when the multiplication rate of oscillation circuit 1 is changed. The on-chip WDT counts the settling time. The oscillation stabilization time becomes the same time as that of recovery from the software standby mode. 3.6.1 Note on Inputting External Clock 85 Description amended. Figure 3.2 is an example of connecting the external clock input. When putting the XTAL pin in open state, make sure the parasitic capacitance is less than or equal to 10 pF. To stably input the external clock with enough PLL stabilizing time at power on or releasing the standby, wait longer than the oscillation stabilizing time. 3.6.5 Note on Using a PLL Oscillation Circuit 86 Description amended. In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. In clock operating mode 7, the EXTAL pin is pulled up and the XTAL pin is left open. Since the analog power supply pins of the PLL ... 4.1.2 Exception Handling Operations Table 4.2 Timing of Exception Source Detection and Start of Exception Handling 4.2.4 Manual Reset (1) Manual Reset by Means of MRES Pin 89 Table amended. Exception Instructions Source Integer division exceptions 96 Description amended. When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without fail, the MRES pin should be kept at the low level for at least 20-tcyc. In the manual reset state ... Rev. 3.00 Jun. 18, 2008 Page 1138 of 1160 REJ09B0191-0300 Item 4.2.4 Manual Reset (3) Note on Manual Reset Page Revision (See Manual for Details) 96 Subheading added and description moved from (2). When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception handling will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the interval which MRES pin driven at low level or the fixed internal manual reset interval cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception handling is not executed. 98 Description amended. When an address error occurs, the bus cycle in which the address error occurred ends.* When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: ... Note: * In the case of an address error caused by instruction fetching when data is read or written, if the bus cycle on which the address error occurred is not completed by the end of the operations described above, the CPU will recommence address error exception processing until the end of that bus cycle. 4.3.2 Address Error Exception Handling 4.6.5 Integer Division Exceptions 4.8 Integer Division Exceptions Table 4.12 Stack Status after Exception Handling Ends 5.10 2 Timing of IRQOUT Negation 7.1 Features 105 108 Title amended. Table amended. (Before) Integer division instruction (After) Integer division exception 156 179 Added Description amended. * Way lock function (only for operand cache): Way 2 and way 3 are lockable ... 7.1.1 Cache Structure 179 Description amended. Each of the address and data sections is divided into 128 entries per way. The data section ... Rev. 3.00 Jun. 18, 2008 Page 1139 of 1160 REJ09B0191-0300 Item 7.3.2 Read Access (2) Read Miss Page Revision (See Manual for Details) 190 Description amended. ... The write-back unit is 16 bytes. The update of cache and write-back to memory are performed in wrap around method. For example, the lower four bits of the address at which a read miss occurs indicate H'4, the update of cache and write-back to memory are performed in the order of H'4, H'8, H'C, H'0, which are the lower four bits of the address. 191 Description amended. ... The write-back unit is 16 bytes. The update of cache and write-back to memory are performed in wrap around method. For example, the lower four bits of the address at which a write miss occurs indicate H'4, the update of cache and write-back to memory are performed in the order of H'4, H'8, H'C, H'0, which are the lower four bits of the address. 194, 195 Description amended. ... U bit of that entry. The write-back to memory is performed in the order of H'0, H'4, H'8, H'C, which are the lower four bits of the address. Description amended. ... U bit of that entry. The write-back to memory is performed in the order of H'0, H'4, H'8, H'C, which are the lower four bits of the address. 198 204 Description of 1. replaced. Table amended. Internal Address H'00000000 to H'03FFFFFF H'20000000 to H'23FFFFFF 7.3.4 Write Operation (Only for Operand Cache) (2) Write Miss 7.4.1 Address Array (2) Address-Array Write (NonAssociative Operation) (3) Address-Array Write (Associative Operation) 195 7.4.4 Notes 8.3 Area Overview 8.3.1 Address Map Table 8.2 Address Map Space CS0 CS0 Memory to be Connected Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) Cache Cache-enabled Cache-disabled 8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 8) (1) Normal Space, SRAM with Byte Selection, MPX-I/O 216 Figure amended. 21 - 20 - 19 - 0 R/W 0 R/W 0 R Rev. 3.00 Jun. 18, 2008 Page 1140 of 1160 REJ09B0191-0300 Item 8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 8) (1) Normal Space, SRAM with Byte Selection, MPX-I/O Page Revision (See Manual for Details) 216 Table amended. Bit 21, 20 Bit Name Initial Value All 0 R/W R/W Description Reserved Clear these bits to 0 when the interface for normal space or SRAM with byte selection is used. Byte Access Selection when SRAM with Byte Selection is Used Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 20 BAS* 0 R/W 17, 16 * All 0 R/W Reserved Clear these bits to 0 when the interface for normal space or SRAM with byte selection is used. 8.5.6 SDRAM Interface Table 8.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-1 289 Table amended. Setting BSZ [1:0] 10 (16 bits) Output Pin of This LSI A13 A12 A2/3 ROW [1:0] 00 (11 bits) Row Address Output Cycle A21 A20*2 A2/3 COL [1:0] 00 (8 bits) Column Address Output Cycle A21 A20*2 SDRAM Pin A12(BA1) A11(BA ) Function Unused Specifies bank (8) Refreshing (b) Self-Refreshing 312 Description amended. ... Note that the necessary signals such as CKE must be driven even in standby state by setting the HIZCNT bit in CMNCR to 1. When the multiplication rate for the PLL circuit is changed, the CKIO output will become unstable or will be fixed low. For details on the CKIO output, see section 3, Clock Pulse Generator (CPG). The contents of SDRAM can be retained by placing the SDRAM in the self-refresh state before changing the multiplication rate. The self-refresh state is not ... (12) Power-On Sequence 317 Description amended. In order to use SDRAM, mode setting must first be made for SDRAM after the pose interval specified for the SDRAM to be used after powering on. The pose interval should be obtained by a power-on reset generating circuit or software. Rev. 3.00 Jun. 18, 2008 Page 1141 of 1160 REJ09B0191-0300 Item 8.5.7 Burst ROM (Clocked Asynchronous) Interface Figure 8.36 Burst ROM Access Timing (Clocked Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) Page Revision (See Manual for Details) 324 Figure amended. T1 CKIO Tw Tw T2B Twb T2B Twb T2B Twb T2 8.5.12 Wait between Access Cycles Table 8.18 Conditions for Determining Number of Idle Cycles 8.5.14 Others (1) Reset 9.3.4 DMA Channel Control Registers (CHCR) 345 Table amended. Description of [5] Read data transfer cycle amended. (Before) HM[1:0] bits (After) HW[1:0] bits 352 Description amended. ... All control registers are initialized. In software standby, sleep, and ... 369 Description of bit 23 amended. ... This bit is valid only in level detection by CHCR_0 to CHCR_3. ... 371 Description of bit 17 amended. Specifies whether DACK and TEND are output in data read cycle or in data write cycle in dual address mode.In single address mode, DACK and TEND are always output regardless of the specification by this bit.This bit is valid only in CHCR_0 to CHCR_3. This bit is reserved in CHCR_4 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: DACK and TEND are outputs in read cycle (dual address mode) 1: DACK and TEND are outputs in write cycle (dual address mode) 9.5 Usage Notes 407 Added Rev. 3.00 Jun. 18, 2008 Page 1142 of 1160 REJ09B0191-0300 Item Page Revision (See Manual for Details) Added 9.5.1 Setting of the Half-End Flag 407 and Generation of the Half-End Interrupt 9.5.2 Timing of DACK and TEND Outputs 9.5.3 DREQ Sampling Figure 9.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection when DACK is Split to 4 Due to Idia Cycles Figure 9.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection when DACK is Split to 2 Due to Idia Cycles Figure 9.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection when DACK is Split to 4 Due to Idia Cycles Figure 9.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection when DACK is Split to 2 Due to Idia Cycles 10.1 Features Table 10.1 MTU2 Functions 10.3.5 Timer Interrupt Enable Register (TIER) 455 407 407, 408 409 Added Added Added 409 Added 410 Added 411 Added 415 Channel 5 of DMAC activation amended. (Before) TGR compare match or input capture (After) -- * TIER_5 Description of bit 2 amended. (Before) Enables or disables interrupt requests (TGIU_5) by compare match between TCNTU_5 and TGRU_5. (After) Enables or disables interrupt requests (TGIU_5) by the CMFU5 bit when the CMFU5 bit in TSR_5 is set to 1. Rev. 3.00 Jun. 18, 2008 Page 1143 of 1160 REJ09B0191-0300 Item 10.3.5 Timer Interrupt Enable Register (TIER) Page Revision (See Manual for Details) 455 * TIER_5 Description of bit 1 amended. (Before) Enables or disables interrupt requests (TGIV_5) by compare match between TCNTV_5 and TGRV_5. (After) Enables or disables interrupt requests (TGIV_5) by the CMFV5 bit when the CMFV5 bit in TSR_5 is set to 1. 455 * TIER_5 Description of bit 0 amended. (Before) Enables or disables interrupt requests (TGIW_5) by compare match between TCNTW_5 and TGRW_5. (After) Enables or disables interrupt requests (TGIW_5) by the CMFW5 bit when the CMFW5 bit in TSR_5 is set to 1. 10.3.6 Timer Status Register (TSR) 461, 462 * TSR_5 Description of bits 2 and 1 amended. ... input capture or compare match. Only 0 can be written, for flag clearing. [Setting condition] * When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control registers U_5, V_5, and W_5 (TIORU_5, TIORV_5, and TIORW_5).*2 10.5.3 A/D Converter Activation (3) A/D Converter Activation by A/D Converter Start Request Delaying Function 598 Description amended. The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1 ... Rev. 3.00 Jun. 18, 2008 Page 1144 of 1160 REJ09B0191-0300 Item 13.2.3 Compare Match Counter (CMCNT) Page Revision (See Manual for Details) 704 Description amended. ... When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT is initialized to H'0000 when the corresponding count start bit for a channel in the compare match timer start register (CMSTR) is cleared from 1 to 0. CMCNT is initialized to H'0000 by a power-on reset or in software standby mode, but retains its previous value in module standby mode. 14.3.2 Watchdog Timer 716 Control/Status Register (WTCSR) Description amended. Bit 2 to 0 Bit Name CKS[2:0] Initial Value 000 R/W R/W Description Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (Pf). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (Pf) is 33 MHz. Bits 2 to 0 000: 001: 010: 011: 100: 101: 110: 111: Clock Ratio 1 x P 1/64 x P 1/128 x P 1/256 x P 1/512 x P 1/1024 x P 1/4096 x P 1/16384 x P Overflow Cycle 7.7 s 500 s 1.0 ms 2.0 ms 4.0 ms 8.0 ms 32 ms 128 ms 14.5.3 Interval Timer Overflow Flag 725 Added Section number amended. Section number amended. Description of bit 3 amended. Note: * Regardless of the input value, CTS level and RTS level have no effect on the transmit operation and the receive operation. Description amended. 5. When modem control is enabled in channel 3, the RTS signal is output according to the empty situation of SCFRDR. 14.5.4 System Reset by WDTOVF 726 Signal 14.5.5 Manual Reset in Watchdog 726 Timer Mode 15.3.9 FIFO Control Register (SCFCR) 758 15.4.2 Operation in Asynchronous 776 Mode (3) Transmitting and Receiving Data Rev. 3.00 Jun. 18, 2008 Page 1145 of 1160 REJ09B0191-0300 Item 15.4.3 Operation in Clocked Synchronous Mode (3) Transmitting and Receiving Data Figure 15.13 Sample Flowchart for Transmitting Serial Data Page Revision (See Manual for Details) 780 Figure amended. Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0 after reading 1. [1] [2] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE Read TDFE flag in SCFSR No TDFE = 1? Yes Write transmit data to SCFTDR and clear TDFE and TEND flags in SCFSR to 0 after reading 1 All data transmitted? Yes [2] No 15.4.3 Operation in Clocked Synchronous Mode (3) Transmitting and Receiving Data Figure 15.18 Sample Flowchart for Transmitting/Receiving Serial Data 785 Figure amended. Initialization [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0 after reading 1. The transition of the TDFE flag from 0 to 1 can also be identified by a transmit FIFO data empty Start of transmission and reception Read TDFE flag in SCFSR interrupt (TXI). No TDFE = 1? Yes Write transmit data to SCFTDR, and clear TDFE and TEND flags in SCFSR to 0 after reading 1 [1] [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. 16.3.1 I2C Bus Control Register 1 (ICCR1) 16.3.2 I2C Bus Control Register 2 (ICCR2) 795 Description of bit 7 amended. 0: This module is halted. (SCL and SDA pins function as ports.) 799 Description of bit 1 amended. Resets bits BC[2:0] in ICMR and IIC3 internal circuits. If this bit is set to 1 when hang-up occurs because of communication failure during I2C bus operation, bits BC[2:0] in ICMR and IIC3 internal circuits can be reset. 16.3.3 I2C Bus Mode Register (ICMR) 801 Description of bits 2 to 0 amended. ... The value returns to B'000 at the end of a data transfer, including the acknowledge bit. And the value becomes B'111 automatically after the stop condition detection. These bits are cleared by a power-on reset and in software standby mode and module standby mode. ... Rev. 3.00 Jun. 18, 2008 Page 1146 of 1160 REJ09B0191-0300 Item 16.6 Bit Synchronous Circuit Figure 16.22 Bit Synchronous Circuit Timing Table 16.5 Time for Monitoring SCL Page Revision (See Manual for Details) 831 Figure replaced. 832 Table amended, note*1 deleted. CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 9 tpcyc* 21 tpcyc* 33 tpcyc* 81 tpcyc* Note : * tpcyc indicates the freguency of the peripheral clock (P). 16.7.1 Note on Issue of Stop/Start 833 Conditions 16.7.2 Settings for Multi-Master Operation 16.7.3 Note on Master Receive Mode 16.7.4 Note on Setting ACKBT in Master Receive Mode 833 833 834 Title added. Added. Added. Added. Added. 16.7.5 Note on the States of Bits 834 MST and TRN when Arbitration is Lost 17.1 Features Figure 17.1 Block Diagram of A/D Converter 836 Figure amended. ADC0 AVCC AVref AVSS 10-bit D/A ADC1 AVCC AVref AVSS 10-bit D/A Rev. 3.00 Jun. 18, 2008 Page 1147 of 1160 REJ09B0191-0300 Item 17.7.7 Note on Usage in Scan Mode and Multi Mode 19.3.2 Port F Table 19.15 Switching Pin Function of PF6/AN6/DA0 and PF7/AN7/DA1 20.1 Features Page Revision (See Manual for Details) 861 943 Added. Table replaced. 945 Description amended. 2. The following pins in this LSI have weak keeper circuits that prevent the pins from floating into intermediate voltage levels. ... If the pull-up or pull-down resistors become necessary to fix the pin level, use the resistor of 10 k or smaller. 20.6 Port E Figure 20.5 Port E 966 Figure amended. PE13 (I/O) / TIOC4B (I/O) / MRES (input) PE12 (I/O) / TIOC4A (I/O) / TxD3 (output) PE11 (I/O) / TIOC3D (I/O) / RxD3 (input) / CTS3 (I/O) 22.3.2 Software Standby Mode (3) Note on Release from Software Standby Mode 22.4.1 Note on Writing to Registers 23.5 Usage Notes 992 Added. 995 Title added. 1004 Description amended. 4. When the TDO change timing switch command is set and the TRST pin is asserted immediately after and the RES pin is negated, the TDO change timing switch command may be cleared. To prevent this, make sure to put 20 tcyc or more between the signal change timing of the RES and TRST pins when the TDO change timing switch command is set. For details, see section 23.4.3, TDO Output Timing. 24.2 Register Bits 1025 Bit 20 of CS0WCR in BSC amended. (Before) BAS (After) 1040 Bit 0 of TOCR1S in MTU2S amended. (Before) PLSP (After) OLSP Rev. 3.00 Jun. 18, 2008 Page 1148 of 1160 REJ09B0191-0300 Item 24.3 Register States in Each Operating Mode Page Revision (See Manual for Details) 1056 Settings in software standby mode in MTU2 and to MTU2S amended. 1061 (Before) Initialized (After) Retained 1069 Table amended. Item Input leakage current All input pins (except PB2, PB3) PB2, PB3 Symbol Min. Typ. Max. Unit Test Conditions Vin = 0.5 to PVCC - 0.5 V 25.3 DC Characteristics Table 25.3 DC Characteristics (1) [Common Items] |Iin | 1.0 1.0 A A 25.4.2 Control Signal Timing Table 25.7 Control Signal Timing 1077 Table amended. B = 66.67MHz Item Symbol Min. Max. Unit Figure Figure 25.11 BREQ setup time BREQ hold time BACK delay time Bus buffer off time 1 Bus buffer off time 2 Bus buffer on time 1 Bus buffer on time 2 BACK setup time for bus buffer off tBREQS tBREQH tBACKD tBOFF1 tBOFF2 tBON1 tBON2 tBACKS 1/2tcyc + 7 1/2tcyc + 2 1/2tcyc + 13 15 15 15 15 ns ns ns ns ns ns ns ns 0 Figure 25.11 Bus Release Timing 1079 Figure amended. tBACKD BACK tBACKS tBOFF1 A25 to A0, D31 to D0 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, CKE tBOFF2 25.4.3 Bus Timing Table 25.8 Bus Timing 1080 Table condition amended. Conditions: Clock mode 2/7, PVCC = 3.0 V to 3.6 V, PVSS = 0 V, Ta = -20C to +85C Rev. 3.00 Jun. 18, 2008 Page 1149 of 1160 REJ09B0191-0300 Item 25.4.3 Bus Timing Table 25.8 Bus Timing Page Revision (See Manual for Details) 1080 Table amended. to 1082 Item Chip enable setup time WAIT setup time WAIT hold time Address setup time for AH DACK, TEND delay time B = 66.66MHz*4 Symbol tCS Min. 0 1/2tcyc + 7.5 Max. Unit ns Figure Figures 25.12 to 25.15, 25.20 tWTS ns Figures 25.13 to 25.20, 25.41, 25.43 Figures 25.13 to 25.20, 25.41, 25.43 Figures 25.16 tWTH 1/2tcyc + 3.5 ns tAVVH tDACD 1/2tcyc - 2 Refer to peripheral modules ns ns Refer to peripheral modules Figures 25.12 to 25.34, 25.38, 25.40 to 25.43 1082 Note added. Note: 4. 1/2 tcyc indicated in minimum and maximum values for the item of delay, setup, and hold times represents a half cycle from the rising edge with a clock. That is, 1/2 tcyc describes a reference of the falling edge with a clock. Figure 25.12 Basic Bus Timing for 1083 Figure amended. Normal Space (No Wait) tCSD1 tCSD1 CSn tCS Figure 25.13 Basic Bus Timing for 1084 Figure amended. Normal Space (One Software Wait Cycle) t CSD1 tCSD1 CSn tCS Figure 25.14 Basic Bus Timing for 1085 Figure amended. Normal Space (One External Wait t Cycle) CSD1 tCSD1 CSn tCS Rev. 3.00 Jun. 18, 2008 Page 1150 of 1160 REJ09B0191-0300 Item 25.4.3 Bus Timing Figure 25.15 Basic Bus Timing for Normal Space (One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle) Page Revision (See Manual for Details) 1086 Figure amended. AS tCSD1 tCSD1 tCSD1 tCSD1 CSn tRWD1 tCS tRWD1 tCS tRWD1 tRWD1 Figure 25.16 MPX-I/O Interface 1087 Figure amended. Bus Cycle (Three Address Cycles, One Software Wait Cycle, One AH External Wait Cycle) tAHD tAHD tAHD tRSD tRSD tRDH1 RD Read D15 to D0 tMAD tMAH tRDS1 Data Address tAVVH tWED1 tWED1 WE1, WE0 Write D15 to D0 tBSD tBSD tAVVH tMAD tWDD1 tMAH tWDH4 tWDH1 Address Data BS Figure 25.41 PCMCIA Memory 1112 Figure amended. Card Bus Cycle (TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, Hardware Wait Cycle 1) WE tWED1 tWED1 White tWDD1 tWDH1 D15 to D0 t t Figure 25.43 PCMCIA I/O Card 1114 Figure amended. Bus Cycle (TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, ICIOWR t White Hardware Wait Cycle 1) WDD1 ICWSD tICWSD tWDH1 D15 to D0 25.4.5 DMAC Module Timing Table 25.10 DMAC Module Timing 1115 Table amended. Item DACK, TEND delay time 1119 Table amended. Item Transmit data delay time (clocked synchronous) Receive data hold time (clocked synchronous) Min. -- 1tpcyc + 15 Unit ns ns Min. 0 Max. 13 25.4.9 SCIF Module Timing Table 25.14 SCIF Module Timing Rev. 3.00 Jun. 18, 2008 Page 1151 of 1160 REJ09B0191-0300 Item A. Pin States Table A.1 Pin States Page Revision (See Manual for Details) 1132 Table amended. Pin Function Reset State Power-On*7 Area 0 Data Bus Width Type Emulator Pin Name AUDSYNC*8 AUDCK*8 AUDATA3 to AUDATA0*8 ASEMD ASEBCK*8 ASEBRKAK/ ASEBRK*8 Pin State Power-Down State 8 Bits 16 Bits I Z Z 32 Bits Manual I Z Z Software Standby I Z Z Sleep I Z Z Bus Mastership Release I Z Z 1133 Notes amended. Notes: 6. The EXTAL pin must be fixed (pulled up/pulled down/connected to power supply/connected to ground) and the XTAL pin must be open. 8. These are the pin states in product chip mode (ASEMD = H). See the Emulation Manual for the pin states in ASE mode (ASEMD = L). Rev. 3.00 Jun. 18, 2008 Page 1152 of 1160 REJ09B0191-0300 Index Numerics 16-bit/32-bit displacement ........................ 39 B Bank active ............................................. 303 Banked register and input/output of banks ....................................................... 150 Bit manipulation instructions .................... 66 Bit synchronous circuit ........................... 830 Block diagram............................................. 7 Branch instructions ................................... 63 Break detection and processing............... 788 Break on data access cycle...................... 173 Break on instruction fetch cycle.............. 172 Burst mode.............................................. 400 Burst MPX-I/O interface......................... 337 Burst read................................................ 295 Burst ROM (clocked asynchronous) interface .................................................. 323 Burst ROM (clocked synchronous) interface .................................................. 342 Burst write............................................... 300 Bus arbitration......................................... 350 Bus state controller (BSC) ...................... 199 Bus timing............................................. 1080 Bus-released state...................................... 68 A A/D conversion time (multi mode and scan mode)................... 855 A/D conversion time (single mode)........ 854 A/D conversion timing ........................... 854 A/D converter (ADC) ............................. 835 A/D converter activation......................... 597 A/D converter characteristics................ 1126 A/D converter start request delaying function................................................... 579 A/D trigger input timing ....................... 1121 Absolute address....................................... 39 Absolute address accessing....................... 39 Absolute maximum ratings................... 1067 AC characteristics................................. 1073 AC characteristics measurement conditions ............................................. 1125 Access size and data alignment .............. 264 Access wait control................................. 272 Address array.................................. 180, 194 Address array read .................................. 194 Address errors........................................... 97 Address map ........................................... 204 Address multiplexing.............................. 283 Address-array write (associative operation) ............................ 195 Address-array write (non-associative operation)..................... 194 Addressing modes..................................... 40 Analog input pin ratings ......................... 860 Arithmetic operation instructions ............. 58 Auto-refreshing....................................... 310 Auto-request mode ................................. 387 C Cache ...................................................... 179 Calculating exception handling vector table addresses .......................................... 92 Canceling software standby mode (WDT)..................................................... 720 Cascaded operation ................................. 514 Caution on period setting ........................ 612 Changing the division ratio ....................... 84 Changing the frequency .................... 83, 721 Changing the multiplication rate............... 83 Clock frequency control circuit................. 71 Rev. 3.00 Jun. 18, 2008 Page 1153 of 1160 REJ09B0191-0300 Clock operating modes ............................. 74 Clock pulse generator (CPG).................... 69 Clock timing ......................................... 1074 Clocked synchronous serial format ........ 820 CMCNT count timing............................. 705 Coherency of cache and external memory................................................... 193 Compare match timer (CMT) ................. 699 Complementary PWM mode .................. 534 Conditions for determining number of idle cycles ............................................... 344 Conflict between byte-write and count-up processes of CMCNT .............. 710 Conflict between word-write and count-up processes of CMCNT .............. 709 Conflict between write and compare-match processes of CMCNT.... 708 Control signal timing ............................ 1077 CPU .......................................................... 29 Crystal oscillator....................................... 71 CSn assert period expansion................... 274 Cycle steal mode..................................... 398 Definitions of A/D conversion accuracy .................................................. 857 Delayed branch instructions...................... 37 Direct memory access controller (DMAC).................................................. 357 Displacement accessing ............................ 39 Divider 1 ................................................... 71 Divider 2 ................................................... 71 DMA transfer flowchart.......................... 386 DMAC activation.................................... 596 DMAC module timing .......................... 1115 DREQ pin sampling timing .................... 403 Dual address mode.................................. 395 E Effective address calculation .................... 40 Electrical characteristics ....................... 1067 Endian ..................................................... 264 Equation for getting SCBRR value......... 749 Exception handling ................................... 87 Exception handling state ........................... 68 Exception handling vector table................ 91 Exception source generation immediately after delayed branch instruction ............................................... 106 Exceptions triggered by instructions....... 103 External pulse width measurement ......... 589 External request mode............................. 387 External trigger input timing................... 855 D D/A converter (DAC) ............................. 863 D/A converter characteristics ............... 1127 D/A output hold function in software standby mode.......................................... 869 Data array ....................................... 180, 195 Data array read ....................................... 195 Data array write ...................................... 195 Data format in registers ............................ 34 Data formats in memory ........................... 34 Data transfer instructions.......................... 54 Data transfer with interrupt request signals..................................................... 154 DC characteristics................................. 1069 Dead time compensation ........................ 590 Deep power-down mode......................... 322 Rev. 3.00 Jun. 18, 2008 Page 1154 of 1160 REJ09B0191-0300 F Fixed mode ............................................. 391 Full-scale error........................................ 857 G General illegal instructions ..................... 104 General registers ....................................... 29 Global base register (GBR) ...................... 31 L Load-store architecture ............................. 36 Logic operation instructions...................... 61 Low-frequency mode .............................. 315 Low-power SDRAM............................... 320 LRU ........................................................ 181 H High-performance user debugging interface (H-UDI) ................................... 997 H-UDI commands................................. 1000 H-UDI interrupt ............................ 127, 1003 H-UDI related pin timing...................... 1123 H-UDI reset .......................................... 1003 M Manual reset.............................................. 96 Master receive operation......................... 813 Master transmit operation ....................... 811 Memory-mapped cache........................... 194 Module standby function ........................ 994 MPX-I/O interface .................................. 275 MTU2 functions...................................... 414 MTU2 interrupts ..................................... 595 MTU2 output pin initialization ............... 627 MTU2, MTU2S module timing ............ 1117 MTU2-MTU2S synchronous operation ................................................. 583 MTU2S functions.................................... 660 Multi mode.............................................. 848 Multi-function timer pulse unit 2 (MTU2)................................................... 413 Multi-function timer pulse unit 2S (MTU2S)................................................. 659 Multiplexed pins (port A) ....................... 871 Multiplexed pins (port B)........................ 872 Multiplexed pins (port C)........................ 872 Multiplexed pins (port D) ....................... 873 Multiplexed pins (port E)........................ 874 Multiplexed pins (port F) ........................ 875 Multiply and accumulate register high (MACH).................................................... 32 Multiply and accumulate register low (MACL) .................................................... 32 Multiply/Multiply-and-accumulate operations.................................................. 37 I I/O port timing ...................................... 1122 I/O ports.................................................. 945 I2C bus format......................................... 810 I2C bus interface 3 (IIC3) ....................... 791 IIC3 module timing .............................. 1120 Immediate data ......................................... 38 Immediate data accessing ......................... 38 Immediate data format.............................. 35 Initial values of control registers .............. 33 Initial values of general registers .............. 33 Initial values of system registers............... 33 Instruction features ................................... 36 Instruction format ..................................... 45 Instruction set ........................................... 49 Integer division exceptions ..................... 105 Interrupt controller (INTC)..................... 111 Interrupt exception handling................... 102 Interrupt exception handling vectors and priorities ........................................... 131 Interrupt priority level............................. 101 Interrupt response time ........................... 143 IRQ interrupts ......................................... 128 J Jump table base register (TBR) ................ 31 Rev. 3.00 Jun. 18, 2008 Page 1155 of 1160 REJ09B0191-0300 N NMI interrupt.......................................... 127 Noise filter .............................................. 824 Nonlinearity error ................................... 857 Normal space interface ........................... 267 Note on bypass capacitor.......................... 86 Note on using a PLL oscillation circuit .... 86 Note on using an external crystal resonator ................................................... 85 Power-on reset .......................................... 94 Power-on sequence ................................. 317 Prefetch operation (only for operand cache) ......................... 190 Procedure register (PR)............................. 32 Processing of analog input pins .............. 859 Product code ......................................... 1134 Program counter (PC) ............................... 32 Program execution state............................ 68 PWM Modes ........................................... 519 O Offset error ............................................. 857 On-chip peripheral module interrupts..... 129 On-chip peripheral module request ........ 389 On-chip RAM......................................... 975 Operation in asynchronous mode ........... 766 Operation in clocked synchronous mode ....................................................... 777 Output load circuit ................................ 1125 Q Quantization error ................................... 857 R Receive data sampling timing and receive margin (asynchronous mode) ..... 789 Register addresses (by functional module, in order of the corresponding section numbers) ................................... 1006 Register bank error exception handling ............................................ 99, 153 Register bank errors .................................. 99 Register bank exception.......................... 153 Register banks................................... 33, 149 Register bits .......................................... 1021 Register states in each operating mode ..................................................... 1052 Registers ACKEYR............................................ 262 ACSWR .............................................. 261 ADCR ................................................. 844 ADCSR ............................................... 840 ADDRA to ADDRH ........................... 839 BAMR................................................. 162 BAR .................................................... 161 BBR .................................................... 165 BDMR................................................. 164 P Package................................................. 1134 Package dimensions.............................. 1135 Page conflict ........................................... 976 PCMCIA interface.................................. 330 Permissible signal source impedance ..... 860 Pin arrangement.......................................... 8 Pin function controller (PFC) ................. 871 Pin states of this LSI............................. 1129 PINT interrupts....................................... 128 PLL circuit 1............................................. 71 PLL circuit 2............................................. 71 POE2 interrupt source ............................ 697 POE2 module timing ............................ 1118 Port output enable 2 (POE2)................... 667 Power-down mode.................................. 316 Power-down modes ................................ 977 Power-down state ..................................... 68 Rev. 3.00 Jun. 18, 2008 Page 1156 of 1160 REJ09B0191-0300 BDR.................................................... 163 BRCR ................................................. 167 CCR1 .................................................. 182 CCR2 .................................................. 184 CHCR ................................................. 368 CMCNT .............................................. 704 CMCOR.............................................. 704 CMCSR .............................................. 702 CMNCR.............................................. 208 CMSTR............................................... 701 CS0WCR ............................ 216, 233, 251 CS1WCR ............................................ 219 CS2WCR .................................... 222, 239 CS3WCR .................................... 222, 240 CS4WCR .................................... 224, 236 CS5WCR .................................... 227, 244 CS6WCR ............................ 231, 244, 248 CS7WCR ............................................ 219 CS8WCR ............................................ 219 CSnBCR (n = 0 to 8) .......................... 211 DACR ................................................. 866 DADR0............................................... 865 DADR1............................................... 865 DAR.................................................... 366 DMAOR ............................................. 379 DMARS0 to DMARS3....................... 383 DMATCR ........................................... 367 FRQCR ................................................. 79 IBCR................................................... 124 IBNR................................................... 125 ICCR1................................................. 795 ICCR2................................................. 798 ICDRR................................................ 808 ICDRS ................................................ 808 ICDRT ................................................ 807 ICIER.................................................. 802 ICMR.................................................. 800 ICR0 ................................................... 117 ICR1 ................................................... 118 ICR2 ................................................... 119 ICSR.................................................... 804 ICSR1.................................................. 673 ICSR2.................................................. 678 ICSR3.................................................. 683 IFCR.................................................... 936 IPR01, IPR02, IPR05 to IPR14........... 115 IRQRR ................................................ 120 MCLKCR.............................................. 82 NF2CYC ............................................. 809 OCSR1 ................................................ 677 OCSR2 ................................................ 682 PACRH1 ............................................. 882 PACRH2 ............................................. 880 PACRH3 ............................................. 879 PACRL1.............................................. 890 PACRL2.............................................. 888 PACRL3.............................................. 886 PACRL4.............................................. 884 PADRH............................................... 948 PADRL ............................................... 949 PAIORH.............................................. 878 PAIORL .............................................. 878 PAPRH................................................ 951 PAPRL ................................................ 952 PBCR1 ................................................ 895 PBCR2 ................................................ 894 PBCR3 ................................................ 892 PBDR .................................................. 954 PBIOR................................................. 892 PBPR................................................... 956 PCCRL1.............................................. 897 PCDRL................................................ 958 PCIORL .............................................. 897 PCPRL ................................................ 959 PDCRH1 ............................................. 913 PDCRH2 ............................................. 909 PDCRH3 ............................................. 905 PDCRH4 ............................................. 901 PDCRL3.............................................. 922 PDCRL4.............................................. 918 Rev. 3.00 Jun. 18, 2008 Page 1157 of 1160 REJ09B0191-0300 PDDRH .............................................. 962 PDDRL ............................................... 963 PDIORH ............................................. 899 PDIORL.............................................. 900 PDPRH ............................................... 964 PDPRL................................................ 965 PECRH1 ............................................. 927 PECRL1.............................................. 934 PECRL2.............................................. 932 PECRL3.............................................. 930 PECRL4.............................................. 928 PEDRH ............................................... 967 PEDRL ............................................... 968 PEIORH.............................................. 926 PEIORL .............................................. 926 PEPRH................................................ 969 PEPRL ................................................ 970 PFDR .................................................. 972 PINTER .............................................. 122 PIRR ................................................... 123 POECR1 ............................................. 687 POECR2 ............................................. 688 RDAR................................................. 377 RDMATCR ........................................ 378 RSAR.................................................. 376 RTCNT ............................................... 259 RTCOR............................................... 260 RTCSR ............................................... 257 SAR (DMAC)..................................... 365 SAR (IIC3) ......................................... 807 SCBRR ............................................... 749 SCFCR................................................ 756 SCFDR ............................................... 759 SCFRDR............................................. 732 SCFSR ................................................ 741 SCFTDR............................................. 733 SCLSR................................................ 762 SCRSR................................................ 732 SCSCR................................................ 737 SCSMR............................................... 734 Rev. 3.00 Jun. 18, 2008 Page 1158 of 1160 REJ09B0191-0300 SCSPTR.............................................. 760 SCTSR ................................................ 733 SDBPR................................................ 999 SDCR.................................................. 253 SDIR ................................................... 999 SPOER................................................ 685 STBCR................................................ 980 STBCR2.............................................. 981 STBCR3.............................................. 982 STBCR4.............................................. 984 SYSCR1.............................................. 986 SYSCR2.............................................. 988 TADCOBRA_4 .................................. 471 TADCOBRB_4................................... 471 TADCORA_4 ..................................... 471 TADCORB_4 ..................................... 471 TADCR............................................... 468 TBTER................................................ 496 TBTM ................................................. 464 TCBR.................................................. 493 TCDR.................................................. 492 TCNT.................................................. 472 TCNTCMPCLR.................................. 450 TCNTS................................................ 491 TCR..................................................... 424 TCSYSTR........................................... 477 TDDR ................................................. 492 TDER.................................................. 498 TGCR.................................................. 489 TGR .................................................... 472 TICCR................................................. 465 TIER ................................................... 451 TIOR ................................................... 431 TITCNT .............................................. 495 TITCR................................................. 493 TMDR................................................. 428 TOCR1................................................ 482 TOCR2................................................ 485 TOER.................................................. 481 TOLBR ............................................... 488 TRWER .............................................. 480 TSR..................................................... 456 TSTR .................................................. 473 TSYCR ............................................... 466 TSYR.................................................. 475 TWCR................................................. 499 WRCSR .............................................. 717 WTCNT .............................................. 714 WTCSR .............................................. 715 Relationship between access size and number of bursts ..................................... 295 Relationship between clock operating mode and frequency range........................ 75 Relationship between refresh requests and bus cycles......................................... 314 Relationships between register settings and pin functions (port A)....................... 938 Relationships between register settings and pin functions (port B)....................... 939 Relationships between register settings and pin functions (port C)....................... 940 Relationships between register settings and pin functions (port D)....................... 940 Relationships between register settings and pin functions (port E) ....................... 942 Reset state ................................................. 68 Reset-synchronized PWM mode ............ 531 Restoration from bank ............................ 151 Restoration from stack............................ 152 Restriction on DMAC usage................... 788 RISC-type instruction set.......................... 36 Round-robin mode.................................. 391 SDRAM interface ................................... 279 Searching cache ...................................... 188 Self-refreshing ........................................ 312 Sending a break signal ............................ 788 Serial communication interface with FIFO (SCIF)............................................ 727 Setting analog input voltage............ 858, 869 Shift instructions ....................................... 62 Sign extension of word data...................... 36 Simultaneous sampling operation ........... 853 Single address mode ............................... 397 Single mode ............................................ 845 Single read .............................................. 299 Single write ............................................. 302 Slave receive operation ........................... 818 Slave transmit operation.......................... 815 Sleep mode.............................................. 990 Slot illegal instructions ........................... 104 Software standby mode........................... 990 SRAM interface with byte selection ....... 325 Stack after interrupt exception handling .................................................. 142 Stack status after exception handling ends ......................................................... 107 Standby control circuit.............................. 72 Status register (SR) ................................... 30 Supported DMA transfers ....................... 394 Switching Pin Function of PF6/AN6/ DA0 and PF7/AN7/DA1......................... 943 System control instructions....................... 64 T S Saving to bank ........................................ 150 Saving to stack........................................ 152 Scan mode .............................................. 850 SCIF interrupt sources ............................ 786 SCIF module timing ............................. 1119 T bit........................................................... 37 TAP controller ...................................... 1001 TDO output timing................................ 1002 Timing to clear an interrupt source ......... 156 Transfer rate............................................ 797 Trap instructions ..................................... 104 Rev. 3.00 Jun. 18, 2008 Page 1159 of 1160 REJ09B0191-0300 Types of exception handling and priority order.......................................................... 87 V Vector base register (VBR)....................... 31 U UBC trigger timing............................... 1115 Unconditional branch instructions with no delay slot.............................................. 37 User break controller (UBC) .................. 157 User break interrupt ................................ 127 Using interval timer mode ...................... 724 Using watchdog timer mode................... 722 W Wait between access cycles .................... 343 Watchdog timer (WDT).......................... 711 Watchdog timer timing ......................... 1118 Write-back buffer (only for operand cache) ......................... 191 Rev. 3.00 Jun. 18, 2008 Page 1160 of 1160 REJ09B0191-0300 Renesas 32-Bit Single-Chip Microcomputer Hardware Manual SH7206 Group Publication Date: Rev.1.00, Mar. 18, 2005 Rev.3.00, Jun. 18, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.2 SH7206 Group Hardware Manual |
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